1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
|
// SPDX-License-Identifier: GPL-2.0-only
/*
* i.MX9 OCOTP fusebox driver
*
* Copyright 2023 NXP
*/
#include <common.h>
#include <io.h>
#include <linux/nvmem-provider.h>
#include <linux/regmap.h>
#include <mach/imx/ele.h>
#include <machine_id.h>
#define UNIQUE_ID_NUM 4
#define OCOTP_UNIQUE_ID(n) (0xc0 + (n) * 4)
enum fuse_type {
FUSE_FSB = 1,
FUSE_ELE = 2,
FUSE_INVALID = -1
};
struct ocotp_map_entry {
u32 start; /* start word */
u32 num; /* num words */
enum fuse_type type;
};
struct ocotp_devtype_data {
u32 reg_off;
char *name;
u32 size;
u32 num_entry;
u32 flag;
struct ocotp_map_entry *entry;
};
struct imx_ocotp_priv {
struct device *dev;
struct regmap *map;
void __iomem *base;
const struct ocotp_devtype_data *data;
struct regmap_config map_config;
};
static enum fuse_type imx_ocotp_fuse_type(struct imx_ocotp_priv *priv, u32 index)
{
const struct ocotp_devtype_data *data = priv->data;
u32 start, end;
int i;
for (i = 0; i < data->num_entry; i++) {
start = data->entry[i].start;
end = data->entry[i].start + data->entry[i].num;
if (index >= start && index < end)
return data->entry[i].type;
}
return FUSE_INVALID;
}
static int imx_ocotp_reg_read(void *context, unsigned int offset, unsigned int *val)
{
struct imx_ocotp_priv *priv = context;
void __iomem *reg = priv->base + priv->data->reg_off;
u32 index;
enum fuse_type type;
int ret;
u32 fuse_word;
index = offset >> 2;
type = imx_ocotp_fuse_type(priv, index);
switch (type) {
case FUSE_ELE:
ret = ele_read_common_fuse(index, &fuse_word, NULL);
if (ret)
*val = 0xbeefdead;
else
*val = fuse_word;
break;
case FUSE_FSB:
*val = readl_relaxed(reg + (index << 2));
break;
default:
*val = 0xdeadbeef;
break;
}
return 0;
};
static int imx_ocotp_cell_pp(void *context, const char *id, unsigned int offset,
void *data, size_t bytes)
{
/* Deal with some post processing of nvmem cell data */
if (id && !strcmp(id, "mac-address")) {
u8 *buf = data;
if (offset == 0x4ec) {
swap(buf[0], buf[5]);
swap(buf[1], buf[4]);
swap(buf[2], buf[3]);
} else if (offset == 0x4f2) {
swap(buf[0], buf[1]);
swap(buf[2], buf[5]);
swap(buf[3], buf[4]);
} else {
return -EINVAL;
}
}
return 0;
}
static struct regmap_bus imx_ocotp_regmap_bus = {
.reg_read = imx_ocotp_reg_read,
};
static void imx_ocotp_set_unique_machine_id(struct imx_ocotp_priv *priv)
{
uint32_t unique_id_parts[UNIQUE_ID_NUM];
int i;
for (i = 0; i < UNIQUE_ID_NUM; i++)
if (imx_ocotp_reg_read(priv, OCOTP_UNIQUE_ID(i),
&unique_id_parts[i]))
return;
machine_id_set_hashable(unique_id_parts, sizeof(unique_id_parts));
}
static int imx_ele_ocotp_probe(struct device *dev)
{
struct imx_ocotp_priv *priv;
struct nvmem_device *nvmem;
struct resource *iores;
struct ocotp_devtype_data *data;
int ret;
priv = xzalloc(sizeof(*priv));
ret = dev_get_drvdata(dev, (const void **)&data);
if (ret)
return ret;
iores = dev_request_mem_resource(dev, 0);
if (IS_ERR(iores))
return PTR_ERR(iores);
priv->base = IOMEM(iores->start);
priv->data = data;
priv->map_config.reg_bits = 32;
priv->map_config.val_bits = 32;
priv->map_config.reg_stride = 4;
priv->map_config.max_register = priv->data->size - priv->map_config.reg_stride;
priv->map = regmap_init(dev, &imx_ocotp_regmap_bus, priv, &priv->map_config);
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
if (IS_ENABLED(CONFIG_MACHINE_ID))
imx_ocotp_set_unique_machine_id(priv);
nvmem = nvmem_regmap_register_with_pp(priv->map, "imx-ocotp",
imx_ocotp_cell_pp);
if (IS_ERR(nvmem))
return PTR_ERR(nvmem);
return 0;
}
static struct ocotp_map_entry imx93_entries[] = {
{ 0, 52, FUSE_FSB },
{ 63, 1, FUSE_ELE},
{ 128, 16, FUSE_ELE },
{ 182, 1, FUSE_ELE },
{ 188, 1, FUSE_ELE },
{ 312, 200, FUSE_FSB }
};
static const struct ocotp_devtype_data imx93_ocotp_data = {
.reg_off = 0x8000,
.size = 2048,
.num_entry = ARRAY_SIZE(imx93_entries),
.entry = imx93_entries,
};
static const struct of_device_id imx_ele_ocotp_dt_ids[] = {
{ .compatible = "fsl,imx93-ocotp", .data = &imx93_ocotp_data, },
{},
};
MODULE_DEVICE_TABLE(of, imx_ele_ocotp_dt_ids);
static struct driver imx_ele_ocotp_driver = {
.name = "imx_ele_ocotp",
.of_match_table = imx_ele_ocotp_dt_ids,
.probe = imx_ele_ocotp_probe,
};
core_platform_driver(imx_ele_ocotp_driver);
MODULE_DESCRIPTION("i.MX OCOTP/ELE driver");
MODULE_AUTHOR("Peng Fan <peng.fan@nxp.com>");
MODULE_LICENSE("GPL");
|
