1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8qm/qxp Display Pixel Link
maintainers:
- Liu Ying <victor.liu@nxp.com>
description: |
The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
asynchronous linkage between pixel sources(display controller or
camera module) and pixel consumers(imaging or displays).
It consists of two distinct functions, a pixel transfer function and a
control interface. Multiple pixel channels can exist per one control channel.
This binding documentation is only for pixel links whose pixel sources are
display controllers.
The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
firmware.
properties:
compatible:
enum:
- fsl,imx8qm-dc-pixel-link
- fsl,imx8qxp-dc-pixel-link
fsl,dc-id:
$ref: /schemas/types.yaml#/definitions/uint8
description: |
u8 value representing the display controller index that the pixel link
connects to.
fsl,dc-stream-id:
$ref: /schemas/types.yaml#/definitions/uint8
description: |
u8 value representing the display controller stream index that the pixel
link connects to.
enum: [0, 1]
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: The pixel link input port node from upstream video source.
patternProperties:
"^port@[1-4]$":
$ref: /schemas/graph.yaml#/properties/port
description: The pixel link output port node to downstream bridge.
required:
- port@0
- port@1
- port@2
- port@3
- port@4
allOf:
- if:
properties:
compatible:
contains:
const: fsl,imx8qxp-dc-pixel-link
then:
properties:
fsl,dc-id:
const: 0
- if:
properties:
compatible:
contains:
const: fsl,imx8qm-dc-pixel-link
then:
properties:
fsl,dc-id:
enum: [0, 1]
required:
- compatible
- fsl,dc-id
- fsl,dc-stream-id
- ports
additionalProperties: false
examples:
- |
dc0-pixel-link0 {
compatible = "fsl,imx8qxp-dc-pixel-link";
fsl,dc-id = /bits/ 8 <0>;
fsl,dc-stream-id = /bits/ 8 <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
/* from dc0 pixel combiner channel0 */
port@0 {
reg = <0>;
dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint {
remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>;
};
};
/* to PXL2DPIs in MIPI/LVDS combo subsystems */
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
};
dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 {
reg = <1>;
remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
};
};
/* unused */
port@2 {
reg = <2>;
};
/* unused */
port@3 {
reg = <3>;
};
/* to imaging subsystem */
port@4 {
reg = <4>;
};
};
};
|
