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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/qcom,msm8996-qmp-pcie-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm QMP PHY controller (MSM8996 PCIe)
maintainers:
- Vinod Koul <vkoul@kernel.org>
description:
QMP PHY controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
properties:
compatible:
const: qcom,msm8996-qmp-pcie-phy
reg:
items:
- description: serdes
"#address-cells":
enum: [ 1, 2 ]
"#size-cells":
enum: [ 1, 2 ]
ranges: true
clocks:
maxItems: 3
clock-names:
items:
- const: aux
- const: cfg_ahb
- const: ref
resets:
maxItems: 3
reset-names:
items:
- const: phy
- const: common
- const: cfg
vdda-phy-supply: true
vdda-pll-supply: true
vddp-ref-clk-supply: true
patternProperties:
"^phy@[0-9a-f]+$":
type: object
description: one child node per PHY provided by this block
properties:
reg:
items:
- description: TX
- description: RX
- description: PCS
clocks:
items:
- description: PIPE clock
clock-names:
deprecated: true
items:
- enum:
- pipe0
- pipe1
- pipe2
resets:
items:
- description: PHY reset
reset-names:
deprecated: true
items:
- enum:
- lane0
- lane1
- lane2
"#clock-cells":
const: 0
clock-output-names:
maxItems: 1
"#phy-cells":
const: 0
required:
- reg
- clocks
- resets
- "#clock-cells"
- clock-output-names
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- ranges
- clocks
- clock-names
- resets
- reset-names
- vdda-phy-supply
- vdda-pll-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-msm8996.h>
pcie_phy: phy-wrapper@34000 {
compatible = "qcom,msm8996-qmp-pcie-phy";
reg = <0x34000 0x488>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x34000 0x4000>;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_PCIE_PHY_BCR>,
<&gcc GCC_PCIE_PHY_COM_BCR>,
<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
reset-names = "phy", "common", "cfg";
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
pciephy_0: phy@1000 {
reg = <0x1000 0x130>,
<0x1200 0x200>,
<0x1400 0x1dc>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
resets = <&gcc GCC_PCIE_0_PHY_BCR>;
#clock-cells = <0>;
clock-output-names = "pcie_0_pipe_clk_src";
#phy-cells = <0>;
};
pciephy_1: phy@2000 {
reg = <0x2000 0x130>,
<0x2200 0x200>,
<0x2400 0x1dc>;
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
resets = <&gcc GCC_PCIE_1_PHY_BCR>;
#clock-cells = <0>;
clock-output-names = "pcie_1_pipe_clk_src";
#phy-cells = <0>;
};
pciephy_2: phy@3000 {
reg = <0x3000 0x130>,
<0x3200 0x200>,
<0x3400 0x1dc>;
clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
resets = <&gcc GCC_PCIE_2_PHY_BCR>;
#clock-cells = <0>;
clock-output-names = "pcie_2_pipe_clk_src";
#phy-cells = <0>;
};
};
|
