dts/Bindings/phy/rockchip,pcie3-phy.yaml


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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Rockchip PCIe v3 phy

maintainers:
  - Heiko Stuebner <heiko@sntech.de>

properties:
  compatible:
    enum:
      - rockchip,rk3568-pcie3-phy

  reg:
    maxItems: 1

  clocks:
    minItems: 3
    maxItems: 3

  clock-names:
    items:
      - const: refclk_m
      - const: refclk_n
      - const: pclk

  data-lanes:
    description: which lanes (by position) should be mapped to which
      controller (value). 0 means lane disabled, higher value means used.
      (controller-number +1 )
    $ref: /schemas/types.yaml#/definitions/uint32-array
    minItems: 2
    maxItems: 16
    items:
      minimum: 0
      maximum: 16

  "#phy-cells":
    const: 0

  resets:
    maxItems: 1

  reset-names:
    const: phy

  rockchip,phy-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the syscon managing the phy "general register files"

  rockchip,pipe-grf:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to the syscon managing the pipe "general register files"

required:
  - compatible
  - reg
  - rockchip,phy-grf
  - "#phy-cells"

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/rk3568-cru.h>
    pcie30phy: phy@fe8c0000 {
      compatible = "rockchip,rk3568-pcie3-phy";
      reg = <0xfe8c0000 0x20000>;
      #phy-cells = <0>;
      clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
               <&pmucru CLK_PCIE30PHY_REF_N>,
               <&cru PCLK_PCIE30PHY>;
      clock-names = "refclk_m", "refclk_n", "pclk";
      resets = <&cru SRST_PCIE30PHY>;
      reset-names = "phy";
      rockchip,phy-grf = <&pcie30_phy_grf>;
    };