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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
*/
/dts-v1/;
/include/ "zynq-7000.dtsi"
/ {
model = "Ebang EBAZ4205";
compatible = "ebang,ebaz4205", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x10000000>;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&clkc {
ps-clk-frequency = <33333333>;
fclk-enable = <8>;
};
&gem0 {
status = "okay";
phy-mode = "mii";
phy-handle = <&phy>;
/* PHY clock */
assigned-clocks = <&clkc 18>;
assigned-clock-rates = <25000000>;
phy: ethernet-phy@0 {
reg = <0>;
};
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&pinctrl0 {
pinctrl_gpio0_default: gpio0-default {
mux {
groups = "gpio0_20_grp", "gpio0_32_grp";
function = "gpio0";
};
conf {
groups = "gpio0_20_grp", "gpio0_32_grp";
io-standard = <3>;
slew-rate = <0>;
};
conf-pull-up {
pins = "MIO20", "MIO32";
bias-disable;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_2_grp";
function = "sdio0";
};
conf {
groups = "sdio0_2_grp";
io-standard = <3>;
slew-rate = <0>;
bias-disable;
};
mux-cd {
groups = "gpio0_34_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "gpio0_34_grp";
io-standard = <3>;
slew-rate = <0>;
bias-high-impedance;
bias-pull-up;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_4_grp";
function = "uart1";
};
conf {
groups = "uart1_4_grp";
io-standard = <3>;
slew-rate = <0>;
};
conf-rx {
pins = "MIO25";
bias-high-impedance;
};
conf-tx {
pins = "MIO24";
bias-disable;
};
};
};
&sdhci0 {
status = "okay";
disable-wp;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
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