summaryrefslogtreecommitdiffstats
path: root/dts/src/arm64/exynos/exynos5433-tm2e.dts
blob: 7891a31adc17594112a8edf1a9ad4914f3446718 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
/*
 * SAMSUNG Exynos5433 TM2E board device tree source
 *
 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
 *
 * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
 * Samsung Exynos5433 SoC.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "exynos5433-tm2-common.dtsi"

/ {
	model = "Samsung TM2E board";
	compatible = "samsung,tm2e", "samsung,exynos5433";
};

&cmu_disp {
	/*
	 * TM2 and TM2e differ only by DISP_PLL rate, but define all assigned
	 * clocks properties for DISP CMU for each board to keep them together
	 * for easier review and maintenance.
	 */
	assigned-clocks = <&cmu_disp CLK_FOUT_DISP_PLL>,
			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
			  <&cmu_disp CLK_MOUT_ACLK_DISP_333_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DSIM0>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK>,
			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER>,
			  <&cmu_disp CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER>,
			  <&cmu_disp CLK_MOUT_DISP_PLL>,
			  <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
	assigned-clock-parents = <0>, <0>,
				 <&cmu_mif CLK_ACLK_DISP_333>,
				 <&cmu_mif CLK_SCLK_DSIM0_DISP>,
				 <&cmu_disp CLK_MOUT_SCLK_DSIM0_USER>,
				 <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
				 <&cmu_disp CLK_MOUT_SCLK_DECON_ECLK_USER>,
				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY>,
				 <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY>,
				 <&cmu_disp CLK_FOUT_DISP_PLL>,
				 <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
	assigned-clock-rates = <278000000>, <400000000>;
};

&ldo31_reg {
	regulator-name = "TSP_VDD_1.8V_AP";
	regulator-min-microvolt = <1800000>;
	regulator-max-microvolt = <1800000>;
};

&ldo38_reg {
	regulator-name = "VCC_3.3V_MOTOR_AP";
	regulator-min-microvolt = <3300000>;
	regulator-max-microvolt = <3300000>;
};