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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
* Device Tree Source for the RZ/V2M SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r9a09g011-cpg.h>
/ {
compatible = "renesas,r9a09g011";
#address-cells = <2>;
#size-cells = <2>;
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
};
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
};
};
soc: soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic: interrupt-controller@82000000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0x0 0x82010000 0 0x1000>,
<0x0 0x82020000 0 0x20000>,
<0x0 0x82040000 0 0x20000>,
<0x0 0x82060000 0 0x20000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
clock-names = "clk";
};
cpg: clock-controller@a3500000 {
compatible = "renesas,r9a09g011-cpg";
reg = <0 0xa3500000 0 0x1000>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#reset-cells = <1>;
#power-domain-cells = <0>;
};
uart0: serial@a4040000 {
compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
reg = <0 0xa4040000 0 0x80>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
<&cpg CPG_MOD R9A09G011_URT_PCLK>;
clock-names = "sclk", "pclk";
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
};
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