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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
*/
#include "rk356x.dtsi"
/ {
compatible = "rockchip,rk3568";
sata0: sata@fc000000 {
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
reg = <0 0xfc000000 0 0x1000>;
clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>,
<&cru CLK_SATA0_RXOOB>;
clock-names = "sata", "pmalive", "rxoob";
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
phys = <&combphy0 PHY_TYPE_SATA>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
power-domains = <&power RK3568_PD_PIPE>;
status = "disabled";
};
pipe_phy_grf0: syscon@fdc70000 {
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
reg = <0x0 0xfdc70000 0x0 0x1000>;
};
qos_pcie3x1: qos@fe190080 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190080 0x0 0x20>;
};
qos_pcie3x2: qos@fe190100 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190100 0x0 0x20>;
};
qos_sata0: qos@fe190200 {
compatible = "rockchip,rk3568-qos", "syscon";
reg = <0x0 0xfe190200 0x0 0x20>;
};
gmac0: ethernet@fe2a0000 {
compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
reg = <0x0 0xfe2a0000 0x0 0x10000>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "eth_wake_irq";
clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
<&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
<&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
clock-names = "stmmaceth", "mac_clk_rx",
"mac_clk_tx", "clk_mac_refout",
"aclk_mac", "pclk_mac",
"clk_mac_speed", "ptp_ref";
resets = <&cru SRST_A_GMAC0>;
reset-names = "stmmaceth";
rockchip,grf = <&grf>;
snps,axi-config = <&gmac0_stmmac_axi_setup>;
snps,mixed-burst;
snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
snps,tso;
status = "disabled";
mdio0: mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <0x1>;
#size-cells = <0x0>;
};
gmac0_stmmac_axi_setup: stmmac-axi-config {
snps,blen = <0 0 0 0 16 8 4>;
snps,rd_osr_lmt = <8>;
snps,wr_osr_lmt = <4>;
};
gmac0_mtl_rx_setup: rx-queues-config {
snps,rx-queues-to-use = <1>;
queue0 {};
};
gmac0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
queue0 {};
};
};
combphy0: phy@fe820000 {
compatible = "rockchip,rk3568-naneng-combphy";
reg = <0x0 0xfe820000 0x0 0x100>;
clocks = <&pmucru CLK_PCIEPHY0_REF>,
<&cru PCLK_PIPEPHY0>,
<&cru PCLK_PIPE>;
clock-names = "ref", "apb", "pipe";
assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
assigned-clock-rates = <100000000>;
resets = <&cru SRST_PIPEPHY0>;
rockchip,pipe-grf = <&pipegrf>;
rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
#phy-cells = <1>;
status = "disabled";
};
};
&cpu0_opp_table {
opp-1992000000 {
opp-hz = /bits/ 64 <1992000000>;
opp-microvolt = <1150000 1150000 1150000>;
};
};
&pipegrf {
compatible = "rockchip,rk3568-pipe-grf", "syscon";
};
&power {
power-domain@RK3568_PD_PIPE {
reg = <RK3568_PD_PIPE>;
clocks = <&cru PCLK_PIPE>;
pm_qos = <&qos_pcie2x1>,
<&qos_pcie3x1>,
<&qos_pcie3x2>,
<&qos_sata0>,
<&qos_sata1>,
<&qos_sata2>,
<&qos_usb3_0>,
<&qos_usb3_1>;
#power-domain-cells = <0>;
};
};
&usb_host0_xhci {
phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
phy-names = "usb2-phy", "usb3-phy";
};
&vop {
compatible = "rockchip,rk3568-vop";
};
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