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Diffstat (limited to 'dts/Bindings/riscv/extensions.yaml')
| -rw-r--r-- | dts/Bindings/riscv/extensions.yaml | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/dts/Bindings/riscv/extensions.yaml b/dts/Bindings/riscv/extensions.yaml index cc1f546fdb..c91ab0e466 100644 --- a/dts/Bindings/riscv/extensions.yaml +++ b/dts/Bindings/riscv/extensions.yaml @@ -128,6 +128,12 @@ properties: changes to interrupts as frozen at commit ccbddab ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. + - const: smstateen + description: | + The standard Smstateen extension for controlling access to CSRs + added by other RISC-V extensions in H/S/VS/U/VU modes and as + ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable. + - const: ssaia description: | The standard Ssaia supervisor-level extension for the advanced @@ -212,6 +218,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1f9 + ("Add changes requested by Ved during signoff") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status register |