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| author | Lucas Stach <l.stach@pengutronix.de> | 2024-01-25 18:29:27 +0100 |
|---|---|---|
| committer | Lucas Stach <l.stach@pengutronix.de> | 2024-01-25 18:29:27 +0100 |
| commit | 9b68e0cdba04895167464f5e20c1c9c851aca422 (patch) | |
| tree | 7ccfa22baa96a859101b04ca668761bcbb3a85fd | |
| parent | 6613476e225e090cc9aad49be7fa504e290dd33d (diff) | |
| download | linux-0-day-irq-barriers.tar.gz linux-0-day-irq-barriers.tar.xz | |
genirq: use relaxed access by default for irq_reg_{readl,writel}irq-barriers
irqchip access does not require any memory ordering between other
in-flight transactions and the IRQ controller peripheral access.
As all architectures now implement the relaxed MMIO accessors we
can switch the irq_reg_{readl,writel} helpers to used them, in
order to avoid potentially costly barriers in the IRQ handling
hotpath.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
| -rw-r--r-- | include/linux/irq.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/include/linux/irq.h b/include/linux/irq.h index 90081afa10ce5..fa1597db78873 100644 --- a/include/linux/irq.h +++ b/include/linux/irq.h @@ -1218,7 +1218,7 @@ static inline void irq_reg_writel(struct irq_chip_generic *gc, if (gc->reg_writel) gc->reg_writel(val, gc->reg_base + reg_offset); else - writel(val, gc->reg_base + reg_offset); + writel_relaxed(val, gc->reg_base + reg_offset); } static inline u32 irq_reg_readl(struct irq_chip_generic *gc, @@ -1227,7 +1227,7 @@ static inline u32 irq_reg_readl(struct irq_chip_generic *gc, if (gc->reg_readl) return gc->reg_readl(gc->reg_base + reg_offset); else - return readl(gc->reg_base + reg_offset); + return readl_relaxed(gc->reg_base + reg_offset); } struct irq_matrix; |