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| author | Paul Burton <paul.burton@imgtec.com> | 2016-02-03 16:17:29 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2016-05-13 14:01:53 +0200 |
| commit | 1dbf6a81c845a748e46b4bcaf25d958038624ad8 (patch) | |
| tree | a917546c842760c489b45bf620cbc68d90e2abbf | |
| parent | df8b1a5ee9f7f5fbb5e8f0df9537c648481019ea (diff) | |
| download | linux-0-day-1dbf6a81c845a748e46b4bcaf25d958038624ad8.tar.gz linux-0-day-1dbf6a81c845a748e46b4bcaf25d958038624ad8.tar.xz | |
MIPS: Add M6250 cases to CPU switch statements
Add casses supporting the M6250 CPU to various switch statements in the
core MIPS kernel code that define behaviour dependent upon the CPU.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: Joshua Kinard <kumba@gentoo.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12374/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/cpu-type.h | 4 | ||||
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h index 2cb0979b5dc5a..fbe1881f28fca 100644 --- a/arch/mips/include/asm/cpu-type.h +++ b/arch/mips/include/asm/cpu-type.h @@ -77,6 +77,10 @@ static inline int __pure __get_cpu_type(const int cpu_type) */ #endif +#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R6 + case CPU_M6250: +#endif + #ifdef CONFIG_SYS_HAS_CPU_MIPS64_R6 case CPU_I6400: case CPU_P6600: diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 729a7d48ceee8..e64d595fdcf2c 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1286,6 +1286,7 @@ static void probe_pcache(void) case CPU_QEMU_GENERIC: case CPU_I6400: case CPU_P6600: + case CPU_M6250: if (!(read_c0_config7() & MIPS_CONF7_IAR) && (c->icache.waysize > PAGE_SIZE)) c->icache.flags |= MIPS_CACHE_ALIASES; |