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| author | Will Deacon <will.deacon@arm.com> | 2013-09-04 12:30:08 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2014-10-20 18:49:18 +0100 |
| commit | a8e0aead70b4af957e6b27b82fba849c6179b707 (patch) | |
| tree | 2127e811b50ddf23f21ae678abc129b34e52ded7 /Documentation/memory-barriers.txt | |
| parent | cbc908ef8e6babc40cb929f46ea1b8a26cbdbce0 (diff) | |
| download | linux-0-day-a8e0aead70b4af957e6b27b82fba849c6179b707.tar.gz linux-0-day-a8e0aead70b4af957e6b27b82fba849c6179b707.tar.xz | |
documentation: memory-barriers: clarify relaxed io accessor semantics
This patch extends the paragraph describing the relaxed read io accessors
so that the relaxed accessors are defined to be:
- Ordered with respect to each other if accessing the same peripheral
- Unordered with respect to normal memory accesses
- Unordered with respect to LOCK/UNLOCK operations
Whilst many architectures will provide stricter semantics, ARM, Alpha and
PPC can achieve significant performance gains by taking advantage of some
or all of the above relaxations.
Cc: Randy Dunlap <rdunlap@infradead.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: David Howells <dhowells@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/memory-barriers.txt')
| -rw-r--r-- | Documentation/memory-barriers.txt | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index 22a969cdd4766..4af4cea8cff04 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -2465,10 +2465,15 @@ functions: Please refer to the PCI specification for more information on interactions between PCI transactions. - (*) readX_relaxed() - - These are similar to readX(), but are not guaranteed to be ordered in any - way. Be aware that there is no I/O read barrier available. + (*) readX_relaxed(), writeX_relaxed() + + These are similar to readX() and writeX(), but provide weaker memory + ordering guarantees. Specifically, they do not guarantee ordering with + respect to normal memory accesses (e.g. DMA buffers) nor do they guarantee + ordering with respect to LOCK or UNLOCK operations. If the latter is + required, an mmiowb() barrier can be used. Note that relaxed accesses to + the same peripheral are guaranteed to be ordered with respect to each + other. (*) ioreadX(), iowriteX() |