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| author | Michael Witten <mfwitten@gmail.com> | 2011-08-29 17:34:00 +0000 |
|---|---|---|
| committer | Michael Witten <mfwitten@gmail.com> | 2011-08-29 20:00:26 +0000 |
| commit | b8c6e0fe46fcd60f58089365dd96dcf04f95263b (patch) | |
| tree | 1077ce0b3bca01ac8ea05d3d51bb808601e6de94 /Documentation | |
| parent | 2d43f5d667273ba4975cb79782a46aa374dd8607 (diff) | |
| download | linux-0-day-b8c6e0fe46fcd60f58089365dd96dcf04f95263b.tar.gz linux-0-day-b8c6e0fe46fcd60f58089365dd96dcf04f95263b.tar.xz | |
DocBook/drm: Refer to the domain-setting function as a device-specific ioctl
Signed-off-by: Michael Witten <mfwitten@gmail.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/DocBook/drm.tmpl | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index ba20f9fbb62b7..9ae328aa1dd3b 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -724,11 +724,11 @@ void intel_crt_init(struct drm_device *dev) has finished rendering to the object, then the object must be made coherent with the CPU's view of memory, usually involving GPU cache flushing of various kinds. - This core CPU<->GPU coherency management is provided by the GEM - set domain function, which evaluates an object's current domain and + This core CPU<->GPU coherency management is provided by a + device-specific ioctl, which evaluates an object's current domain and performs any necessary flushing or synchronization to put the object into the desired coherency domain (note that the object may be busy, - i.e. an active render target; in that case, the set domain function + i.e. an active render target; in that case, setting the domain blocks the client and waits for rendering to complete before performing any necessary flushing operations). </para> |