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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2017-03-22 09:06:58 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2017-04-01 21:12:20 +1100 |
| commit | 957b778a166e32e242a33fdab693ffb256a19cbd (patch) | |
| tree | e4ffce7347a62e55ac2cd99b3efdb2e62c7cf070 /arch/powerpc/include/asm/book3s/64/mmu.h | |
| parent | f6eedbba7a26fdaee9ea8121336dc86236c136c7 (diff) | |
| download | linux-0-day-957b778a166e32e242a33fdab693ffb256a19cbd.tar.gz linux-0-day-957b778a166e32e242a33fdab693ffb256a19cbd.tar.xz | |
powerpc/mm: Add addr_limit to mm_context and use it to derive max slice index
In the followup patch, we will increase the slice array size to handle
512TB range, but will limit the max addr to 128TB. Avoid doing
unnecessary computation and avoid doing slice mask related operation
above address limit.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/book3s/64/mmu.h')
| -rw-r--r-- | arch/powerpc/include/asm/book3s/64/mmu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/include/asm/book3s/64/mmu.h index cce434e7de068..c4b865112d248 100644 --- a/arch/powerpc/include/asm/book3s/64/mmu.h +++ b/arch/powerpc/include/asm/book3s/64/mmu.h @@ -82,6 +82,7 @@ typedef struct { #ifdef CONFIG_PPC_MM_SLICES u64 low_slices_psize; /* SLB page size encodings */ unsigned char high_slices_psize[SLICE_ARRAY_SIZE]; + unsigned long addr_limit; #else u16 sllp; /* SLB page size encoding */ #endif |