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| author | Rocky Hao <rocky.hao@rock-chips.com> | 2017-08-04 16:06:14 +0800 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2017-08-11 17:13:34 +0200 |
| commit | 20590de2802155e65968e7569587f3dd29218d50 (patch) | |
| tree | 767d34d7b6358c98d283c3fc4a8c81ac2687fc82 /arch | |
| parent | d80ef50a1305e29a9bdacdf31501615695d0039e (diff) | |
| download | linux-0-day-20590de2802155e65968e7569587f3dd29218d50.tar.gz linux-0-day-20590de2802155e65968e7569587f3dd29218d50.tar.xz | |
arm64: dts: rockchip: add tsadc node for rk3328 SoC
add tsadc needed main information for rk3328 SoC.
50000Hz is the max clock rate supported by tsadc module.
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index cf23a6a4fb54f..5cc186b3c31bb 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -400,6 +400,26 @@ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; }; + tsadc: tsadc@ff250000 { + compatible = "rockchip,rk3328-tsadc"; + reg = <0x0 0xff250000 0x0 0x100>; + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; + assigned-clocks = <&cru SCLK_TSADC>; + assigned-clock-rates = <50000>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + pinctrl-names = "init", "default", "sleep"; + pinctrl-0 = <&otp_gpio>; + pinctrl-1 = <&otp_out>; + pinctrl-2 = <&otp_gpio>; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + rockchip,grf = <&grf>; + rockchip,hw-tshut-temp = <100000>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + saradc: adc@ff280000 { compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc"; reg = <0x0 0xff280000 0x0 0x100>; |