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| author | Anchal Jain <anchalj109@gmail.com> | 2016-09-18 12:16:40 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2016-09-18 09:13:35 +0200 |
| commit | ed88363e6aebb91df820e1a8898d2a07b18d2bc9 (patch) | |
| tree | e761fd8fef65ef8c9799dda1f7a115906263b6b9 /drivers/staging/olpc_dcon | |
| parent | 6841b2a0fccf930e80e0c7d7f1bd8d78d21cd0fa (diff) | |
| download | linux-0-day-ed88363e6aebb91df820e1a8898d2a07b18d2bc9.tar.gz linux-0-day-ed88363e6aebb91df820e1a8898d2a07b18d2bc9.tar.xz | |
staging: olpc_dcon: Replace a bit shift by a use of BIT.
This patch replaces bit shifting on 1 with the BIT(x) macro
as it's extensively used by other function in the file olpc_dcon.h .
Signed-off-by: Anchal Jain <anchalj109@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/staging/olpc_dcon')
| -rw-r--r-- | drivers/staging/olpc_dcon/olpc_dcon.h | 30 |
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/staging/olpc_dcon/olpc_dcon.h b/drivers/staging/olpc_dcon/olpc_dcon.h index 215e7ec4dea23..23a48a189dbc5 100644 --- a/drivers/staging/olpc_dcon/olpc_dcon.h +++ b/drivers/staging/olpc_dcon/olpc_dcon.h @@ -9,18 +9,18 @@ #define DCON_REG_ID 0 #define DCON_REG_MODE 1 -#define MODE_PASSTHRU (1<<0) -#define MODE_SLEEP (1<<1) -#define MODE_SLEEP_AUTO (1<<2) -#define MODE_BL_ENABLE (1<<3) -#define MODE_BLANK (1<<4) -#define MODE_CSWIZZLE (1<<5) -#define MODE_COL_AA (1<<6) -#define MODE_MONO_LUMA (1<<7) -#define MODE_SCAN_INT (1<<8) -#define MODE_CLOCKDIV (1<<9) -#define MODE_DEBUG (1<<14) -#define MODE_SELFTEST (1<<15) +#define MODE_PASSTHRU bit(0) +#define MODE_SLEEP bit(1) +#define MODE_SLEEP_AUTO bit(2) +#define MODE_BL_ENABLE bit(3) +#define MODE_BLANK bit(4) +#define MODE_CSWIZZLE bit(5) +#define MODE_COL_AA bit(6) +#define MODE_MONO_LUMA bit(7) +#define MODE_SCAN_INT bit(8) +#define MODE_CLOCKDIV bit(9) +#define MODE_DEBUG bit(14) +#define MODE_SELFTEST bit(15) #define DCON_REG_HRES 0x2 #define DCON_REG_HTOTAL 0x3 @@ -35,11 +35,11 @@ #define DCON_REG_MEM_OPT_B 0x42 /* Load Delay Locked Loop (DLL) settings for clock delay */ -#define MEM_DLL_CLOCK_DELAY (1<<0) +#define MEM_DLL_CLOCK_DELAY bit(0) /* Memory controller power down function */ -#define MEM_POWER_DOWN (1<<8) +#define MEM_POWER_DOWN bit(8) /* Memory controller software reset */ -#define MEM_SOFT_RESET (1<<0) +#define MEM_SOFT_RESET bit(0) /* Status values */ |