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| author | Sean Wang <sean.wang@mediatek.com> | 2018-03-01 11:27:50 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-03-19 13:25:09 -0700 |
| commit | 55a5fcafe3a94e8a0777bb993d09107d362258d2 (patch) | |
| tree | cbe1dd2e9155eff7d83d6f72cd3a6df055f6c782 /include/dt-bindings | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
| download | linux-0-day-55a5fcafe3a94e8a0777bb993d09107d362258d2.tar.gz linux-0-day-55a5fcafe3a94e8a0777bb993d09107d362258d2.tar.xz | |
dt-bindings: clock: mediatek: add binding for fixed-factor clock axisel_d4
Just add binding for a fixed-factor clock axisel_d4, which would be
referenced by PWM devices on MT7623 or MT2701 SoC.
Cc: stable@vger.kernel.org
Fixes: 1de9b21633d6 ("clk: mediatek: Add dt-bindings for MT2701 clocks")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/mt2701-clk.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/mt2701-clk.h b/include/dt-bindings/clock/mt2701-clk.h index 551f7600ab586..24e93dfcee9ff 100644 --- a/include/dt-bindings/clock/mt2701-clk.h +++ b/include/dt-bindings/clock/mt2701-clk.h @@ -176,7 +176,8 @@ #define CLK_TOP_AUD_EXT1 156 #define CLK_TOP_AUD_EXT2 157 #define CLK_TOP_NFI1X_PAD 158 -#define CLK_TOP_NR 159 +#define CLK_TOP_AXISEL_D4 159 +#define CLK_TOP_NR 160 /* APMIXEDSYS */ |