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| author | Stephen Boyd <sboyd@kernel.org> | 2018-03-16 09:09:49 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2018-03-16 09:09:49 -0700 |
| commit | 91fab9d26bcbf8614c2389ead327aa704768b639 (patch) | |
| tree | f679ff477ef905b4a5b33938842517f94c5e8b67 /include/dt-bindings | |
| parent | 7928b2cbe55b2a410a0f5c1f154610059c57b1b2 (diff) | |
| parent | c35b518f9ba06c9de79fb3ff62eed7462d804995 (diff) | |
| download | linux-0-day-91fab9d26bcbf8614c2389ead327aa704768b639.tar.gz linux-0-day-91fab9d26bcbf8614c2389ead327aa704768b639.tar.xz | |
Merge tag 'tegra-for-4.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-tegra
Pull tegra clk driver updates from Thierry Reding:
This contains preliminary work for the MBIST workaround implemented in
the Tegra PMC driver. There's also some fixes to various clocks for bugs
that went unnoticed for a long time.
* tag 'tegra-for-4.17-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Fix pll_u rate configuration
clk: tegra: Specify VDE clock rate
clk: tegra20: Correct PLL_C_OUT1 setup
clk: tegra: Mark HCLK, SCLK and EMC as critical
clk: tegra: MBIST work around for Tegra210
clk: tegra: add fence_delay for clock registers
clk: tegra: Add la clock for Tegra210
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/tegra210-car.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h index 6422314e46eba..6b77e721f6b1f 100644 --- a/include/dt-bindings/clock/tegra210-car.h +++ b/include/dt-bindings/clock/tegra210-car.h @@ -95,7 +95,7 @@ #define TEGRA210_CLK_CSITE 73 /* 74 */ /* 75 */ -/* 76 */ +#define TEGRA210_CLK_LA 76 /* 77 */ #define TEGRA210_CLK_SOC_THERM 78 #define TEGRA210_CLK_DTV 79 |