| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | riscv: add swiotlb support | Christoph Hellwig | 2018-05-19 | 1 | -0/+2 |
| * | Rename sbi_save to parse_dtb to improve code readability | Michael Clark | 2018-02-20 | 1 | -1/+1 |
| * | riscv: add ZONE_DMA32 | Christoph Hellwig | 2018-01-30 | 1 | -0/+9 |
| * | RISC-V: Remove mem_end command line processing | Palmer Dabbelt | 2018-01-30 | 1 | -19/+0 |
| * | RISC-V: Remove duplicate command-line parsing logic | Michael Clark | 2018-01-30 | 1 | -16/+0 |
| * | RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code | Palmer Dabbelt | 2017-12-11 | 1 | -11/+0 |
| * | RISC-V: Export some expected symbols for modules | Olof Johansson | 2017-11-30 | 1 | -0/+2 |
| * | RISC-V: move empty_zero_page definition to C and export it | Olof Johansson | 2017-11-30 | 1 | -0/+3 |
| * | RISC-V: Init and Halt Code | Palmer Dabbelt | 2017-09-26 | 1 | -0/+257 |
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