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path: root/drivers/net/wireless/ath/ath9k/hw.c
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* ath9k: Fix ack SIFS time for quarter/half channelsWojciech Dubowik2018-02-271-1/+7
| | | | | | | | | | Ack timing generation has to be adapted for 5/10 MHz channels. Do it by properly initializing ack shift field in TXSIFS register. Ack shift assumes channel width of 2.5 Mhz so value zero means 2.5 MHz, 1 is 5 MHz and so on. Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: Fix airtime calculation for quarter/half channelsWojciech Dubowik2018-02-271-2/+4
| | | | | | | | | The bitrate value for airtime calculation is specified for full rates. We need to divide it for 5 and 10MHz channels to get correct result. Signed-off-by: Wojciech Dubowik <Wojciech.Dubowik@neratec.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: add MSI supportRussell Hu2018-01-161-7/+26
| | | | | | | | | | | On new Intel platforms like ApolloLake, legacy interrupt mechanism (INTx) is not supported, so WLAN modules are not working because interrupts are missing, therefore this patch is to add MSI support to ath9k. With module paremeter "use_msi=1", ath9k driver would try to use MSI instead of INTx. Signed-off-by: Russell Hu <rhu@qti.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k_hw: check if the chip failed to wake upFelix Fietkau2017-02-071-0/+4
| | | | | | | | | | | | | | | In an RFC patch, Sven Eckelmann and Simon Wunderlich reported: "QCA 802.11n chips (especially AR9330/AR9340) sometimes end up in a state in which a read of AR_CFG always returns 0xdeadbeef. This should not happen when when the power_mode of the device is ATH9K_PM_AWAKE." Include the check for the default register state in the existing MAC hang check. Signed-off-by: Felix Fietkau <nbd@nbd.name> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: fix spelling mistake: "meaurement" -> "measurement"Colin Ian King2017-01-121-1/+1
| | | | | | | Trivial fix to spelling mistake in ath_err message Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: fix ath9k_hw_gpio_get() to return 0 or 1 on successMatthias Schiffer2016-11-231-1/+1
| | | | | | | | | | | | | | | | | Commit b2d70d4944c1 ("ath9k: make GPIO API to support both of WMAC and SOC") refactored ath9k_hw_gpio_get() to support both WMAC and SOC GPIOs, changing the return on success from 1 to BIT(gpio). This broke some callers like ath_is_rfkill_set(). This doesn't fix any known bug in mainline at the moment, but should be fixed anyway. Instead of fixing all callers, change ath9k_hw_gpio_get() back to only return 0 or 1. Fixes: b2d70d4944c1 ("ath9k: make GPIO API to support both of WMAC and SOC") Cc: <stable@vger.kernel.org> # v4.7+ Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> [kvalo@qca.qualcomm.com: mention that doesn't fix any known bug] Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: fix AR5416 access GPIO warningMiaoqing Pan2016-09-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | The warning was seen on AR5416 chip, which invoke ath9k_hw_gio_get() before the GPIO initialized correctly. WARNING: CPU: 1 PID: 1159 at ~/drivers/net/wireless/ath/ath9k/hw.c:2776 ath9k_hw_gpio_get+0x148/0x1a0 [ath9k_hw] ... CPU: 1 PID: 1159 Comm: systemd-udevd Not tainted 4.7.0-rc7-aptosid-amd64 #1 aptosid 4.7~rc7-1~git92.slh.3 Hardware name: /DH67CL, BIOS BLH6710H.86A.0160.2012.1204.1156 12/04/2012 0000000000000286 00000000f912d633 ffffffff81290fd3 0000000000000000 0000000000000000 ffffffff81063fd4 ffff88040c6dc018 0000000000000000 0000000000000002 0000000000000000 0000000000000100 ffff88040c6dc018 Call Trace: [<ffffffff81290fd3>] ? dump_stack+0x5c/0x79 [<ffffffff81063fd4>] ? __warn+0xb4/0xd0 [<ffffffffa0668fb8>] ? ath9k_hw_gpio_get+0x148/0x1a0 [ath9k_hw] Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Reported-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: Remove some #defined constants to decrease verbosityBenjamin Berg2016-07-081-1/+1
| | | | | | | | | The removed ATH9K_SLOT_TIME_X constants simply map the value in microseconds to the same integer. These constants were not used consistently, so fix the inconsistency issue by replacing all occurances with the integer equivalent. Signed-off-by: Benjamin Berg <benjamin.berg@open-mesh.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: Use tsf offset helper in ath9k_hw_resetBenjamin Berg2016-07-081-8/+8
| | | | | | | | | | | | | These changes make ath9k_hw_reset more consistent with other places that handle the TSF value by using the same helper routine. A slight improvement is to not assume that a fixed time of 1.5ms has passed for the initval writes when compared to the first write attempt. Instead the TSF value is re-calculated which will yield a higher accuracy of the restored TSF timer. Signed-off-by: Benjamin Berg <benjamin.berg@open-mesh.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: remove return value from ath9k_hw_init_macaddrMartin Blumenstingl2016-07-081-10/+5
| | | | | | | | | ath9k_hw_init_macaddr unconditionally returns 0 in all cases, making the return value unnecessary. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Julian Calaby <julian.calaby@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: ath9k_hw_init_macaddr should not overwrite valid MAC addressesMartin Blumenstingl2016-07-081-9/+13
| | | | | | | | | | Currently setting the MAC address via ath9k_platform_data works only due to the order in which init.c sets common->macaddr, which is done after ath9k_hw_init_macaddr was executed. It would be better if the latter was independent of the order in which it's being called. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: remove variable which is set but never readMartin Blumenstingl2016-07-081-3/+0
| | | | | | | | | No functional changes - this only removes a variable which is set but never read. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Julian Calaby <julian.calaby@gmail.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: interpret requested txpower in EIRP domainZefir Kurtisi2016-04-191-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tx power limitations at upper layers are interpreted in the EIRP domain. When the user requests a given maximum txpower, e.g. with: 'iw phy0 set txpower fixed 1500', he expects the EIRP to be at or below 15dBm. In ath9k_hw_apply_txpower(), the interpretation is different: the antenna-gain is capped against the current txpower limit in the regulatory, but not against the user set value. It ensures that the resulting EIRP is below the limit defined by the active countrycode, but not below the value the user requested. In a scenario like e.g. a) antenna_gain=6 b) countrycode limits to eirp=18 c) user set txpower=15 this will cause a setting for AR_PHY_POWER_TX_RATE regs resulting in an EIRP > 15. This patch ensures that antenna-gain is considered whenever the txpower limit is adjusted and with that the user set limits are kept. Signed-off-by: Zefir Kurtisi <zefir.kurtisi@neratec.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: free GPIO resource for SOC GPIOsMiaoqing Pan2016-03-111-0/+1
| | | | | | | | For SOC GPIOs, should call ath9k_hw_gpio_free() to release the GPIO resource. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: make GPIO API to support both of WMAC and SOCMiaoqing Pan2016-03-111-79/+117
| | | | | | | | | | | | | | | | | | | commit 61b559dea40e ("ath9k: add extra GPIO led support") added ath9k to support access SOC's GPIOs, but implemented in a separated API: ath9k_hw_request_gpio(). So this patch make the APIs more common, to support both of WMAC and SOC GPIOs. The new APIs as below, void ath9k_hw_gpio_request_in(); void ath9k_hw_gpio_request_out(); void ath9k_hw_gpio_free(); NOTE, the BSP of the SOC chips(AR9340, AR9531, AR9550, AR9561) should set the corresponding MUX registers correctly. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: define correct GPIO numbers and bits maskMiaoqing Pan2016-03-111-14/+56
| | | | | | | | | | | | Define correct GPIO numbers and MASK bits to indicate the WMAC GPIO resource. Allow SOC chips(AR9340, AR9531, AR9550, AR9561) to access all GPIOs which rely on gpiolib framework. But restrict SOC AR9330 only to access WMAC GPIO which has the same design with the old chips. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: fix data bus error on ar9300 and ar9580Miaoqing Pan2016-01-261-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One crash issue be found on ar9300: RTC_RC reg read leads crash, leading the data bus error, due to RTC_RC reg write not happen properly. Warm Reset trigger in continuous beacon stuck for one of the customer for other chip, noticed the MAC was stuck in RTC reset. After analysis noticed DMA did not complete when RTC was put in reset. So, before resetting the MAC need to make sure there are no pending DMA transactions because this reset does not reset all parts of the chip. The 12th and 11th bit of MAC _DMA_CFG register used to do that. 12 cfg_halt_ack 0x0 0 DMA has not yet halted 1 DMA has halted 11 cfg_halt_req 0x0 0 DMA logic operates normally 1 Request DMA logic to stop so software can reset the MAC The Bit [12] of this register indicates when the halt has taken effect or not. the DMA halt IS NOT recoverable; once software sets bit [11] to request a DMA halt, software must wait for bit [12] to be set and reset the MAC. So, the same thing we implemented for ar9580 chip. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: fix AR_RX_FILTER for ar9462/ar9565 when rx stoppedMiaoqing Pan2015-12-111-3/+0
| | | | | | | | | | | | When rx stopped, AR_RX_FILTER should be cleared, but in ath9k_hw_setrxfilter(), ATH9K_RX_FILTER_CONTROL_WRAPPER will always be set for ar9462/ar9565. Fix this by moving the code in ath9k_hw_setrxfilter() to ath_calcrxfilter(). Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* ath9k: add debug messages to aggr/chanctx funcsJanusz Dziedzic2015-12-081-4/+4
| | | | | | | Add/extend debug messages when chanctx used. Signed-off-by: Janusz Dziedzic <janusz.dziedzic@tieto.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
* Merge tag 'driver-core-4.4-rc1' of ↵Linus Torvalds2015-11-041-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core updates from Greg KH: "Here's the "big" driver core updates for 4.4-rc1. Primarily a bunch of debugfs updates, with a smattering of minor driver core fixes and updates as well. All have been in linux-next for a long time" * tag 'driver-core-4.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: debugfs: Add debugfs_create_ulong() of: to support binding numa node to specified device in devicetree debugfs: Add read-only/write-only bool file ops debugfs: Add read-only/write-only size_t file ops debugfs: Add read-only/write-only x64 file ops debugfs: Consolidate file mode checks in debugfs_create_*() Revert "mm: Check if section present during memory block (un)registering" driver-core: platform: Provide helpers for multi-driver modules mm: Check if section present during memory block (un)registering devres: fix a for loop bounds check CMA: fix CONFIG_CMA_SIZE_MBYTES overflow in 64bit base/platform: assert that dev_pm_domain callbacks are called unconditionally sysfs: correctly handle short reads on PREALLOC attrs. base: soc: siplify ida usage kobject: move EXPORT_SYMBOL() macros next to corresponding definitions kobject: explain what kobject's sd field is debugfs: document that debugfs_remove*() accepts NULL and error values debugfs: Pass bool pointer to debugfs_create_bool() ACPI / EC: Fix broken 64bit big-endian users of 'global_lock'
| * debugfs: Pass bool pointer to debugfs_create_bool()Viresh Kumar2015-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Its a bit odd that debugfs_create_bool() takes 'u32 *' as an argument, when all it needs is a boolean pointer. It would be better to update this API to make it accept 'bool *' instead, as that will make it more consistent and often more convenient. Over that bool takes just a byte. That required updates to all user sites as well, in the same commit updating the API. regmap core was also using debugfs_{read|write}_file_bool(), directly and variable types were updated for that to be bool as well. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Mark Brown <broonie@kernel.org> Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | ath9k: Add support for OCB modeJan Kaisrlik2015-09-291-0/+1
|/ | | | | | | | | | | The patch adds support for "outside the context of a BSS"(OCB) mode to ath9k driver and extends debugfs files by OCB ralated information. This patch was tested on AR9380-AL1A cards. Signed-off-by: Jan Kaisrlik <kaisrja1@fel.cvut.cz> Cc: Michal Sojka <sojkam1@fel.cvut.cz> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: add correct MAC/BB name for ar9561Miaoqing Pan2015-08-181-0/+1
| | | | | | | MAC/BB name is"????" if the MAC/BB is unknown. Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k_hw: fix device ID check for AR956xFelix Fietkau2015-07-111-0/+1
| | | | | | | | Because of the missing return, the macVersion value was being overwritten with an invalid register read Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: add extra GPIO led supportMiaoqing Pan2015-04-071-2/+15
| | | | | | | | | ar9550 or later chips, the AR_GPIO_IN_OUT register only can control GPIO[0:3]. For the extra GPIO, use standard GPIO calls instead of WMAC internal registers. Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller2015-04-021-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/net/usb/asix_common.c drivers/net/usb/sr9800.c drivers/net/usb/usbnet.c include/linux/usb/usbnet.h net/ipv4/tcp_ipv4.c net/ipv6/tcp_ipv6.c The TCP conflicts were overlapping changes. In 'net' we added a READ_ONCE() to the socket cached RX route read, whilst in 'net-next' Eric Dumazet touched the surrounding code dealing with how mini sockets are handled. With USB, it's a case of the same bug fix first going into net-next and then I cherry picked it back into net. Signed-off-by: David S. Miller <davem@davemloft.net>
| * ath9k: disable TPC support again (for now)Felix Fietkau2015-03-161-1/+1
| | | | | | | | | | | | | | | | | | TPC support has been observed to cause some tx power fluctuations on some devices with at least AR934x and AR938x chips. Disable it for now until the bugs have been found and fixed Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* | ath9k: use rmw buffer in ath9k_hw_set_operating_mode and ath9k_hw_resetOleksij Rempel2015-03-301-0/+4
| | | | | | | | | | Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* | ath9k: add new function ath9k_hw_read_arrayOleksij Rempel2015-03-301-0/+30
| | | | | | | | | | | | | | | | REG_READ generate most overhead on usb bus. It send and read micro packages and reduce usb bandwidth. To reduce this overhead we should read in batches. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* | ath9k: Initialize pll_pwrsave for AR9462/AR9565Sujith Manoharan2015-03-131-0/+3
|/ | | | | | | | Cards based on AR9462/AR9565 support more PCIE power save mechanisms, so register them correctly. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: Register max WOW patternsSujith Manoharan2015-02-031-0/+7
| | | | | | | | | Since the number of patterns that can be configured in the HW is higher for newer chips, store the chip-specific value in ath9k_hw_wow. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: Remove ATH9K_HW_WOW_DEVICE_CAPABLESujith Manoharan2015-02-031-3/+0
| | | | | | | | | Enabling WOW based on the chip is incorrect since it needs to be done for specific sub-devices which have proper platform support. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: enable per-packet TPC on AR9002 based chipsLorenzo Bianconi2015-01-151-2/+1
| | | | | | | Enable per-packet TPC on AR9002 based chips by default Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: Add QCA956x HW supportMiaoqing Pan2015-01-151-14/+23
| | | | | | Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: Add HW IDs for QCA956xMiaoqing Pan2015-01-151-0/+4
| | | | | | Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* ath9k: enable TPC by defaultLorenzo Bianconi2014-12-241-0/+3
| | | | | | | Enable hw TPC by default on AR9003 based chips Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
* Merge commit '4e6ce4dc7ce71d0886908d55129d5d6482a27ff9' of ↵John W. Linville2014-11-191-13/+0
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless
| * ath9k: Fix RTC_DERIVED_CLK usageMiaoqing Pan2014-11-111-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the reference clock, which could be 25MHz or 40MHz, AR_RTC_DERIVED_CLK is programmed differently for AR9340 and AR9550. But, when a chip reset is done, processing the initvals sets the register back to the default value. Fix this by moving the code in ath9k_hw_init_pll() to ar9003_hw_override_ini(). Also, do this override for AR9531. Cc: stable@vger.kernel.org Signed-off-by: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k: Store the chip chainmask in HW capabilitiesSujith Manoharan2014-11-171-10/+10
| | | | | | | | | | | | Cc: Miaoqing Pan <miaoqing@qca.qualcomm.com> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k: Enable TSF2 for generic HW timersSujith Manoharan2014-11-171-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The base TSF is used for HW timers 0..7, but chips in the AR9003 family and above can support more generic timers. To use them, however, a second HW TSF needs to be enabled. This patch allows usage of the extra timers by starting the second TSF properly. The extra set of HW timers is apparently also present in AR9287, but we enable it only for the AR9003 family. Cc: Kobi Cohen-Arazi <kobic@qti.qualcomm.com> Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k_htc: Enable software crypto for mgmt frame in Tx for USB devicesChun-Yeow Yeoh2014-11-171-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In secured mesh, the unicast mgmt frame is encrypted using the same key that used for encrypting the unicast data frame. This patch "ath9k_htc_firmware: fix the offset of CCMP header for mesh data frame" applied to open-ath9k-htc-firmware allows the ath9k_htc to be loaded without "nohwcrypt=1". Unfortunately, this is not working and we still need CCMP encryption of transmitted management frames to be done in software. So this patch allows the software encryption for transmitted management frame to be done in software but remain the hardware decryption for received management frame. This patch is tested with the following hardwares: - TP-Link TL-WN821N v3 802.11n [Atheros AR7010+AR9287] - AR9271 802.11n and managed to work with peer mesh STA equipped with ath9k. Signed-off-by: Chun-Yeow Yeoh <yeohchunyeow@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k|ath9k_htc: Seperate the software crypto flag for Tx and RxChun-Yeow Yeoh2014-11-171-3/+6
| | | | | | | | | | | | | | | | | | | | Use the sw_mgmt_crypto_tx flag to trigger the CCMP encryption for transmitted management frames to be done in software while the sw_mgmt_crypto_rx flag is used to trigger the CCMP decryption for received management frames to be done in software. Signed-off-by: Chun-Yeow Yeoh <yeohchunyeow@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k: use a random MAC address if the EEPROM address is invalidFelix Fietkau2014-10-271-2/+11
| | | | | | | | | | | | | | Based on OpenWrt patch by Gabor Juhos Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k: allow disabling bands via platform dataFelix Fietkau2014-10-271-8/+16
| | | | | | | | | | | | | | | | | | | | Some devices have multiple bands enables in the EEPROM data, even though they are only calibrated for one. Allow platform data to disable unsupported bands. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* | ath9k_hw: start initial NF calibration after PA calibration on <AR9003Felix Fietkau2014-10-271-2/+4
|/ | | | | | | This makes the initial NF calibration less likely to fail. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k_hw: fix PLL clock initialization for newer SoCFelix Fietkau2014-09-301-3/+6
| | | | | | | | | | | | | | | | | On AR934x and newer SoC devices, the layout of the AR_RTC_PLL_CONTROL register changed. This currently breaks at least 5/10 MHz operation. AR933x uses the old layout. It might also have been causing other stability issues because of the different location of the PLL_BYPASS bit which needs to be set during PLL clock initialization. This patch also removes more instances of hardcoded register values in favor of properly computed ones with the PLL_BYPASS bit added. Reported-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k_hw: disable hardware ad-hoc flag on ar934x rev 3Felix Fietkau2014-09-301-3/+6
| | | | | | | | | | | | | | On AR934x rev 3, settin the ad-hoc flag completely messes up hardware state - beacons get stuck, almost no packets make it out, hardware is constantly reset. When leaving out that flag and setting up the hw like in AP mode, TSF timers won't be automatically synced, but at least the rest works. AR934x rev 2 and older are not affected by this bug Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: use ah->get_mac_revision for all SoC devices if availableFelix Fietkau2014-09-301-7/+4
| | | | | | | It is needed for AR934x as well Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: enable ext channel pulse detectionLorenzo Bianconi2014-09-161-0/+1
| | | | | | | Enable pulse detection on extension channel if 40MHz channel width has been set Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
* ath9k: do not overwrite ACK timeout estimationLorenzo Bianconi2014-09-161-0/+8
| | | | | | | | Do not overwrite ACK timeout estimation in ath9k_hw_init_global_settings() if dynack processing has been enabled Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi83@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-20 23:14:20 +0000