diff options
author | Michael Tretter <m.tretter@pengutronix.de> | 2020-08-14 09:28:03 +0200 |
---|---|---|
committer | Lucas Stach <l.stach@pengutronix.de> | 2021-07-21 22:27:10 +0200 |
commit | 90574a8c50dc59b899c70320e5cf3054c8280c2a (patch) | |
tree | 711091c84fa9f2a5a19c34cb31489f2af21ca7de | |
parent | 654afd715be55fcd83285ab996a4437263020cfb (diff) | |
download | linux-90574a8c50dc59b899c70320e5cf3054c8280c2a.tar.gz linux-90574a8c50dc59b899c70320e5cf3054c8280c2a.tar.xz |
ARM64: dts: imx8mm: add lcdif and mipi-dsi bridge
Add the LCDIF and MIPI-DSI bridge devices to the i.MX8MM device tree.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
-rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f8bcde737804..6f20aff3b883 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1084,6 +1084,63 @@ #phy-cells = <1>; }; + lcdif: lcdif@32e00000 { + compatible = "fsl,imx6sx-lcdif"; + reg = <0x32e00000 0x10000>; + clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "pix", "axi", "disp_axi"; + assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>; + assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <594000000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_LCDIF>; + status = "disabled"; + + port { + lcdif_to_dsim: endpoint { + remote-endpoint = <&dsim_from_lcdif>; + }; + }; + }; + + mipi_dsi: mipi_dsi@32e10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x32e10000 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + clock-names = "bus_clk", "sclk_mipi"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_VIDEO_PLL1_OUT>, + <&clk IMX8MM_CLK_DSI_PHY_REF>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_BYPASS>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>, <27000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + phys = <&mipi_dphy 0>; + phy-names = "dsim"; + power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_MIPI_DSI>; + status = "disabled"; + + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <54000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + }; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; |