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authorVinod Koul <vinod.koul@intel.com>2016-05-17 10:14:16 +0530
committerVinod Koul <vinod.koul@intel.com>2016-05-17 10:14:16 +0530
commit56214883c586a235ea73c07a423b27ee62ea2810 (patch)
tree8718f223dd672d029bb15893c4846a0f94c1c3ce /Documentation/devicetree/bindings/dma
parent95c4dc7b2c622a3cc41535f67f46dd31332186c8 (diff)
parent3a14c66d43d018baed96ceb74f9ab548878c09b8 (diff)
downloadlinux-56214883c586a235ea73c07a423b27ee62ea2810.tar.gz
linux-56214883c586a235ea73c07a423b27ee62ea2810.tar.xz
Merge branch 'topic/dw' into for-linus
Diffstat (limited to 'Documentation/devicetree/bindings/dma')
-rw-r--r--Documentation/devicetree/bindings/dma/snps-dma.txt11
1 files changed, 8 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index c261598164a7..0f5583293c9c 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -13,6 +13,11 @@ Required properties:
- chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
increase from chan n->0
- block_size: Maximum block size supported by the controller
+- data-width: Maximum data width supported by hardware per AHB master
+ (in bytes, power of 2)
+
+
+Deprecated properties:
- data_width: Maximum data width supported by hardware per AHB master
(0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
@@ -38,7 +43,7 @@ Example:
chan_allocation_order = <1>;
chan_priority = <1>;
block_size = <0xfff>;
- data_width = <3 3>;
+ data-width = <8 8>;
};
DMA clients connected to the Designware DMA controller must use the format
@@ -47,8 +52,8 @@ The four cells in order are:
1. A phandle pointing to the DMA controller
2. The DMA request line number
-3. Source master for transfers on allocated channel
-4. Destination master for transfers on allocated channel
+3. Memory master for transfers on allocated channel
+4. Peripheral master for transfers on allocated channel
Example: