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authorMasahiro Yamada <yamada.m@jp.panasonic.com>2015-01-15 17:52:40 +0900
committerLinus Walleij <linus.walleij@linaro.org>2015-01-19 11:33:35 +0100
commit74981fb81d8348b9e405e9acc21c0d5e241d2d69 (patch)
tree2460b7c1a4997f983c582d372c76999ed921c043 /Documentation/devicetree/bindings/gpio/gpio.txt
parent04d2264c3bf07f5c3d18165ba78de0a93360c6c0 (diff)
downloadlinux-74981fb81d8348b9e405e9acc21c0d5e241d2d69.tar.gz
linux-74981fb81d8348b9e405e9acc21c0d5e241d2d69.tar.xz
Documentation: gpio: fix bindings document
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/gpio/gpio.txt')
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio.txt5
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index b9bd1d64cfa6..f7a158d85862 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller.
----------------------------------
A gpio-specifier should contain a flag indicating the GPIO polarity; active-
-high or active-low. If it does, the follow best practices should be followed:
+high or active-low. If it does, the following best practices should be
+followed:
The gpio-specifier's polarity flag should represent the physical level at the
GPIO controller that achieves (or represents, for inputs) a logically asserted
@@ -147,7 +148,7 @@ contains information structures as follows:
numeric-gpio-range ::=
<pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>'
- gpio-phandle : phandle to pin controller node.
+ pinctrl-phandle : phandle to pin controller node
gpio-base : Base GPIO ID in the GPIO controller
pinctrl-base : Base pinctrl pin ID in the pin controller
count : The number of GPIOs/pins in this range