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| author | Mylène Josserand <mylene.josserand@free-electrons.com> | 2017-01-17 15:02:22 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-01-17 17:42:46 +0100 |
| commit | 603a0c8af9cb23f7cf94d57e76113fef51848200 (patch) | |
| tree | 0fb26415f874bacf728d62db4c55209ff6c3d254 /Documentation | |
| parent | 70421257c068b91476e70cade15fca68045d0693 (diff) | |
| download | linux-603a0c8af9cb23f7cf94d57e76113fef51848200.tar.gz linux-603a0c8af9cb23f7cf94d57e76113fef51848200.tar.xz | |
clk: sunxi-ng: a33: Add CLK_SET_RATE_PARENT to ac-dig
The audio DAI needs to set the clock rates of the ac-dig clock.
To make it possible, the parent PLL audio clock rates should
also be changed. This is possible via "CLK_SET_RATE_PARENT" flag.
Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions