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| author | Caesar Wang <wxt@rock-chips.com> | 2016-07-27 22:24:07 +0800 |
|---|---|---|
| committer | Jonathan Cameron <jic23@kernel.org> | 2016-08-23 19:08:29 +0100 |
| commit | 3d4267a5a3a4b7619b80ad1839d8b3bedd8b7a8d (patch) | |
| tree | 2ff1e7b2b29f3d268828c5edfabda4d9e8e10746 /arch/arm/boot/dts/rk3288.dtsi | |
| parent | 78ec79bfd59e126e1cb394302bfa531a420b3ecd (diff) | |
| download | linux-3d4267a5a3a4b7619b80ad1839d8b3bedd8b7a8d.tar.gz linux-3d4267a5a3a4b7619b80ad1839d8b3bedd8b7a8d.tar.xz | |
arm: dts: rockchip: add reset node for the exist saradc SoCs
SARADC controller needs to be reset before programming it, otherwise
it will not function properly.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd33f0170890..91c4b3c7a8d5 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -279,6 +279,8 @@ #io-channel-cells = <1>; clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; status = "disabled"; }; |