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| author | Kevin Cernekee <cernekee@gmail.com> | 2015-03-16 14:43:07 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-03-31 11:59:40 +0200 |
| commit | d631fc60706ccd86c5c2b0084bcea0739952ce90 (patch) | |
| tree | 80691675006671da9846343c4e964e4e447ef6f8 /arch/mips/include/asm/mach-generic | |
| parent | a47eb351d2bd17cdf01de070f13cb12f6be4a0c5 (diff) | |
| download | linux-d631fc60706ccd86c5c2b0084bcea0739952ce90.tar.gz linux-d631fc60706ccd86c5c2b0084bcea0739952ce90.tar.xz | |
MIPS: Create a common <asm/mach-generic/war.h>
11 platforms require at least one of these workarounds to be enabled; 22
platforms do not. In the latter case we can fall back to a generic version.
Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR.
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: James Hartley <james.hartley@imgtec.com>
Cc: James Hogan <james.hogan@imgtec.com>
Patchwork: https://patchwork.linux-mips.org/patch/9567/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-generic')
| -rw-r--r-- | arch/mips/include/asm/mach-generic/war.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h new file mode 100644 index 000000000000..a1bc2e71f983 --- /dev/null +++ b/arch/mips/include/asm/mach-generic/war.h @@ -0,0 +1,24 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> + */ +#ifndef __ASM_MACH_GENERIC_WAR_H +#define __ASM_MACH_GENERIC_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_GENERIC_WAR_H */ |