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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2016-05-17 09:02:49 +0200 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-07-09 02:02:48 -0500 |
| commit | 6264dbb98ff762d71c65e04ae3b2e632d28a5b84 (patch) | |
| tree | 8acad0b1e649c5ce9426621917b86399e0dc38bc /arch/powerpc/kernel/head_8xx.S | |
| parent | 567a16d15296f42dd3df640ef60d04f642443251 (diff) | |
| download | linux-6264dbb98ff762d71c65e04ae3b2e632d28a5b84.tar.gz linux-6264dbb98ff762d71c65e04ae3b2e632d28a5b84.tar.xz | |
powerpc/8xx: unpin all TLBs before flushing
Bootloader may have pinned some TLB entries so the kernel must
unpin them before flushing TLBs with tlbia otherwise pinned TLB
entries won't get flushed
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/kernel/head_8xx.S')
| -rw-r--r-- | arch/powerpc/kernel/head_8xx.S | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S index 44f4edbd5dee..d9a165629202 100644 --- a/arch/powerpc/kernel/head_8xx.S +++ b/arch/powerpc/kernel/head_8xx.S @@ -797,6 +797,14 @@ start_here: * these mappings is mapped by page tables. */ initial_mmu: + li r8, 0 + mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */ + lis r10, MD_RESETVAL@h +#ifndef CONFIG_8xx_COPYBACK + oris r10, r10, MD_WTDEF@h +#endif + mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */ + tlbia /* Invalidate all TLB entries */ /* Always pin the first 8 MB ITLB to prevent ITLB misses while mucking around with SRR0/SRR1 in asm @@ -807,16 +815,10 @@ initial_mmu: mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */ #ifdef CONFIG_PIN_TLB - lis r10, (MD_RSV4I | MD_RESETVAL)@h + oris r10, r10, MD_RSV4I@h ori r10, r10, 0x1c00 - mr r8, r10 -#else - lis r10, MD_RESETVAL@h -#endif -#ifndef CONFIG_8xx_COPYBACK - oris r10, r10, MD_WTDEF@h -#endif mtspr SPRN_MD_CTR, r10 /* Set data TLB control */ +#endif /* Now map the lower 8 Meg into the TLBs. For this quick hack, * we can load the instruction and data TLB registers with the |