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| author | Yazen Ghannam <Yazen.Ghannam@amd.com> | 2016-11-17 17:57:37 -0500 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2016-11-28 17:50:11 +0100 |
| commit | b64ce7cd7f540c64e3fbeaeee3ddb59bc9ab1a3b (patch) | |
| tree | 3ffab7c868dcf9aa50be60d0b4265f3b0bfe71c1 /drivers/edac/amd64_edac.h | |
| parent | 936fc3afaa8abc20dfea306c9b6d19a6e7ca5caf (diff) | |
| download | linux-b64ce7cd7f540c64e3fbeaeee3ddb59bc9ab1a3b.tar.gz linux-b64ce7cd7f540c64e3fbeaeee3ddb59bc9ab1a3b.tar.xz | |
EDAC, amd64: Read MC registers on AMD Fam17h
Fam17h has a different set of registers and bitfields. Most of these
registers are read through SMN (System Management Network) rather
than PCI config space. Also, the derivation of various values is now
different.
Update amd64_edac to read the appropriate registers and extract the
correct values for Fam17h.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Cc: Aravind Gopalakrishnan <aravindksg.lkml@gmail.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/1479423463-8536-12-git-send-email-Yazen.Ghannam@amd.com
[ Save us the indentation level in read_mc_regs(), add defines ]
Signed-off-by: Borislav Petkov <bp@suse.de>
Diffstat (limited to 'drivers/edac/amd64_edac.h')
| -rw-r--r-- | drivers/edac/amd64_edac.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 4ca7d249f02e..738166393673 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -250,12 +250,23 @@ /* MSRs */ #define MSR_MCGCTL_NBE BIT(4) +/* F17h */ + +/* F0: */ +#define DF_DHAR 0x104 + /* UMC CH register offsets */ +#define UMCCH_BASE_ADDR 0x0 +#define UMCCH_ADDR_MASK 0x20 +#define UMCCH_DIMM_CFG 0x80 #define UMCCH_SDP_CTRL 0x104 +#define UMCCH_ECC_CTRL 0x14C #define UMCCH_UMC_CAP_HI 0xDF4 /* UMC CH bitfields */ +#define UMC_ECC_CHIPKILL_CAP BIT(31) #define UMC_ECC_ENABLED BIT(30) + #define UMC_SDP_INIT BIT(31) #define NUM_UMCS 2 @@ -302,7 +313,9 @@ struct chip_select { }; struct amd64_umc { + u32 dimm_cfg; /* DIMM Configuration reg */ u32 sdp_ctrl; /* SDP Control reg */ + u32 ecc_ctrl; /* DRAM ECC Control reg */ }; struct amd64_pvt { |