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authorShawn Lin <shawn.lin@rock-chips.com>2016-12-07 15:05:59 -0600
committerBjorn Helgaas <bhelgaas@google.com>2016-12-07 15:05:59 -0600
commit45e9320f3a4ef9588ee50a2eb1891c4bfdbb07df (patch)
tree6793b084c91ca861fca7170230c4967e1f9b9012 /drivers/pci
parent1177f76a7e7e52d4be3c78247b30ab73cabf7164 (diff)
downloadlinux-45e9320f3a4ef9588ee50a2eb1891c4bfdbb07df.tar.gz
linux-45e9320f3a4ef9588ee50a2eb1891c4bfdbb07df.tar.xz
PCI: rockchip: Fix negotiated lanes calculation
The calculation of negotiated lanes is wrong: it should be shifted by PCIE_CORE_PL_CONF_LANE_SHIFT, but it is shifted by PCIE_CORE_PL_CONF_LANE_MASK instead. Let's fix it. Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/host/pcie-rockchip.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index b296808ccc71..f641a4e6f605 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -636,8 +636,8 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
/* Check the final link width from negotiated lane counter from MGMT */
status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
- status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
- PCIE_CORE_PL_CONF_LANE_MASK);
+ status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
+ PCIE_CORE_PL_CONF_LANE_SHIFT);
dev_dbg(dev, "current link width is x%d\n", status);
rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,