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| author | Andy Shevchenko <andriy.shevchenko@linux.intel.com> | 2017-01-17 13:57:31 +0200 |
|---|---|---|
| committer | Vinod Koul <vinod.koul@intel.com> | 2017-01-25 11:51:40 +0530 |
| commit | 199244d69458770770890f8b5988a1b6cad701ad (patch) | |
| tree | 545b41f9bba1461ae5d33f9a793ebc5253c1b559 /include/linux/platform_data | |
| parent | a9f4d1b8314396cc09301fa3ab954167ff81a46b (diff) | |
| download | linux-199244d69458770770890f8b5988a1b6cad701ad.tar.gz linux-199244d69458770770890f8b5988a1b6cad701ad.tar.xz | |
dmaengine: dw: add support of iDMA 32-bit hardware
iDMA 32-bit is Intel designed DMA controller that behaves like Synopsys
Designware DMA. This patch adds a support of the new Intel hardware.
Due to iDMA 32-bit has no autoconfiguration the platform code must
provide a platform data to dw_dma_probe().
By default full FIFO (1024 bytes) is assigned to channel 0. Here we
slice FIFO on equal parts between channels for iDMA 32-bit case.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Diffstat (limited to 'include/linux/platform_data')
| -rw-r--r-- | include/linux/platform_data/dma-dw.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h index e69e415d0d98..896cb71a382c 100644 --- a/include/linux/platform_data/dma-dw.h +++ b/include/linux/platform_data/dma-dw.h @@ -41,6 +41,7 @@ struct dw_dma_slave { * @is_private: The device channels should be marked as private and not for * by the general purpose DMA channel allocator. * @is_memcpy: The device channels do support memory-to-memory transfers. + * @is_idma32: The type of the DMA controller is iDMA32 * @chan_allocation_order: Allocate channels starting from 0 or 7 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0. * @block_size: Maximum block size supported by the controller @@ -53,6 +54,7 @@ struct dw_dma_platform_data { unsigned int nr_channels; bool is_private; bool is_memcpy; + bool is_idma32; #define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */ #define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */ unsigned char chan_allocation_order; |