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| author | Johan Hovold <jhovold@gmail.com> | 2013-02-07 16:31:58 +0100 |
|---|---|---|
| committer | Nicolas Ferre <nicolas.ferre@atmel.com> | 2013-03-13 11:05:12 +0100 |
| commit | bbd44f6bd9d1aa735b180b29b5719d63a8e87b55 (patch) | |
| tree | d2d6b87a1104b5a931ea95a7f0c7c9341ad6f079 /include/video | |
| parent | 934a50bd089789d1ed74f0bef4988a97bd590afe (diff) | |
| download | linux-bbd44f6bd9d1aa735b180b29b5719d63a8e87b55.tar.gz linux-bbd44f6bd9d1aa735b180b29b5719d63a8e87b55.tar.xz | |
ARM: at91/avr32/atmel_lcdfb: add platform device-id table
Add platform device-id table in order to identify the controller and
determine its configuration.
The currently used configuration parameters are:
have_alt_pixclock
- SOC uses an alternate pixel-clock calculation formula (at91sam9g45
non-ES)
have_hozval
- SOC has a HOZVAL field in LCDFRMCFG which is used to determine the
linesize for STN displays (at91sam9261, at921sam9g10 and at32ap)
have_intensity_bit
- SOC uses IBGR:555 rather than BGR:565 16-bit pixel layout
(at91sam9261, at91sam9263 and at91sam9rl)
This allows us to remove all the remaining uses of cpu_is macros from
the driver.
Tested on at91sam9263 and at91sam9g45, compile-tested for other
AT91-SOCs, and untested for AVR32.
Signed-off-by: Johan Hovold <jhovold@gmail.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'include/video')
| -rw-r--r-- | include/video/atmel_lcdc.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h index 8deb22672ada..0f5a2fc69af9 100644 --- a/include/video/atmel_lcdc.h +++ b/include/video/atmel_lcdc.h @@ -31,6 +31,7 @@ #define ATMEL_LCDC_WIRING_BGR 0 #define ATMEL_LCDC_WIRING_RGB 1 +struct atmel_lcdfb_config; /* LCD Controller info data structure, stored in device platform_data */ struct atmel_lcdfb_info { @@ -61,7 +62,8 @@ struct atmel_lcdfb_info { void (*atmel_lcdfb_power_control)(int on); struct fb_monspecs *default_monspecs; u32 pseudo_palette[16]; - bool have_intensity_bit; + + struct atmel_lcdfb_config *config; }; #define ATMEL_LCDC_DMABADDR1 0x00 |