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* MIPS: Remove r2_emul_return from struct thread_infoPaul Burton2017-01-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The r2_emul_return field in struct thread_info was used in order to take an alternate codepath when returning to userland, which (besides not implementing certain features) effectively used the eretnc instruction in place of eret. The difference is that eretnc doesn't clear LLBit, and therefore doesn't cause a linked load & store sequence to fail due to emulation like eret would. The reason eret would usually be used to clear LLBit is so that after context switching we ensure that a load performed by one task doesn't influence another task. However commit 7c151d3d5d7a ("MIPS: Make use of the ERETNC instruction on MIPS R6") which introduced the r2_emul_return field and conditional use of eretnc also for some reason began explicitly clearing LLBit during context switches - despite retaining the use of eret for everything but returns from the pre-r6 instruction emulation code. As LLBit is cleared upon context switches anyway, simplify this by using eretnc unconditionally for MIPSr6 kernels. This allows us to remove the 4 byte r2_emul_return boolean from struct thread_info, simplify the return to user code in entry.S and avoid the overhead of tracking & checking state which we don't need. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14408/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add uprobes support.Ralf Baechle2015-09-031-1/+4
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-04-171-2/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS for Linux 4.1. Most noteworthy: - Add more Octeon-optimized crypto functions - Octeon crypto preemption and locking fixes - Little endian support for Octeon - Use correct CSR to soft reset Octeons - Support LEDs on the Octeon-based DSR-1000N - Fix PCI interrupt mapping for the Octeon-based DSR-1000N - Mark prom_free_prom_memory() as __init for a number of systems - Support for Imagination's Pistachio SOC. This includes arch and CLK bits. I'd like to merge pinctrl bits later - Improve parallelism of csum_partial for certain pipelines - Organize DTB files in subdirs like other architectures - Implement read_sched_clock for all MIPS platforms other than Octeon - Massive series of 38 fixes and cleanups for the FPU emulator / kernel - Further FPU remulator work to support new features. This sits on a separate branch which also has been pulled into the 4.1 KVM branch - Clean up and fixes for the SEAD3 eval board; remove unused file - Various updates for Netlogic platforms - A number of small updates for Loongson 3 platforms - Increase the memory limit for ATH79 platforms to 256MB - A fair number of fixes and updates for BCM47xx platforms - Finish the implementation of XPA support - MIPS FDC support. No, not floppy controller but Fast Debug Channel :) - Detect the R16000 used in SGI legacy platforms - Fix Kconfig dependencies for the SSB bus support" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (265 commits) MIPS: Makefile: Fix MIPS ASE detection code MIPS: asm: elf: Set O32 default FPU flags MIPS: BCM47XX: Fix detecting Microsoft MN-700 & Asus WL500G MIPS: Kconfig: Disable SMP/CPS for 64-bit MIPS: Hibernate: flush TLB entries earlier MIPS: smp-cps: cpu_set FPU mask if FPU present MIPS: lose_fpu(): Disable FPU when MSA enabled MIPS: ralink: add missing symbol for RALINK_ILL_ACC MIPS: ralink: Fix bad config symbol in PCI makefile. SSB: fix Kconfig dependencies MIPS: Malta: Detect and fix bad memsize values Revert "MIPS: Avoid pipeline stalls on some MIPS32R2 cores." MIPS: Octeon: Delete override of cpu_has_mips_r2_exec_hazard. MIPS: Fix cpu_has_mips_r2_exec_hazard. MIPS: kernel: entry.S: Set correct ISA level for mips_ihb MIPS: asm: spinlock: Fix addiu instruction for R10000_LLSC_WAR case MIPS: r4kcache: Use correct base register for MIPS R6 cache flushes MIPS: Kconfig: Fix typo for the r2-to-r6 emulator kernel parameter MIPS: unaligned: Fix regular load/store instruction emulation for EVA MIPS: unaligned: Surround load/store macros in do {} while statements ...
| * MIPS: Changed current_thread_info() to an equivalent supported by both clang ↵Daniel Sanders2015-04-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and GCC Without this, a 'break' instruction is executed very early in the boot and the boot hangs. The problem is that clang doesn't honour named registers on local variables and silently treats them as normal uninitialized variables. However, it does honour them on global variables. Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: David Daney <ddaney.cavm@gmail.com> Acked-by: Behan Webster <behanw@converseincode.com> Patchwork: https://patchwork.linux-mips.org/patch/9311/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* | arch: Remove exec_domain from remaining archsRichard Weinberger2015-04-121-2/+0
|/ | | | Signed-off-by: Richard Weinberger <richard@nod.at>
* Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linusLinus Torvalds2015-02-211-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS: - a number of fixes that didn't make the 3.19 release. - a number of cleanups. - preliminary support for Cavium's Octeon 3 SOCs which feature up to 48 MIPS64 R3 cores with FPU and hardware virtualization. - support for MIPS R6 processors. Revision 6 of the MIPS architecture is a major revision of the MIPS architecture which does away with many of original sins of the architecture such as branch delay slots. This and other changes in R6 require major changes throughout the entire MIPS core architecture code and make up for the lion share of this pull request. - finally some preparatory work for eXtendend Physical Address support, which allows support of up to 40 bit of physical address space on 32 bit processors" [ Ahh, MIPS can't leave the PAE brain damage alone. It's like every CPU architect has to make that mistake, but pee in the snow by changing the TLA. But whether it's called PAE, LPAE or XPA, it's horrid crud - Linus ] * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits) MIPS: sead3: Corrected get_c0_perfcount_int MIPS: mm: Remove dead macro definitions MIPS: OCTEON: irq: add CIB and other fixes MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs. MIPS: OCTEON: More OCTEONIII support MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup. MIPS: OCTEON: Update octeon-model.h code for new SoCs. MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h MIPS: OCTEON: Implement the core-16057 workaround MIPS: OCTEON: Delete unused COP2 saving code MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register MIPS: OCTEON: Save and restore CP2 SHA3 state MIPS: OCTEON: Fix FP context save. MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs MIPS: boot: Provide more uImage options MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h MIPS: ip22-gio: Remove legacy suspend/resume support mips: pci: Add ifdef around pci_proc_domain ...
| * MIPS: Make use of the ERETNC instruction on MIPS R6Markos Chandras2015-02-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The ERETNC instruction, introduced in MIPS R5, is similar to the ERET one, except it does not clear the LLB bit in the LLADDR register. This feature is necessary to safely emulate R2 LL/SC instructions. However, on context switches, we need to clear the LLAddr/LLB bit in order to make sure that an SC instruction from the new thread will never succeed if it happens to interrupt an LL operation on the same address from the previous thread. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* | all arches, signal: move restart_block to struct task_structAndy Lutomirski2015-02-121-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an attacker can cause a controlled kernel stack overflow, overwriting the restart block is a very juicy exploit target. This is because the restart_block is held in the same memory allocation as the kernel stack. Moving the restart block to struct task_struct prevents this exploit by making the restart_block harder to locate. Note that there are other fields in thread_info that are also easy targets, at least on some architectures. It's also a decent simplification, since the restart code is more or less identical on all architectures. [james.hogan@imgtec.com: metag: align thread_info::supervisor_stack] Signed-off-by: Andy Lutomirski <luto@amacapital.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Al Viro <viro@zeniv.linux.org.uk> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@kernel.org> Cc: Kees Cook <keescook@chromium.org> Cc: David Miller <davem@davemloft.net> Acked-by: Richard Weinberger <richard@nod.at> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Haavard Skinnemoen <hskinnemoen@gmail.com> Cc: Hans-Christian Egtvedt <egtvedt@samfundet.no> Cc: Steven Miao <realmz6@gmail.com> Cc: Mark Salter <msalter@redhat.com> Cc: Aurelien Jacquiot <a-jacquiot@ti.com> Cc: Mikael Starvik <starvik@axis.com> Cc: Jesper Nilsson <jesper.nilsson@axis.com> Cc: David Howells <dhowells@redhat.com> Cc: Richard Kuo <rkuo@codeaurora.org> Cc: "Luck, Tony" <tony.luck@intel.com> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Michal Simek <monstr@monstr.eu> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Jonas Bonn <jonas@southpole.se> Cc: "James E.J. Bottomley" <jejb@parisc-linux.org> Cc: Helge Deller <deller@gmx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Tested-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Cc: Martin Schwidefsky <schwidefsky@de.ibm.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: Chen Liqin <liqin.linux@gmail.com> Cc: Lennox Wu <lennox.wu@gmail.com> Cc: Chris Metcalf <cmetcalf@ezchip.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Chris Zankel <chris@zankel.net> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Oleg Nesterov <oleg@redhat.com> Cc: Guenter Roeck <linux@roeck-us.net> Signed-off-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | MIPS: Fix syscall_get_nr for the syscall exit tracing.Lars Persson2015-02-041-0/+1
|/ | | | | | | | | | Register 2 is alredy overwritten by the return value when syscall_trace_leave() is called. Signed-off-by: Lars Persson <larper@axis.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9187/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support for hybrid FPRsPaul Burton2014-11-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: MT: Remove SMTC supportRalf Baechle2014-05-241-10/+1
| | | | | | | | | | | | | | | Nobody is maintaining SMTC anymore and there also seems to be no userbase. Which is a pity - the SMTC technology primarily developed by Kevin D. Kissell <kevink@paralogos.com> is an ingenious demonstration for the MT ASE's power and elegance. Based on Markos Chandras <Markos.Chandras@imgtec.com> patch https://patchwork.linux-mips.org/patch/6719/ which while very similar did no longer apply cleanly when I tried to merge it plus some additional post-SMTC cleanup - SMTC was a feature as tricky to remove as it was to merge once upon a time. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Basic MSA context switching supportPaul Burton2014-03-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for context switching the MSA vector registers. These 128 bit vector registers are aliased with the FP registers - an FP register accesses the least significant bits of the vector register with which it is aliased (ie. the register with the same index). Due to both this & the requirement that the scalar FPU must be 64-bit (FR=1) if enabled at the same time as MSA the kernel will enable MSA & scalar FP at the same time for tasks which use MSA. If we restore the MSA vector context then we might as well enable the scalar FPU since the reason it was left disabled was to allow for lazy FP context restoring - but we just restored the FP context as it's a subset of the vector context. If we restore the FP context and have previously used MSA then we have to restore the whole vector context anyway (see comment in enable_restore_fp_context for details) so similarly we might as well enable MSA. Thus if a task does not use MSA then it will continue to behave as without this patch - the scalar FP context will be saved & restored as usual. But if a task executes an MSA instruction then it will save & restore the vector context forever more. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6431/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: asm: thread_info: Add _TIF_SECCOMP flagMarkos Chandras2014-03-261-1/+2
| | | | | | | | | | | | Add _TIF_SECCOMP flag to _TIF_WORK_SYSCALL_ENTRY to indicate that the system call needs to be checked against a seccomp filter. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6405/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Support for 64-bit FP with O32 binariesPaul Burton2014-01-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CPUs implementing MIPS32 R2 may include a 64-bit FPU, just as MIPS64 CPUs do. In order to preserve backwards compatibility a 64-bit FPU will act like a 32-bit FPU (by accessing doubles from the least significant 32 bits of an even-odd pair of FP registers) when the Status.FR bit is zero, again just like a mips64 CPU. The standard O32 ABI is defined expecting a 32-bit FPU, however recent toolchains support use of a 64-bit FPU from an O32 MIPS32 executable. When an ELF executable is built to use a 64-bit FPU a new flag (EF_MIPS_FP64) is set in the ELF header. With this patch the kernel will check the EF_MIPS_FP64 flag when executing an O32 binary, and set Status.FR accordingly. The addition of O32 64-bit FP support lessens the opportunity for optimisation in the FPU emulator, so a CONFIG_MIPS_O32_FP64_SUPPORT Kconfig option is introduced to allow this support to be disabled for those that don't require it. Inspired by an earlier patch by Leonid Yegoshin, but implemented more cleanly & correctly. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paul Burton <paul.burton@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/6154/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* preempt: Make PREEMPT_ACTIVE genericThomas Gleixner2013-11-131-2/+0
| | | | | | | | No point in having this bit defined by architecture. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/20130917183629.090698799@linutronix.de
* MIPS: ftrace: Add support for syscall tracepoints.Ralf Baechle2013-10-291-3/+6
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Move definition of SMP processor id register to header fileJayachandran C2013-10-291-1/+32
| | | | | | | | | | The definition of the CP0 register used to save the smp processor id is repicated in many files, move them all to thread_info.h. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Implement HAVE_CONTEXT_TRACKING.Ralf Baechle2013-06-101-3/+8
| | | | | | This enables support for CONFIG_NO_HZ_FULL. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Cleanup flags in syscall flags handlers.Ralf Baechle2013-06-101-0/+2
| | | | | | This will simplify further modifications. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Use inline function to access current thread pointer.Ralf Baechle2013-04-111-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With LTE this fixes this issue: LDFINAL vmlinux.o arch/mips/built-in.o (symbol from plugin): In function `sgimc_init': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here kernel/built-in.o (symbol from plugin): In function `get_task_mm': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here mm/built-in.o (symbol from plugin): In function `iov_iter_single_seg_count': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here fs/built-in.o (symbol from plugin): In function `finish_no_open': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here ipc/built-in.o (symbol from plugin): In function `ipc_init_ids': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here security/built-in.o (symbol from plugin): In function `key_schedule_gc': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here crypto/built-in.o (symbol from plugin): In function `crypto_find_alg': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here block/built-in.o (symbol from plugin): In function `elv_rb_find': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here argv_split.o (symbol from plugin): In function `argv_free': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here dec_and_lock.o (symbol from plugin): In function `_atomic_dec_and_lock': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here extable.o (symbol from plugin): In function `sort_extable': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here flex_proportions.o (symbol from plugin): In function `fprop_global_init': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here idr.o (symbol from plugin): In function `idr_for_each': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here is_single_threaded.o (symbol from plugin): In function `current_is_single_threaded': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here kobject.o (symbol from plugin): In function `kobject_get': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here kobject_uevent.o (symbol from plugin): In function `add_uevent_var': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here plist.o (symbol from plugin): In function `plist_add': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here radix-tree.o (symbol from plugin): In function `radix_tree_lookup_slot': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here ratelimit.o (symbol from plugin): In function `___ratelimit': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here rwsem-spinlock.o (symbol from plugin): In function `__init_rwsem': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here show_mem.o (symbol from plugin): In function `show_mem': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here timerqueue.o (symbol from plugin): In function `timerqueue_iterate_next': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here vsprintf.o (symbol from plugin): In function `simple_strtoull': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here delay.o (symbol from plugin): In function `__delay': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here mips-atomic.o (symbol from plugin): In function `arch_local_irq_disable': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here uncached.o (symbol from plugin): In function `run_uncached': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here lib/built-in.o (symbol from plugin): In function `_bcd2bin': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here arch/mips/lib/built-in.o (symbol from plugin): In function `ioread8': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here drivers/built-in.o (symbol from plugin): In function `fb_notifier_call_chain': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here net/built-in.o (symbol from plugin): In function `sock_from_file': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here klist.o (symbol from plugin): In function `klist_init': (.text+0x0): multiple definition of `$28' init/built-in.o (symbol from plugin):(.text+0x0): first defined here It also makes the code a little more readable, so let's merge it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Whitespace cleanup.Ralf Baechle2013-02-011-1/+1
| | | | | | | | Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix comment.Ralf Baechle2012-12-271-4/+5
| | | | | | The value is incorrect and were copied in Linux 2.5.4 from i386. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: compat: Delete now unused TIF_32BIT.Ralf Baechle2012-11-091-6/+0
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: compat: Fix use of TIF_32BIT_ADDR vs _TIF_32BIT_ADDRRalf Baechle2012-11-091-1/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* sanitize tsk_is_polling()Al Viro2012-10-011-2/+0
| | | | | | | | | | | | Make default just return 0. The current default (checking TIF_POLLING_NRFLAG) is taken to architectures that need it; ones that don't do polling in their idle threads don't need to defined TIF_POLLING_NRFLAG at all. ia64 defined both TS_POLLING (used by its tsk_is_polling()) and TIF_POLLING_NRFLAG (not used at all). Killed the latter... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* bury _TIF_RESTORE_SIGMASKAl Viro2012-10-011-1/+0
| | | | | | never used... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* mips: NOTIFY_RESUME is not needed in TIF masksAl Viro2012-10-011-2/+1
| | | | | | | If it's set, SIGPENDING is also set. And SIGPENDING is present in the masks... Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* mips: unobfuscate _TIF..._MASKAl Viro2012-10-011-3/+4
| | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
* MIPS: Properly align the .data..init_task section.David Daney2012-07-191-2/+2
| | | | | | | | | | | | | | | | Improper alignment can lead to unbootable systems and/or random crashes. [ralf@linux-mips.org: This is a lond standing bug since 6eb10bc9e2deab06630261cd05c4cb1e9a60e980 (kernel.org) rsp. c422a10917f75fd19fa7fe070aaaa23e384dae6f (lmo) [MIPS: Clean up linker script using new linker script macros.] so dates back to 2.6.32.] Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> Patchwork: https://patchwork.linux-mips.org/patch/3881/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mips: Use common threadinfo allocatorThomas Gleixner2012-05-081-12/+0
| | | | | | | | | No point in using kmalloc for allocating 0, 1 resp. 2 pages for threadinfo. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Ralf Baechle <ralf@linux-mips.org> Link: http://lkml.kernel.org/r/20120505150141.936950979@linutronix.de
* freezer: remove now unused TIF_FREEZETejun Heo2011-11-211-2/+0
| | | | | | Signed-off-by: Tejun Heo <tj@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: linux-arch@vger.kernel.org
* MIPS: Use single define for pending work on syscall exitRalf Baechle2011-05-191-0/+3
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* mm: NUMA aware alloc_thread_info_node()Eric Dumazet2011-03-221-2/+4
| | | | | | | | | | | | | | | | | | | Add a node parameter to alloc_thread_info(), and change its name to alloc_thread_info_node() This change is needed to allow NUMA aware kthread_create_on_cpu() Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com> Acked-by: David S. Miller <davem@davemloft.net> Reviewed-by: Andi Kleen <ak@linux.intel.com> Acked-by: Rusty Russell <rusty@rustcorp.com.au> Cc: Tejun Heo <tj@kernel.org> Cc: Tony Luck <tony.luck@intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: David Howells <dhowells@redhat.com> Cc: <linux-arch@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: IRQ: Add stackoverflow detectionFrom: jiang.adam@gmail.com2010-10-291-0/+2
| | | | | | | | | | | | | | | | | | | Add stackoverflow detection to mips arch Signed-off-by: Adam Jiang <jiang.adam@gmail.com> Cc: dmitri.vorobiev@movial.com Cc: wuzhangjin@gmail.com Cc: ddaney@caviumnetworks.com Cc: peterz@infradead.org Cc: fweisbec@gmail.com Cc: tj@kernel.org Cc: tglx@linutronix.de Cc: mingo@elte.hu Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1559/ Patchwork: https://patchwork.linux-mips.org/patch/1651/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Audit: Fix hang in entry.S.Ralf Baechle2010-10-041-1/+2
| | | | | | | | | | | _TIF_WORK_MASK false had _TIF_SYSCALL_AUDIT set. If a thread's _TIF_SYSCALL_AUDIT is ever set this will lead to an endless loop on the way out from a syscall. Currently this is only a theoretic bug as init/Kconfig doesn't allow AUDIT_SYSCALL to be enabled for MIPS. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* add descriptive comment for TIF_MEMDIE task flag declaration.Andreas Dilger2010-05-141-1/+1
| | | | | | Signed-off-by: Andreas Dilger <adilger@dilger.ca> Acked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* MIPS: Cleanup CONFIG_DEBUG_STACK_USAGE version of alloc_thread_info.Ralf Baechle2009-11-021-8/+1
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* KEYS: Extend TIF_NOTIFY_RESUME to (almost) all architectures [try #6]David Howells2009-09-021-0/+2
| | | | | | | | | | | | | | | | | Implement TIF_NOTIFY_RESUME for most of those architectures in which isn't yet available, and, whilst we're at it, have it call the appropriate tracehook. After this patch, blackfin, m68k* and xtensa still lack support and need alteration of assembly code to make it work. Resume notification can then be used (by a later patch) to install a new session keyring on the parent of a process. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Russell King <rmk+kernel@arm.linux.org.uk> cc: linux-arch@vger.kernel.org Signed-off-by: James Morris <jmorris@namei.org>
* sched: INIT_PREEMPT_COUNTPeter Zijlstra2009-07-101-3/+1
| | | | | | | | | | | | | | | | | | | | | Pull the initial preempt_count value into a single definition site. Maintainers for: alpha, ia64 and m68k, please have a look, your arch code is funny. The header magic is a bit odd, but similar to the KERNEL_DS one, CPP waits with expanding these macros until the INIT_THREAD_INFO macro itself is expanded, which is in arch/*/kernel/init_task.c where we've already included sched.h so we're good. Cc: tony.luck@intel.com Cc: rth@twiddle.net Cc: geert@linux-m68k.org Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Acked-by: Matt Mackall <mpm@selenic.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* MIPS: Cavium: Add support for 8k and 32k page sizes.Ralf Baechle2009-05-141-0/+3
| | | | | | | | Beyond the requirements of the architecture standard Cavium also supports 8k and 32k pages. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
* MIPS: Fix TIF_32BIT undefined problem when seccomp is disabledZhang Le2009-03-131-0/+6
| | | | | Signed-off-by: Zhang Le <r0bertz@gentoo.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add HARDWARE_WATCHPOINTS definitions and support code.David Daney2008-10-111-0/+2
| | | | | | | | | | | This is the main support code for the patch. Here we just add the code, the following patches hook it up. Signed-off-by: David Daney <ddaney@avtrex.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> create mode 100644 arch/mips/include/asm/watch.h create mode 100644 arch/mips/kernel/watch.c
* MIPS: Move headfiles to new location below arch/mips/includeRalf Baechle2008-10-111-0/+151
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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