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path: root/arch/mips/kernel/traps.c
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* MIPS: Clean up notify_die() usage.David Daney2010-08-051-10/+15
* MIPS: Remove unused task_struct.trap_no field.David Daney2010-08-051-1/+1
* MIPS: kprobe: Add support.David Daney2010-08-051-1/+21
* MIPS: Provide more elevant interface cu2_notifier for CP2 extensions.Ralf Baechle2010-08-051-6/+1
* MIPS: Return after handling coprocessor 2 exceptionJesper Nilsson2010-07-051-1/+1
* Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2010-05-211-1/+1
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| * MIPS: Use set_cpus_allowed_ptrJulia Lawall2010-05-211-1/+1
* | mips,kgdb: kdb low level trap catch and stack traceJason Wessel2010-05-201-0/+13
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* MIPS: Use CKSEG1ADDR for uncached handlerSebastian Andrzej Siewior2010-04-301-6/+1
* MIPS: die() does not call die notifier chainYury Polyanskiy2010-04-301-2/+7
* MIPS: Calculate proper ebase value for 64-bit kernelsDavid Daney2010-04-121-1/+1
* MIPS: Deal with larger physical offsetsFlorian Fainelli2010-02-271-8/+13
* MIPS: Annotate set_except_vector with __initFlorian Fainelli2010-02-271-1/+1
* MIPS: Fixup of the r4k timerWu Zhangjin2010-02-101-0/+1
* MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQsDavid VomLehn2010-01-281-2/+4
* MIPS: Cleanup signal code initializationRalf Baechle2009-12-171-76/+0
* MIPS: Modularize COP2 handlingRalf Baechle2009-12-171-15/+45
* MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assemblerRalf Baechle2009-09-171-3/+2
* MIPS: Move Cavium CP0 hwrena impl bits to cpu-feature-overrides.hDavid Daney2009-06-171-4/+0
* MIPS: Allow CPU specific overriding of CP0 hwrena impl bits.David Daney2009-06-171-1/+1
* MIPS: Use BUG_ON() where possible.Ralf Baechle2009-03-301-2/+1
* MIPS: R2: Fix problem with code that incorrectly modifies ebase.Chris Dearman2009-03-231-5/+7
* MIPS: Read watch registers with interrupts disabled.David Daney2009-01-301-1/+7
* MIPS: R2: Fix broken installation of cache error handler.Ralf Baechle2009-01-301-2/+6
* MIPS: For Cavium OCTEON set hwrena and lazily restore CP2 state.David Daney2009-01-111-0/+21
* MIPS: Switch FPU emulator trap to BREAK instruction.Ralf Baechle2008-10-301-0/+16
* MIPS: Consider value of c0_ebase when computing value of exception base.David Daney2008-10-301-4/+9
* MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.David Daney2008-10-111-5/+19
* [MIPS] SMTC: Fix holes in SMTC and FPU affinity support.Kevin D. Kissell2008-10-031-2/+4
* [MIPS] Fix potential latency problem due to non-atomic cpu_wait.Atsushi Nemoto2008-09-211-6/+16
* [MIPS] Fix WARNING: at kernel/smp.c:290Thomas Bogendoerfer2008-09-051-5/+7
* [MIPS] Fix data bus error recoveryThomas Bogendoerfer2008-09-051-2/+4
* [MIPS] kgdb: add arch support for the kernel's kgdb coreJason Wessel2008-07-301-0/+21
* [MIPS] Replace use of print_symbol with new %sP pointer format.Ralf Baechle2008-07-151-4/+4
* [MIPS] Remove board_watchpoint_handlerDavid Daney2008-07-151-6/+0
* [MIPS] Fix check for valid stack pointer during backtraceThomas Bogendoerfer2008-06-051-7/+9
* [MIPS] Fix handling of trap and breakpoint instructionsRalf Baechle2008-04-281-52/+37
* [MIPS] Add support for MIPS CMP platform.Ralf Baechle2008-04-281-12/+99
* [MIPS] Add noulri kernel argument to disable "rdhwr $29" usermode support.Chris Dearman2008-04-281-1/+12
* [MIPS] Fix loads of section missmatchesRalf Baechle2008-03-121-3/+4
* [MIPS] Added missing cases for rdhwr emulationChris Dearman2008-03-121-6/+25
* [MIPS] Ensure that ST0_FR is never set on a 32 bit kernelChris Dearman2007-12-141-3/+3
* [MIPS] Fix shadow register support.Ralf Baechle2007-11-151-65/+3
* Use helpers to obtain task pid in printks (arch code)Alexey Dobriyan2007-10-191-1/+1
* [MIPS] time: Move R4000 clockevent device code to separate configurable fileRalf Baechle2007-10-181-0/+11
* [MIPS] SYNC emulation for MIPS I processorsMaciej W. Rozycki2007-10-171-78/+86
* [MIPS] IP22: Fix warning.Ralf Baechle2007-10-161-6/+15
* [MIPS] Make facility to convert CPU types to strings generally available.Ralf Baechle2007-10-111-1/+2
* [MIPS] Fix "no space between function name and open parenthesis" warnings.Ralf Baechle2007-10-111-13/+13
* [MIPS] Allow hardwiring of the CPU type to a single type for optimization.Ralf Baechle2007-10-111-3/+3
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