summaryrefslogtreecommitdiffstats
path: root/arch/blackfin/mach-bf609/dma.c
blob: 1da4b38ac22c3a67ef59e46dfbe972c0c1c96805 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
/*
 * the simple DMA Implementation for Blackfin
 *
 * Copyright 2007-2009 Analog Devices Inc.
 *
 * Licensed under the GPL-2 or later.
 */

#include <linux/module.h>

#include <asm/blackfin.h>
#include <asm/dma.h>

struct dma_register * const dma_io_base_addr[MAX_DMA_CHANNELS] = {
	(struct dma_register *) DMA0_NEXT_DESC_PTR,
	(struct dma_register *) DMA1_NEXT_DESC_PTR,
	(struct dma_register *) DMA2_NEXT_DESC_PTR,
	(struct dma_register *) DMA3_NEXT_DESC_PTR,
	(struct dma_register *) DMA4_NEXT_DESC_PTR,
	(struct dma_register *) DMA5_NEXT_DESC_PTR,
	(struct dma_register *) DMA6_NEXT_DESC_PTR,
	(struct dma_register *) DMA7_NEXT_DESC_PTR,
	(struct dma_register *) DMA8_NEXT_DESC_PTR,
	(struct dma_register *) DMA9_NEXT_DESC_PTR,
	(struct dma_register *) DMA10_NEXT_DESC_PTR,
	(struct dma_register *) DMA11_NEXT_DESC_PTR,
	(struct dma_register *) DMA12_NEXT_DESC_PTR,
	(struct dma_register *) DMA13_NEXT_DESC_PTR,
	(struct dma_register *) DMA14_NEXT_DESC_PTR,
	(struct dma_register *) DMA15_NEXT_DESC_PTR,
	(struct dma_register *) DMA16_NEXT_DESC_PTR,
	(struct dma_register *) DMA17_NEXT_DESC_PTR,
	(struct dma_register *) DMA18_NEXT_DESC_PTR,
	(struct dma_register *) DMA19_NEXT_DESC_PTR,
	(struct dma_register *) DMA20_NEXT_DESC_PTR,
	(struct dma_register *) MDMA0_SRC_CRC0_NEXT_DESC_PTR,
	(struct dma_register *) MDMA0_DEST_CRC0_NEXT_DESC_PTR,
	(struct dma_register *) MDMA1_SRC_CRC1_NEXT_DESC_PTR,
	(struct dma_register *) MDMA1_DEST_CRC1_NEXT_DESC_PTR,
	(struct dma_register *) MDMA2_SRC_NEXT_DESC_PTR,
	(struct dma_register *) MDMA2_DEST_NEXT_DESC_PTR,
	(struct dma_register *) MDMA3_SRC_NEXT_DESC_PTR,
	(struct dma_register *) MDMA3_DEST_NEXT_DESC_PTR,
	(struct dma_register *) DMA29_NEXT_DESC_PTR,
	(struct dma_register *) DMA30_NEXT_DESC_PTR,
	(struct dma_register *) DMA31_NEXT_DESC_PTR,
	(struct dma_register *) DMA32_NEXT_DESC_PTR,
	(struct dma_register *) DMA33_NEXT_DESC_PTR,
	(struct dma_register *) DMA34_NEXT_DESC_PTR,
	(struct dma_register *) DMA35_NEXT_DESC_PTR,
	(struct dma_register *) DMA36_NEXT_DESC_PTR,
	(struct dma_register *) DMA37_NEXT_DESC_PTR,
	(struct dma_register *) DMA38_NEXT_DESC_PTR,
	(struct dma_register *) DMA39_NEXT_DESC_PTR,
	(struct dma_register *) DMA40_NEXT_DESC_PTR,
	(struct dma_register *) DMA41_NEXT_DESC_PTR,
	(struct dma_register *) DMA42_NEXT_DESC_PTR,
	(struct dma_register *) DMA43_NEXT_DESC_PTR,
	(struct dma_register *) DMA44_NEXT_DESC_PTR,
	(struct dma_register *) DMA45_NEXT_DESC_PTR,
	(struct dma_register *) DMA46_NEXT_DESC_PTR,
};
EXPORT_SYMBOL(dma_io_base_addr);

int channel2irq(unsigned int channel)
{
	int ret_irq = -1;

	switch (channel) {
	case CH_SPORT0_RX:
		ret_irq = IRQ_SPORT0_RX;
		break;
	case CH_SPORT0_TX:
		ret_irq = IRQ_SPORT0_TX;
		break;
	case CH_SPORT1_RX:
		ret_irq = IRQ_SPORT1_RX;
		break;
	case CH_SPORT1_TX:
		ret_irq = IRQ_SPORT1_TX;
		break;
	case CH_SPORT2_RX:
		ret_irq = IRQ_SPORT2_RX;
		break;
	case CH_SPORT2_TX:
		ret_irq = IRQ_SPORT2_TX;
		break;
	case CH_SPI0_TX:
		ret_irq = IRQ_SPI0_TX;
		break;
	case CH_SPI0_RX:
		ret_irq = IRQ_SPI0_RX;
		break;
	case CH_SPI1_TX:
		ret_irq = IRQ_SPI1_TX;
		break;
	case CH_SPI1_RX:
		ret_irq = IRQ_SPI1_RX;
		break;
	case CH_RSI:
		ret_irq = IRQ_RSI;
		break;
	case CH_SDU:
		ret_irq = IRQ_SDU;
		break;
	case CH_LP0:
		ret_irq = IRQ_LP0;
		break;
	case CH_LP1:
		ret_irq = IRQ_LP1;
		break;
	case CH_LP2:
		ret_irq = IRQ_LP2;
		break;
	case CH_LP3:
		ret_irq = IRQ_LP3;
		break;
	case CH_UART0_RX:
		ret_irq = IRQ_UART0_RX;
		break;
	case CH_UART0_TX:
		ret_irq = IRQ_UART0_TX;
		break;
	case CH_UART1_RX:
		ret_irq = IRQ_UART1_RX;
		break;
	case CH_UART1_TX:
		ret_irq = IRQ_UART1_TX;
		break;
	case CH_EPPI0_CH0:
		ret_irq = IRQ_EPPI0_CH0;
		break;
	case CH_EPPI0_CH1:
		ret_irq = IRQ_EPPI0_CH1;
		break;
	case CH_EPPI1_CH0:
		ret_irq = IRQ_EPPI1_CH0;
		break;
	case CH_EPPI1_CH1:
		ret_irq = IRQ_EPPI1_CH1;
		break;
	case CH_EPPI2_CH0:
		ret_irq = IRQ_EPPI2_CH0;
		break;
	case CH_EPPI2_CH1:
		ret_irq = IRQ_EPPI2_CH1;
		break;
	case CH_PIXC_CH0:
		ret_irq = IRQ_PIXC_CH0;
		break;
	case CH_PIXC_CH1:
		ret_irq = IRQ_PIXC_CH1;
		break;
	case CH_PIXC_CH2:
		ret_irq = IRQ_PIXC_CH2;
		break;
	case CH_PVP_CPDOB:
		ret_irq = IRQ_PVP_CPDOB;
		break;
	case CH_PVP_CPDOC:
		ret_irq = IRQ_PVP_CPDOC;
		break;
	case CH_PVP_CPSTAT:
		ret_irq = IRQ_PVP_CPSTAT;
		break;
	case CH_PVP_CPCI:
		ret_irq = IRQ_PVP_CPCI;
		break;
	case CH_PVP_MPDO:
		ret_irq = IRQ_PVP_MPDO;
		break;
	case CH_PVP_MPDI:
		ret_irq = IRQ_PVP_MPDI;
		break;
	case CH_PVP_MPSTAT:
		ret_irq = IRQ_PVP_MPSTAT;
		break;
	case CH_PVP_MPCI:
		ret_irq = IRQ_PVP_MPCI;
		break;
	case CH_PVP_CPDOA:
		ret_irq = IRQ_PVP_CPDOA;
		break;
	case CH_MEM_STREAM0_SRC:
	case CH_MEM_STREAM0_DEST:
		ret_irq = IRQ_MDMAS0;
		break;
	case CH_MEM_STREAM1_SRC:
	case CH_MEM_STREAM1_DEST:
		ret_irq = IRQ_MDMAS1;
		break;
	case CH_MEM_STREAM2_SRC:
	case CH_MEM_STREAM2_DEST:
		ret_irq = IRQ_MDMAS2;
		break;
	case CH_MEM_STREAM3_SRC:
	case CH_MEM_STREAM3_DEST:
		ret_irq = IRQ_MDMAS3;
		break;
	}
	return ret_irq;
}