etna: make driver more self contained by including generated headers

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>

20 files changed, 4233 insertions, 32 deletions

diff --git a/src/gallium/drivers/etna/etna_asm.h b/src/gallium/drivers/etna/etna_asm.h
index 8ace6ca1d3..c945a52f94 100644
--- a/src/gallium/drivers/etna/etna_asm.h
+++ b/src/gallium/drivers/etna/etna_asm.h
@@ -25,7 +25,7 @@
 #define H_ETNA_ASM
 #include <stdint.h>
 
-#include <etnaviv/isa.xml.h>
+#include "hw/isa.xml.h"
 
 /* Size of an instruction in 32-bit words */
 #define ETNA_INST_SIZE (4)
diff --git a/src/gallium/drivers/etna/etna_blend.c b/src/gallium/drivers/etna/etna_blend.c
index 9536e49a87..3c2ee984d1 100644
--- a/src/gallium/drivers/etna/etna_blend.c
+++ b/src/gallium/drivers/etna/etna_blend.c
@@ -30,9 +30,9 @@
 #include "pipe/p_state.h"
 #include "util/u_memory.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 static void *etna_pipe_create_blend_state(struct pipe_context *pipe,
                             const struct pipe_blend_state *bs)
diff --git a/src/gallium/drivers/etna/etna_clear_blit.c b/src/gallium/drivers/etna/etna_clear_blit.c
index 89798cb7d6..6312a8f36a 100644
--- a/src/gallium/drivers/etna/etna_clear_blit.c
+++ b/src/gallium/drivers/etna/etna_clear_blit.c
@@ -34,9 +34,9 @@
 #include "util/u_memory.h"
 #include "util/u_surface.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 /* Save current state for blitter operation */
 static void etna_pipe_blit_save_state(struct pipe_context *pipe)
diff --git a/src/gallium/drivers/etna/etna_compiler.c b/src/gallium/drivers/etna/etna_compiler.c
index fe4fc919b7..003dd756e5 100644
--- a/src/gallium/drivers/etna/etna_compiler.c
+++ b/src/gallium/drivers/etna/etna_compiler.c
@@ -58,8 +58,8 @@
 
 #include <etnaviv/etna.h>
 #include <etnaviv/etna_util.h>
-#include <etnaviv/isa.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/isa.xml.h"
+#include "hw/state_3d.xml.h"
 
 #include <stdio.h>
 #include <sys/types.h>
diff --git a/src/gallium/drivers/etna/etna_internal.h b/src/gallium/drivers/etna/etna_internal.h
index 48d1358997..1b7ada9dc0 100644
--- a/src/gallium/drivers/etna/etna_internal.h
+++ b/src/gallium/drivers/etna/etna_internal.h
@@ -26,8 +26,8 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 #define ETNA_NUM_INPUTS (16)
 #define ETNA_NUM_VARYINGS (16)
diff --git a/src/gallium/drivers/etna/etna_pipe.c b/src/gallium/drivers/etna/etna_pipe.c
index 5104d6b478..eed857ba7a 100644
--- a/src/gallium/drivers/etna/etna_pipe.c
+++ b/src/gallium/drivers/etna/etna_pipe.c
@@ -25,10 +25,10 @@
 #include "etna_pipe.h"
 #include "etna_translate.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
-#include <etnaviv/cmdstream.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
+#include "hw/cmdstream.xml.h"
 #include <etnaviv/viv.h>
 #include <etnaviv/etna.h>
 
diff --git a/src/gallium/drivers/etna/etna_rasterizer.c b/src/gallium/drivers/etna/etna_rasterizer.c
index 691865a5b8..37ad29bb07 100644
--- a/src/gallium/drivers/etna/etna_rasterizer.c
+++ b/src/gallium/drivers/etna/etna_rasterizer.c
@@ -30,9 +30,9 @@
 #include "pipe/p_state.h"
 #include "util/u_memory.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 static void *etna_pipe_create_rasterizer_state(struct pipe_context *pipe,
                                  const struct pipe_rasterizer_state *rs)
diff --git a/src/gallium/drivers/etna/etna_shader.c b/src/gallium/drivers/etna/etna_shader.c
index a76bc240df..6402d38102 100644
--- a/src/gallium/drivers/etna/etna_shader.c
+++ b/src/gallium/drivers/etna/etna_shader.c
@@ -31,7 +31,7 @@
 #include "util/u_memory.h"
 #include "util/u_math.h"
 
-#include <etnaviv/state_3d.xml.h>
+#include "hw/state_3d.xml.h"
 
 /* Fetch uniforms from user buffer, if bound, and mark respective uniform
  * bank as dirty. */
diff --git a/src/gallium/drivers/etna/etna_surface.c b/src/gallium/drivers/etna/etna_surface.c
index 81ff2496e1..4a66f7ebae 100644
--- a/src/gallium/drivers/etna/etna_surface.c
+++ b/src/gallium/drivers/etna/etna_surface.c
@@ -33,9 +33,9 @@
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 static struct pipe_surface *etna_pipe_create_surface(struct pipe_context *pipe,
                                       struct pipe_resource *resource_,
diff --git a/src/gallium/drivers/etna/etna_texture.c b/src/gallium/drivers/etna/etna_texture.c
index a67bbe65ec..0452a8da38 100644
--- a/src/gallium/drivers/etna/etna_texture.c
+++ b/src/gallium/drivers/etna/etna_texture.c
@@ -31,9 +31,9 @@
 #include "util/u_inlines.h"
 #include "util/u_memory.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 static void *etna_pipe_create_sampler_state(struct pipe_context *pipe,
                               const struct pipe_sampler_state *ss)
diff --git a/src/gallium/drivers/etna/etna_translate.h b/src/gallium/drivers/etna/etna_translate.h
index 2ef2f2cc87..273d38a7e1 100644
--- a/src/gallium/drivers/etna/etna_translate.h
+++ b/src/gallium/drivers/etna/etna_translate.h
@@ -28,10 +28,10 @@
 #include "pipe/p_format.h"
 #include "pipe/p_state.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
-#include <etnaviv/cmdstream.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
+#include "hw/cmdstream.xml.h"
 #include <etnaviv/etna_util.h>
 #include <etnaviv/etna_tex.h>
 #include "etna_internal.h"
diff --git a/src/gallium/drivers/etna/etna_zsa.c b/src/gallium/drivers/etna/etna_zsa.c
index 2c711b2f9e..c2a82a6cbc 100644
--- a/src/gallium/drivers/etna/etna_zsa.c
+++ b/src/gallium/drivers/etna/etna_zsa.c
@@ -30,9 +30,9 @@
 #include "pipe/p_state.h"
 #include "util/u_memory.h"
 
-#include <etnaviv/common.xml.h>
-#include <etnaviv/state.xml.h>
-#include <etnaviv/state_3d.xml.h>
+#include "hw/common.xml.h"
+#include "hw/state.xml.h"
+#include "hw/state_3d.xml.h"
 
 static void *etna_pipe_create_depth_stencil_alpha_state(struct pipe_context *pipe,
                                     const struct pipe_depth_stencil_alpha_state *dsa_p)
diff --git a/src/gallium/drivers/etna/hw/cmdstream.xml.h b/src/gallium/drivers/etna/hw/cmdstream.xml.h
new file mode 100644
index 0000000000..392a92969c
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/cmdstream.xml.h
@@ -0,0 +1,218 @@
+#ifndef CMDSTREAM_XML
+#define CMDSTREAM_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/cmdstream.xml (  12589 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml    (  18379 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define FE_OPCODE_LOAD_STATE					0x00000001
+#define FE_OPCODE_END						0x00000002
+#define FE_OPCODE_NOP						0x00000003
+#define FE_OPCODE_DRAW_2D					0x00000004
+#define FE_OPCODE_DRAW_PRIMITIVES				0x00000005
+#define FE_OPCODE_DRAW_INDEXED_PRIMITIVES			0x00000006
+#define FE_OPCODE_WAIT						0x00000007
+#define FE_OPCODE_LINK						0x00000008
+#define FE_OPCODE_STALL						0x00000009
+#define FE_OPCODE_CALL						0x0000000a
+#define FE_OPCODE_RETURN					0x0000000b
+#define FE_OPCODE_CHIP_SELECT					0x0000000d
+#define PRIMITIVE_TYPE_POINTS					0x00000001
+#define PRIMITIVE_TYPE_LINES					0x00000002
+#define PRIMITIVE_TYPE_LINE_STRIP				0x00000003
+#define PRIMITIVE_TYPE_TRIANGLES				0x00000004
+#define PRIMITIVE_TYPE_TRIANGLE_STRIP				0x00000005
+#define PRIMITIVE_TYPE_TRIANGLE_FAN				0x00000006
+#define PRIMITIVE_TYPE_LINE_LOOP				0x00000007
+#define PRIMITIVE_TYPE_QUADS					0x00000008
+#define VIV_FE_LOAD_STATE					0x00000000
+
+#define VIV_FE_LOAD_STATE_HEADER				0x00000000
+#define VIV_FE_LOAD_STATE_HEADER_OP__MASK			0xf8000000
+#define VIV_FE_LOAD_STATE_HEADER_OP__SHIFT			27
+#define VIV_FE_LOAD_STATE_HEADER_OP_LOAD_STATE			0x08000000
+#define VIV_FE_LOAD_STATE_HEADER_FIXP				0x04000000
+#define VIV_FE_LOAD_STATE_HEADER_COUNT__MASK			0x03ff0000
+#define VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT			16
+#define VIV_FE_LOAD_STATE_HEADER_COUNT(x)			(((x) << VIV_FE_LOAD_STATE_HEADER_COUNT__SHIFT) & VIV_FE_LOAD_STATE_HEADER_COUNT__MASK)
+#define VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK			0x0000ffff
+#define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT			0
+#define VIV_FE_LOAD_STATE_HEADER_OFFSET(x)			(((x) << VIV_FE_LOAD_STATE_HEADER_OFFSET__SHIFT) & VIV_FE_LOAD_STATE_HEADER_OFFSET__MASK)
+#define VIV_FE_LOAD_STATE_HEADER_OFFSET__SHR			2
+
+#define VIV_FE_END						0x00000000
+
+#define VIV_FE_END_HEADER					0x00000000
+#define VIV_FE_END_HEADER_EVENT_ID__MASK			0x0000001f
+#define VIV_FE_END_HEADER_EVENT_ID__SHIFT			0
+#define VIV_FE_END_HEADER_EVENT_ID(x)				(((x) << VIV_FE_END_HEADER_EVENT_ID__SHIFT) & VIV_FE_END_HEADER_EVENT_ID__MASK)
+#define VIV_FE_END_HEADER_EVENT_ENABLE				0x00000100
+#define VIV_FE_END_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_END_HEADER_OP__SHIFT				27
+#define VIV_FE_END_HEADER_OP_END				0x10000000
+
+#define VIV_FE_NOP						0x00000000
+
+#define VIV_FE_NOP_HEADER					0x00000000
+#define VIV_FE_NOP_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_NOP_HEADER_OP__SHIFT				27
+#define VIV_FE_NOP_HEADER_OP_NOP				0x18000000
+
+#define VIV_FE_DRAW_2D						0x00000000
+
+#define VIV_FE_DRAW_2D_HEADER					0x00000000
+#define VIV_FE_DRAW_2D_HEADER_COUNT__MASK			0x0000ff00
+#define VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT			8
+#define VIV_FE_DRAW_2D_HEADER_COUNT(x)				(((x) << VIV_FE_DRAW_2D_HEADER_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_COUNT__MASK)
+#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK			0x07ff0000
+#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT			16
+#define VIV_FE_DRAW_2D_HEADER_DATA_COUNT(x)			(((x) << VIV_FE_DRAW_2D_HEADER_DATA_COUNT__SHIFT) & VIV_FE_DRAW_2D_HEADER_DATA_COUNT__MASK)
+#define VIV_FE_DRAW_2D_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_DRAW_2D_HEADER_OP__SHIFT				27
+#define VIV_FE_DRAW_2D_HEADER_OP_DRAW_2D			0x20000000
+
+#define VIV_FE_DRAW_2D_TOP_LEFT					0x00000008
+#define VIV_FE_DRAW_2D_TOP_LEFT_X__MASK				0x0000ffff
+#define VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT			0
+#define VIV_FE_DRAW_2D_TOP_LEFT_X(x)				(((x) << VIV_FE_DRAW_2D_TOP_LEFT_X__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_X__MASK)
+#define VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK				0xffff0000
+#define VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT			16
+#define VIV_FE_DRAW_2D_TOP_LEFT_Y(x)				(((x) << VIV_FE_DRAW_2D_TOP_LEFT_Y__SHIFT) & VIV_FE_DRAW_2D_TOP_LEFT_Y__MASK)
+
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT				0x0000000c
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK			0x0000ffff
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT			0
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_X(x)			(((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_X__MASK)
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK			0xffff0000
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT			16
+#define VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y(x)			(((x) << VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__SHIFT) & VIV_FE_DRAW_2D_BOTTOM_RIGHT_Y__MASK)
+
+#define VIV_FE_DRAW_PRIMITIVES					0x00000000
+
+#define VIV_FE_DRAW_PRIMITIVES_HEADER				0x00000000
+#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__MASK			0xf8000000
+#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP__SHIFT			27
+#define VIV_FE_DRAW_PRIMITIVES_HEADER_OP_DRAW_PRIMITIVES	0x28000000
+
+#define VIV_FE_DRAW_PRIMITIVES_COMMAND				0x00000004
+#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK		0x000000ff
+#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT		0
+#define VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE(x)			(((x) << VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_PRIMITIVES_COMMAND_TYPE__MASK)
+
+#define VIV_FE_DRAW_PRIMITIVES_START				0x00000008
+
+#define VIV_FE_DRAW_PRIMITIVES_COUNT				0x0000000c
+
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES				0x00000000
+
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER			0x00000000
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__MASK		0xf8000000
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP__SHIFT		27
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_HEADER_OP_DRAW_INDEXED_PRIMITIVES	0x30000000
+
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND			0x00000004
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK	0x000000ff
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT	0
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE(x)		(((x) << VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__SHIFT) & VIV_FE_DRAW_INDEXED_PRIMITIVES_COMMAND_TYPE__MASK)
+
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_START			0x00000008
+
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_COUNT			0x0000000c
+
+#define VIV_FE_DRAW_INDEXED_PRIMITIVES_OFFSET			0x00000010
+
+#define VIV_FE_WAIT						0x00000000
+
+#define VIV_FE_WAIT_HEADER					0x00000000
+#define VIV_FE_WAIT_HEADER_DELAY__MASK				0x0000ffff
+#define VIV_FE_WAIT_HEADER_DELAY__SHIFT				0
+#define VIV_FE_WAIT_HEADER_DELAY(x)				(((x) << VIV_FE_WAIT_HEADER_DELAY__SHIFT) & VIV_FE_WAIT_HEADER_DELAY__MASK)
+#define VIV_FE_WAIT_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_WAIT_HEADER_OP__SHIFT				27
+#define VIV_FE_WAIT_HEADER_OP_WAIT				0x38000000
+
+#define VIV_FE_LINK						0x00000000
+
+#define VIV_FE_LINK_HEADER					0x00000000
+#define VIV_FE_LINK_HEADER_PREFETCH__MASK			0x0000ffff
+#define VIV_FE_LINK_HEADER_PREFETCH__SHIFT			0
+#define VIV_FE_LINK_HEADER_PREFETCH(x)				(((x) << VIV_FE_LINK_HEADER_PREFETCH__SHIFT) & VIV_FE_LINK_HEADER_PREFETCH__MASK)
+#define VIV_FE_LINK_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_LINK_HEADER_OP__SHIFT				27
+#define VIV_FE_LINK_HEADER_OP_LINK				0x40000000
+
+#define VIV_FE_LINK_ADDRESS					0x00000004
+
+#define VIV_FE_STALL						0x00000000
+
+#define VIV_FE_STALL_HEADER					0x00000000
+#define VIV_FE_STALL_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_STALL_HEADER_OP__SHIFT				27
+#define VIV_FE_STALL_HEADER_OP_STALL				0x48000000
+
+#define VIV_FE_STALL_TOKEN					0x00000004
+#define VIV_FE_STALL_TOKEN_FROM__MASK				0x0000001f
+#define VIV_FE_STALL_TOKEN_FROM__SHIFT				0
+#define VIV_FE_STALL_TOKEN_FROM(x)				(((x) << VIV_FE_STALL_TOKEN_FROM__SHIFT) & VIV_FE_STALL_TOKEN_FROM__MASK)
+#define VIV_FE_STALL_TOKEN_TO__MASK				0x00001f00
+#define VIV_FE_STALL_TOKEN_TO__SHIFT				8
+#define VIV_FE_STALL_TOKEN_TO(x)				(((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
+
+#define VIV_FE_CALL						0x00000000
+
+#define VIV_FE_CALL_HEADER					0x00000000
+#define VIV_FE_CALL_HEADER_PREFETCH__MASK			0x0000ffff
+#define VIV_FE_CALL_HEADER_PREFETCH__SHIFT			0
+#define VIV_FE_CALL_HEADER_PREFETCH(x)				(((x) << VIV_FE_CALL_HEADER_PREFETCH__SHIFT) & VIV_FE_CALL_HEADER_PREFETCH__MASK)
+#define VIV_FE_CALL_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_CALL_HEADER_OP__SHIFT				27
+#define VIV_FE_CALL_HEADER_OP_CALL				0x50000000
+
+#define VIV_FE_CALL_ADDRESS					0x00000004
+
+#define VIV_FE_CALL_RETURN_PREFETCH				0x00000008
+
+#define VIV_FE_CALL_RETURN_ADDRESS				0x0000000c
+
+#define VIV_FE_RETURN						0x00000000
+
+#define VIV_FE_RETURN_HEADER					0x00000000
+#define VIV_FE_RETURN_HEADER_OP__MASK				0xf8000000
+#define VIV_FE_RETURN_HEADER_OP__SHIFT				27
+#define VIV_FE_RETURN_HEADER_OP_RETURN				0x58000000
+
+#define VIV_FE_CHIP_SELECT					0x00000000
+
+#define VIV_FE_CHIP_SELECT_HEADER				0x00000000
+#define VIV_FE_CHIP_SELECT_HEADER_OP__MASK			0xf8000000
+#define VIV_FE_CHIP_SELECT_HEADER_OP__SHIFT			27
+#define VIV_FE_CHIP_SELECT_HEADER_OP_CHIP_SELECT		0x68000000
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP15			0x00008000
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP14			0x00004000
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP13			0x00002000
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP12			0x00001000
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP11			0x00000800
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP10			0x00000400
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP9			0x00000200
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP8			0x00000100
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP7			0x00000080
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP6			0x00000040
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP5			0x00000020
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP4			0x00000010
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP3			0x00000008
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP2			0x00000004
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP1			0x00000002
+#define VIV_FE_CHIP_SELECT_HEADER_ENABLE_CHIP0			0x00000001
+
+
+#endif /* CMDSTREAM_XML */
diff --git a/src/gallium/drivers/etna/hw/common.xml.h b/src/gallium/drivers/etna/hw/common.xml.h
new file mode 100644
index 0000000000..6746ff7f5b
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/common.xml.h
@@ -0,0 +1,253 @@
+#ifndef COMMON_XML
+#define COMMON_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/state.xml    (  18526 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml   (  18379 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_hi.xml (  22495 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_2d.xml (  51191 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_3d.xml (  54570 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_vg.xml (   5942 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define PIPE_ID_PIPE_3D						0x00000000
+#define PIPE_ID_PIPE_2D						0x00000001
+#define SYNC_RECIPIENT_FE					0x00000001
+#define SYNC_RECIPIENT_RA					0x00000005
+#define SYNC_RECIPIENT_PE					0x00000007
+#define SYNC_RECIPIENT_DE					0x0000000b
+#define SYNC_RECIPIENT_VG					0x0000000f
+#define SYNC_RECIPIENT_TESSELATOR				0x00000010
+#define SYNC_RECIPIENT_VG2					0x00000011
+#define SYNC_RECIPIENT_TESSELATOR2				0x00000012
+#define SYNC_RECIPIENT_VG3					0x00000013
+#define SYNC_RECIPIENT_TESSELATOR3				0x00000014
+#define ENDIAN_MODE_NO_SWAP					0x00000000
+#define ENDIAN_MODE_SWAP_16					0x00000001
+#define ENDIAN_MODE_SWAP_32					0x00000002
+#define chipModel_GC300						0x00000300
+#define chipModel_GC320						0x00000320
+#define chipModel_GC350						0x00000350
+#define chipModel_GC355						0x00000355
+#define chipModel_GC400						0x00000400
+#define chipModel_GC410						0x00000410
+#define chipModel_GC420						0x00000420
+#define chipModel_GC450						0x00000450
+#define chipModel_GC500						0x00000500
+#define chipModel_GC530						0x00000530
+#define chipModel_GC600						0x00000600
+#define chipModel_GC700						0x00000700
+#define chipModel_GC800						0x00000800
+#define chipModel_GC860						0x00000860
+#define chipModel_GC880						0x00000880
+#define chipModel_GC1000					0x00001000
+#define chipModel_GC2000					0x00002000
+#define chipModel_GC2100					0x00002100
+#define chipModel_GC4000					0x00004000
+#define RGBA_BITS_R						0x00000001
+#define RGBA_BITS_G						0x00000002
+#define RGBA_BITS_B						0x00000004
+#define RGBA_BITS_A						0x00000008
+#define chipFeatures_FAST_CLEAR					0x00000001
+#define chipFeatures_SPECIAL_ANTI_ALIASING			0x00000002
+#define chipFeatures_PIPE_3D					0x00000004
+#define chipFeatures_DXT_TEXTURE_COMPRESSION			0x00000008
+#define chipFeatures_DEBUG_MODE					0x00000010
+#define chipFeatures_Z_COMPRESSION				0x00000020
+#define chipFeatures_YUV420_SCALER				0x00000040
+#define chipFeatures_MSAA					0x00000080
+#define chipFeatures_DC						0x00000100
+#define chipFeatures_PIPE_2D					0x00000200
+#define chipFeatures_ETC1_TEXTURE_COMPRESSION			0x00000400
+#define chipFeatures_FAST_SCALER				0x00000800
+#define chipFeatures_HIGH_DYNAMIC_RANGE				0x00001000
+#define chipFeatures_YUV420_TILER				0x00002000
+#define chipFeatures_MODULE_CG					0x00004000
+#define chipFeatures_MIN_AREA					0x00008000
+#define chipFeatures_NO_EARLY_Z					0x00010000
+#define chipFeatures_NO_422_TEXTURE				0x00020000
+#define chipFeatures_BUFFER_INTERLEAVING			0x00040000
+#define chipFeatures_BYTE_WRITE_2D				0x00080000
+#define chipFeatures_NO_SCALER					0x00100000
+#define chipFeatures_YUY2_AVERAGING				0x00200000
+#define chipFeatures_HALF_PE_CACHE				0x00400000
+#define chipFeatures_HALF_TX_CACHE				0x00800000
+#define chipFeatures_YUY2_RENDER_TARGET				0x01000000
+#define chipFeatures_MEM32					0x02000000
+#define chipFeatures_PIPE_VG					0x04000000
+#define chipFeatures_VGTS					0x08000000
+#define chipFeatures_FE20					0x10000000
+#define chipFeatures_BYTE_WRITE_3D				0x20000000
+#define chipFeatures_RS_YUV_TARGET				0x40000000
+#define chipFeatures_32_BIT_INDICES				0x80000000
+#define chipMinorFeatures0_FLIP_Y				0x00000001
+#define chipMinorFeatures0_DUAL_RETURN_BUS			0x00000002
+#define chipMinorFeatures0_ENDIANNESS_CONFIG			0x00000004
+#define chipMinorFeatures0_TEXTURE_8K				0x00000008
+#define chipMinorFeatures0_CORRECT_TEXTURE_CONVERTER		0x00000010
+#define chipMinorFeatures0_SPECIAL_MSAA_LOD			0x00000020
+#define chipMinorFeatures0_FAST_CLEAR_FLUSH			0x00000040
+#define chipMinorFeatures0_2DPE20				0x00000080
+#define chipMinorFeatures0_CORRECT_AUTO_DISABLE			0x00000100
+#define chipMinorFeatures0_RENDERTARGET_8K			0x00000200
+#define chipMinorFeatures0_2BITPERTILE				0x00000400
+#define chipMinorFeatures0_SEPARATE_TILE_STATUS_WHEN_INTERLEAVED	0x00000800
+#define chipMinorFeatures0_SUPER_TILED				0x00001000
+#define chipMinorFeatures0_VG_20				0x00002000
+#define chipMinorFeatures0_TS_EXTENDED_COMMANDS			0x00004000
+#define chipMinorFeatures0_COMPRESSION_FIFO_FIXED		0x00008000
+#define chipMinorFeatures0_HAS_SIGN_FLOOR_CEIL			0x00010000
+#define chipMinorFeatures0_VG_FILTER				0x00020000
+#define chipMinorFeatures0_VG_21				0x00040000
+#define chipMinorFeatures0_SHADER_HAS_W				0x00080000
+#define chipMinorFeatures0_HAS_SQRT_TRIG			0x00100000
+#define chipMinorFeatures0_MORE_MINOR_FEATURES			0x00200000
+#define chipMinorFeatures0_MC20					0x00400000
+#define chipMinorFeatures0_MSAA_SIDEBAND			0x00800000
+#define chipMinorFeatures0_BUG_FIXES0				0x01000000
+#define chipMinorFeatures0_VAA					0x02000000
+#define chipMinorFeatures0_BYPASS_IN_MSAA			0x04000000
+#define chipMinorFeatures0_HZ					0x08000000
+#define chipMinorFeatures0_NEW_TEXTURE				0x10000000
+#define chipMinorFeatures0_2D_A8_TARGET				0x20000000
+#define chipMinorFeatures0_CORRECT_STENCIL			0x40000000
+#define chipMinorFeatures0_ENHANCE_VR				0x80000000
+#define chipMinorFeatures1_RSUV_SWIZZLE				0x00000001
+#define chipMinorFeatures1_V2_COMPRESSION			0x00000002
+#define chipMinorFeatures1_VG_DOUBLE_BUFFER			0x00000004
+#define chipMinorFeatures1_EXTRA_EVENT_STATES			0x00000008
+#define chipMinorFeatures1_NO_STRIPING_NEEDED			0x00000010
+#define chipMinorFeatures1_TEXTURE_STRIDE			0x00000020
+#define chipMinorFeatures1_BUG_FIXES3				0x00000040
+#define chipMinorFeatures1_AUTO_DISABLE				0x00000080
+#define chipMinorFeatures1_AUTO_RESTART_TS			0x00000100
+#define chipMinorFeatures1_DISABLE_PE_GATING			0x00000200
+#define chipMinorFeatures1_L2_WINDOWING				0x00000400
+#define chipMinorFeatures1_HALF_FLOAT				0x00000800
+#define chipMinorFeatures1_PIXEL_DITHER				0x00001000
+#define chipMinorFeatures1_TWO_STENCIL_REFERENCE		0x00002000
+#define chipMinorFeatures1_EXTENDED_PIXEL_FORMAT		0x00004000
+#define chipMinorFeatures1_CORRECT_MIN_MAX_DEPTH		0x00008000
+#define chipMinorFeatures1_2D_DITHER				0x00010000
+#define chipMinorFeatures1_BUG_FIXES5				0x00020000
+#define chipMinorFeatures1_NEW_2D				0x00040000
+#define chipMinorFeatures1_NEW_FP				0x00080000
+#define chipMinorFeatures1_TEXTURE_HALIGN			0x00100000
+#define chipMinorFeatures1_NON_POWER_OF_TWO			0x00200000
+#define chipMinorFeatures1_LINEAR_TEXTURE_SUPPORT		0x00400000
+#define chipMinorFeatures1_HALTI0				0x00800000
+#define chipMinorFeatures1_CORRECT_OVERFLOW_VG			0x01000000
+#define chipMinorFeatures1_NEGATIVE_LOG_FIX			0x02000000
+#define chipMinorFeatures1_RESOLVE_OFFSET			0x04000000
+#define chipMinorFeatures1_OK_TO_GATE_AXI_CLOCK			0x08000000
+#define chipMinorFeatures1_MMU_VERSION				0x10000000
+#define chipMinorFeatures1_WIDE_LINE				0x20000000
+#define chipMinorFeatures1_BUG_FIXES6				0x40000000
+#define chipMinorFeatures1_FC_FLUSH_STALL			0x80000000
+#define chipMinorFeatures2_LINE_LOOP				0x00000001
+#define chipMinorFeatures2_LOGIC_OP				0x00000002
+#define chipMinorFeatures2_UNK2					0x00000004
+#define chipMinorFeatures2_SUPERTILED_TEXTURE			0x00000008
+#define chipMinorFeatures2_UNK4					0x00000010
+#define chipMinorFeatures2_RECT_PRIMITIVE			0x00000020
+#define chipMinorFeatures2_COMPOSITION				0x00000040
+#define chipMinorFeatures2_CORRECT_AUTO_DISABLE_COUNT		0x00000080
+#define chipMinorFeatures2_UNK8					0x00000100
+#define chipMinorFeatures2_UNK9					0x00000200
+#define chipMinorFeatures2_UNK10				0x00000400
+#define chipMinorFeatures2_SAMPLERBASE_16			0x00000800
+#define chipMinorFeatures2_UNK12				0x00001000
+#define chipMinorFeatures2_UNK13				0x00002000
+#define chipMinorFeatures2_UNK14				0x00004000
+#define chipMinorFeatures2_EXTRA_TEXTURE_STATE			0x00008000
+#define chipMinorFeatures2_FULL_DIRECTFB			0x00010000
+#define chipMinorFeatures2_2D_TILING				0x00020000
+#define chipMinorFeatures2_THREAD_WALKER_IN_PS			0x00040000
+#define chipMinorFeatures2_TILE_FILLER				0x00080000
+#define chipMinorFeatures2_UNK20				0x00100000
+#define chipMinorFeatures2_2D_MULTI_SOURCE_BLIT			0x00200000
+#define chipMinorFeatures2_UNK22				0x00400000
+#define chipMinorFeatures2_UNK23				0x00800000
+#define chipMinorFeatures2_UNK24				0x01000000
+#define chipMinorFeatures2_MIXED_STREAMS			0x02000000
+#define chipMinorFeatures2_2D_420_L2CACHE			0x04000000
+#define chipMinorFeatures2_UNK27				0x08000000
+#define chipMinorFeatures2_2D_NO_INDEX8_BRUSH			0x10000000
+#define chipMinorFeatures2_TEXTURE_TILED_READ			0x20000000
+#define chipMinorFeatures2_UNK30				0x40000000
+#define chipMinorFeatures2_UNK31				0x80000000
+#define chipMinorFeatures3_ROTATION_STALL_FIX			0x00000001
+#define chipMinorFeatures3_UNK1					0x00000002
+#define chipMinorFeatures3_2D_MULTI_SOURCE_BLT_EX		0x00000004
+#define chipMinorFeatures3_UNK3					0x00000008
+#define chipMinorFeatures3_UNK4					0x00000010
+#define chipMinorFeatures3_UNK5					0x00000020
+#define chipMinorFeatures3_UNK6					0x00000040
+#define chipMinorFeatures3_UNK7					0x00000080
+#define chipMinorFeatures3_UNK8					0x00000100
+#define chipMinorFeatures3_UNK9					0x00000200
+#define chipMinorFeatures3_BUG_FIXES10				0x00000400
+#define chipMinorFeatures3_UNK11				0x00000800
+#define chipMinorFeatures3_BUG_FIXES11				0x00001000
+#define chipMinorFeatures3_UNK13				0x00002000
+#define chipMinorFeatures3_UNK14				0x00004000
+#define chipMinorFeatures3_UNK15				0x00008000
+#define chipMinorFeatures3_UNK16				0x00010000
+#define chipMinorFeatures3_UNK17				0x00020000
+#define chipMinorFeatures3_UNK18				0x00040000
+#define chipMinorFeatures3_UNK19				0x00080000
+#define chipMinorFeatures3_UNK20				0x00100000
+#define chipMinorFeatures3_UNK21				0x00200000
+#define chipMinorFeatures3_UNK22				0x00400000
+#define chipMinorFeatures3_UNK23				0x00800000
+#define chipMinorFeatures3_UNK24				0x01000000
+#define chipMinorFeatures3_UNK25				0x02000000
+#define chipMinorFeatures3_UNK26				0x04000000
+#define chipMinorFeatures3_UNK27				0x08000000
+#define chipMinorFeatures3_UNK28				0x10000000
+#define chipMinorFeatures3_UNK29				0x20000000
+#define chipMinorFeatures3_UNK30				0x40000000
+#define chipMinorFeatures3_UNK31				0x80000000
+#define chipMinorFeatures4_UNK0					0x00000001
+#define chipMinorFeatures4_UNK1					0x00000002
+#define chipMinorFeatures4_UNK2					0x00000004
+#define chipMinorFeatures4_UNK3					0x00000008
+#define chipMinorFeatures4_UNK4					0x00000010
+#define chipMinorFeatures4_UNK5					0x00000020
+#define chipMinorFeatures4_UNK6					0x00000040
+#define chipMinorFeatures4_UNK7					0x00000080
+#define chipMinorFeatures4_UNK8					0x00000100
+#define chipMinorFeatures4_UNK9					0x00000200
+#define chipMinorFeatures4_UNK10				0x00000400
+#define chipMinorFeatures4_UNK11				0x00000800
+#define chipMinorFeatures4_UNK12				0x00001000
+#define chipMinorFeatures4_UNK13				0x00002000
+#define chipMinorFeatures4_UNK14				0x00004000
+#define chipMinorFeatures4_UNK15				0x00008000
+#define chipMinorFeatures4_UNK16				0x00010000
+#define chipMinorFeatures4_UNK17				0x00020000
+#define chipMinorFeatures4_UNK18				0x00040000
+#define chipMinorFeatures4_UNK19				0x00080000
+#define chipMinorFeatures4_UNK20				0x00100000
+#define chipMinorFeatures4_UNK21				0x00200000
+#define chipMinorFeatures4_UNK22				0x00400000
+#define chipMinorFeatures4_UNK23				0x00800000
+#define chipMinorFeatures4_UNK24				0x01000000
+#define chipMinorFeatures4_UNK25				0x02000000
+#define chipMinorFeatures4_UNK26				0x04000000
+#define chipMinorFeatures4_UNK27				0x08000000
+#define chipMinorFeatures4_UNK28				0x10000000
+#define chipMinorFeatures4_UNK29				0x20000000
+#define chipMinorFeatures4_UNK30				0x40000000
+#define chipMinorFeatures4_UNK31				0x80000000
+
+#endif /* COMMON_XML */
diff --git a/src/gallium/drivers/etna/hw/isa.xml.h b/src/gallium/drivers/etna/hw/isa.xml.h
new file mode 100644
index 0000000000..3f8ad2ea47
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/isa.xml.h
@@ -0,0 +1,206 @@
+#ifndef ISA_XML
+#define ISA_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/isa.xml (  19194 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define INST_OPCODE_NOP						0x00000000
+#define INST_OPCODE_ADD						0x00000001
+#define INST_OPCODE_MAD						0x00000002
+#define INST_OPCODE_MUL						0x00000003
+#define INST_OPCODE_DST						0x00000004
+#define INST_OPCODE_DP3						0x00000005
+#define INST_OPCODE_DP4						0x00000006
+#define INST_OPCODE_DSX						0x00000007
+#define INST_OPCODE_DSY						0x00000008
+#define INST_OPCODE_MOV						0x00000009
+#define INST_OPCODE_MOVAR					0x0000000a
+#define INST_OPCODE_MOVAF					0x0000000b
+#define INST_OPCODE_RCP						0x0000000c
+#define INST_OPCODE_RSQ						0x0000000d
+#define INST_OPCODE_LITP					0x0000000e
+#define INST_OPCODE_SELECT					0x0000000f
+#define INST_OPCODE_SET						0x00000010
+#define INST_OPCODE_EXP						0x00000011
+#define INST_OPCODE_LOG						0x00000012
+#define INST_OPCODE_FRC						0x00000013
+#define INST_OPCODE_CALL					0x00000014
+#define INST_OPCODE_RET						0x00000015
+#define INST_OPCODE_BRANCH					0x00000016
+#define INST_OPCODE_TEXKILL					0x00000017
+#define INST_OPCODE_TEXLD					0x00000018
+#define INST_OPCODE_TEXLDB					0x00000019
+#define INST_OPCODE_TEXLDD					0x0000001a
+#define INST_OPCODE_TEXLDL					0x0000001b
+#define INST_OPCODE_TEXLDPCF					0x0000001c
+#define INST_OPCODE_REP						0x0000001d
+#define INST_OPCODE_ENDREP					0x0000001e
+#define INST_OPCODE_LOOP					0x0000001f
+#define INST_OPCODE_ENDLOOP					0x00000020
+#define INST_OPCODE_SQRT					0x00000021
+#define INST_OPCODE_SIN						0x00000022
+#define INST_OPCODE_COS						0x00000023
+#define INST_OPCODE_FLOOR					0x00000025
+#define INST_OPCODE_CEIL					0x00000026
+#define INST_OPCODE_SIGN					0x00000027
+#define INST_OPCODE_I2F						0x0000002d
+#define INST_OPCODE_CMP						0x00000031
+#define INST_OPCODE_LOAD					0x00000032
+#define INST_OPCODE_STORE					0x00000033
+#define INST_OPCODE_IMULLO0					0x0000003c
+#define INST_OPCODE_IMULHI0					0x00000040
+#define INST_OPCODE_LEADZERO					0x00000058
+#define INST_OPCODE_LSHIFT					0x00000059
+#define INST_OPCODE_RSHIFT					0x0000005a
+#define INST_OPCODE_ROTATE					0x0000005b
+#define INST_OPCODE_OR						0x0000005c
+#define INST_OPCODE_AND						0x0000005d
+#define INST_OPCODE_XOR						0x0000005e
+#define INST_OPCODE_NOT						0x0000005f
+#define INST_CONDITION_TRUE					0x00000000
+#define INST_CONDITION_GT					0x00000001
+#define INST_CONDITION_LT					0x00000002
+#define INST_CONDITION_GE					0x00000003
+#define INST_CONDITION_LE					0x00000004
+#define INST_CONDITION_EQ					0x00000005
+#define INST_CONDITION_NE					0x00000006
+#define INST_CONDITION_AND					0x00000007
+#define INST_CONDITION_OR					0x00000008
+#define INST_CONDITION_XOR					0x00000009
+#define INST_CONDITION_NOT					0x0000000a
+#define INST_CONDITION_NZ					0x0000000b
+#define INST_CONDITION_GEZ					0x0000000c
+#define INST_CONDITION_GZ					0x0000000d
+#define INST_CONDITION_LEZ					0x0000000e
+#define INST_CONDITION_LZ					0x0000000f
+#define INST_RGROUP_TEMP					0x00000000
+#define INST_RGROUP_INTERNAL					0x00000001
+#define INST_RGROUP_UNIFORM_0					0x00000002
+#define INST_RGROUP_UNIFORM_1					0x00000003
+#define INST_AMODE_DIRECT					0x00000000
+#define INST_AMODE_ADD_A_X					0x00000001
+#define INST_AMODE_ADD_A_Y					0x00000002
+#define INST_AMODE_ADD_A_Z					0x00000003
+#define INST_AMODE_ADD_A_W					0x00000004
+#define INST_SWIZ_COMP_X					0x00000000
+#define INST_SWIZ_COMP_Y					0x00000001
+#define INST_SWIZ_COMP_Z					0x00000002
+#define INST_SWIZ_COMP_W					0x00000003
+#define INST_COMPS_X						0x00000001
+#define INST_COMPS_Y						0x00000002
+#define INST_COMPS_Z						0x00000004
+#define INST_COMPS_W						0x00000008
+#define INST_SWIZ_X__MASK					0x00000003
+#define INST_SWIZ_X__SHIFT					0
+#define INST_SWIZ_X(x)						(((x) << INST_SWIZ_X__SHIFT) & INST_SWIZ_X__MASK)
+#define INST_SWIZ_Y__MASK					0x0000000c
+#define INST_SWIZ_Y__SHIFT					2
+#define INST_SWIZ_Y(x)						(((x) << INST_SWIZ_Y__SHIFT) & INST_SWIZ_Y__MASK)
+#define INST_SWIZ_Z__MASK					0x00000030
+#define INST_SWIZ_Z__SHIFT					4
+#define INST_SWIZ_Z(x)						(((x) << INST_SWIZ_Z__SHIFT) & INST_SWIZ_Z__MASK)
+#define INST_SWIZ_W__MASK					0x000000c0
+#define INST_SWIZ_W__SHIFT					6
+#define INST_SWIZ_W(x)						(((x) << INST_SWIZ_W__SHIFT) & INST_SWIZ_W__MASK)
+#define VIV_ISA_WORD_0						0x00000000
+#define VIV_ISA_WORD_0_OPCODE__MASK				0x0000003f
+#define VIV_ISA_WORD_0_OPCODE__SHIFT				0
+#define VIV_ISA_WORD_0_OPCODE(x)				(((x) << VIV_ISA_WORD_0_OPCODE__SHIFT) & VIV_ISA_WORD_0_OPCODE__MASK)
+#define VIV_ISA_WORD_0_COND__MASK				0x000007c0
+#define VIV_ISA_WORD_0_COND__SHIFT				6
+#define VIV_ISA_WORD_0_COND(x)					(((x) << VIV_ISA_WORD_0_COND__SHIFT) & VIV_ISA_WORD_0_COND__MASK)
+#define VIV_ISA_WORD_0_SAT					0x00000800
+#define VIV_ISA_WORD_0_DST_USE					0x00001000
+#define VIV_ISA_WORD_0_DST_AMODE__MASK				0x0000e000
+#define VIV_ISA_WORD_0_DST_AMODE__SHIFT				13
+#define VIV_ISA_WORD_0_DST_AMODE(x)				(((x) << VIV_ISA_WORD_0_DST_AMODE__SHIFT) & VIV_ISA_WORD_0_DST_AMODE__MASK)
+#define VIV_ISA_WORD_0_DST_REG__MASK				0x007f0000
+#define VIV_ISA_WORD_0_DST_REG__SHIFT				16
+#define VIV_ISA_WORD_0_DST_REG(x)				(((x) << VIV_ISA_WORD_0_DST_REG__SHIFT) & VIV_ISA_WORD_0_DST_REG__MASK)
+#define VIV_ISA_WORD_0_DST_COMPS__MASK				0x07800000
+#define VIV_ISA_WORD_0_DST_COMPS__SHIFT				23
+#define VIV_ISA_WORD_0_DST_COMPS(x)				(((x) << VIV_ISA_WORD_0_DST_COMPS__SHIFT) & VIV_ISA_WORD_0_DST_COMPS__MASK)
+#define VIV_ISA_WORD_0_TEX_ID__MASK				0xf8000000
+#define VIV_ISA_WORD_0_TEX_ID__SHIFT				27
+#define VIV_ISA_WORD_0_TEX_ID(x)				(((x) << VIV_ISA_WORD_0_TEX_ID__SHIFT) & VIV_ISA_WORD_0_TEX_ID__MASK)
+
+#define VIV_ISA_WORD_1						0x00000004
+#define VIV_ISA_WORD_1_TEX_AMODE__MASK				0x00000007
+#define VIV_ISA_WORD_1_TEX_AMODE__SHIFT				0
+#define VIV_ISA_WORD_1_TEX_AMODE(x)				(((x) << VIV_ISA_WORD_1_TEX_AMODE__SHIFT) & VIV_ISA_WORD_1_TEX_AMODE__MASK)
+#define VIV_ISA_WORD_1_TEX_SWIZ__MASK				0x000007f8
+#define VIV_ISA_WORD_1_TEX_SWIZ__SHIFT				3
+#define VIV_ISA_WORD_1_TEX_SWIZ(x)				(((x) << VIV_ISA_WORD_1_TEX_SWIZ__SHIFT) & VIV_ISA_WORD_1_TEX_SWIZ__MASK)
+#define VIV_ISA_WORD_1_SRC0_USE					0x00000800
+#define VIV_ISA_WORD_1_SRC0_REG__MASK				0x001ff000
+#define VIV_ISA_WORD_1_SRC0_REG__SHIFT				12
+#define VIV_ISA_WORD_1_SRC0_REG(x)				(((x) << VIV_ISA_WORD_1_SRC0_REG__SHIFT) & VIV_ISA_WORD_1_SRC0_REG__MASK)
+#define VIV_ISA_WORD_1_UNK1_21					0x00200000
+#define VIV_ISA_WORD_1_SRC0_SWIZ__MASK				0x3fc00000
+#define VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT				22
+#define VIV_ISA_WORD_1_SRC0_SWIZ(x)				(((x) << VIV_ISA_WORD_1_SRC0_SWIZ__SHIFT) & VIV_ISA_WORD_1_SRC0_SWIZ__MASK)
+#define VIV_ISA_WORD_1_SRC0_NEG					0x40000000
+#define VIV_ISA_WORD_1_SRC0_ABS					0x80000000
+
+#define VIV_ISA_WORD_2						0x00000008
+#define VIV_ISA_WORD_2_SRC0_AMODE__MASK				0x00000007
+#define VIV_ISA_WORD_2_SRC0_AMODE__SHIFT			0
+#define VIV_ISA_WORD_2_SRC0_AMODE(x)				(((x) << VIV_ISA_WORD_2_SRC0_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC0_AMODE__MASK)
+#define VIV_ISA_WORD_2_SRC0_RGROUP__MASK			0x00000038
+#define VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT			3
+#define VIV_ISA_WORD_2_SRC0_RGROUP(x)				(((x) << VIV_ISA_WORD_2_SRC0_RGROUP__SHIFT) & VIV_ISA_WORD_2_SRC0_RGROUP__MASK)
+#define VIV_ISA_WORD_2_SRC1_USE					0x00000040
+#define VIV_ISA_WORD_2_SRC1_REG__MASK				0x0000ff80
+#define VIV_ISA_WORD_2_SRC1_REG__SHIFT				7
+#define VIV_ISA_WORD_2_SRC1_REG(x)				(((x) << VIV_ISA_WORD_2_SRC1_REG__SHIFT) & VIV_ISA_WORD_2_SRC1_REG__MASK)
+#define VIV_ISA_WORD_2_OPCODE_BIT6				0x00010000
+#define VIV_ISA_WORD_2_SRC1_SWIZ__MASK				0x01fe0000
+#define VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT				17
+#define VIV_ISA_WORD_2_SRC1_SWIZ(x)				(((x) << VIV_ISA_WORD_2_SRC1_SWIZ__SHIFT) & VIV_ISA_WORD_2_SRC1_SWIZ__MASK)
+#define VIV_ISA_WORD_2_SRC1_NEG					0x02000000
+#define VIV_ISA_WORD_2_SRC1_ABS					0x04000000
+#define VIV_ISA_WORD_2_SRC1_AMODE__MASK				0x38000000
+#define VIV_ISA_WORD_2_SRC1_AMODE__SHIFT			27
+#define VIV_ISA_WORD_2_SRC1_AMODE(x)				(((x) << VIV_ISA_WORD_2_SRC1_AMODE__SHIFT) & VIV_ISA_WORD_2_SRC1_AMODE__MASK)
+#define VIV_ISA_WORD_2_UNK2_30__MASK				0xc0000000
+#define VIV_ISA_WORD_2_UNK2_30__SHIFT				30
+#define VIV_ISA_WORD_2_UNK2_30(x)				(((x) << VIV_ISA_WORD_2_UNK2_30__SHIFT) & VIV_ISA_WORD_2_UNK2_30__MASK)
+
+#define VIV_ISA_WORD_3						0x0000000c
+#define VIV_ISA_WORD_3_SRC1_RGROUP__MASK			0x00000007
+#define VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT			0
+#define VIV_ISA_WORD_3_SRC1_RGROUP(x)				(((x) << VIV_ISA_WORD_3_SRC1_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC1_RGROUP__MASK)
+#define VIV_ISA_WORD_3_SRC2_IMM__MASK				0x003fff80
+#define VIV_ISA_WORD_3_SRC2_IMM__SHIFT				7
+#define VIV_ISA_WORD_3_SRC2_IMM(x)				(((x) << VIV_ISA_WORD_3_SRC2_IMM__SHIFT) & VIV_ISA_WORD_3_SRC2_IMM__MASK)
+#define VIV_ISA_WORD_3_SRC2_USE					0x00000008
+#define VIV_ISA_WORD_3_SRC2_REG__MASK				0x00001ff0
+#define VIV_ISA_WORD_3_SRC2_REG__SHIFT				4
+#define VIV_ISA_WORD_3_SRC2_REG(x)				(((x) << VIV_ISA_WORD_3_SRC2_REG__SHIFT) & VIV_ISA_WORD_3_SRC2_REG__MASK)
+#define VIV_ISA_WORD_3_UNK3_13					0x00002000
+#define VIV_ISA_WORD_3_SRC2_SWIZ__MASK				0x003fc000
+#define VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT				14
+#define VIV_ISA_WORD_3_SRC2_SWIZ(x)				(((x) << VIV_ISA_WORD_3_SRC2_SWIZ__SHIFT) & VIV_ISA_WORD_3_SRC2_SWIZ__MASK)
+#define VIV_ISA_WORD_3_SRC2_NEG					0x00400000
+#define VIV_ISA_WORD_3_SRC2_ABS					0x00800000
+#define VIV_ISA_WORD_3_UNK3_24					0x01000000
+#define VIV_ISA_WORD_3_SRC2_AMODE__MASK				0x0e000000
+#define VIV_ISA_WORD_3_SRC2_AMODE__SHIFT			25
+#define VIV_ISA_WORD_3_SRC2_AMODE(x)				(((x) << VIV_ISA_WORD_3_SRC2_AMODE__SHIFT) & VIV_ISA_WORD_3_SRC2_AMODE__MASK)
+#define VIV_ISA_WORD_3_SRC2_RGROUP__MASK			0x70000000
+#define VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT			28
+#define VIV_ISA_WORD_3_SRC2_RGROUP(x)				(((x) << VIV_ISA_WORD_3_SRC2_RGROUP__SHIFT) & VIV_ISA_WORD_3_SRC2_RGROUP__MASK)
+#define VIV_ISA_WORD_3_UNK3_31					0x80000000
+
+
+#endif /* ISA_XML */
diff --git a/src/gallium/drivers/etna/hw/state.xml.h b/src/gallium/drivers/etna/hw/state.xml.h
new file mode 100644
index 0000000000..7ec0457b6c
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/state.xml.h
@@ -0,0 +1,348 @@
+#ifndef STATE_XML
+#define STATE_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/state.xml    (  18526 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml   (  18379 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_hi.xml (  22495 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_2d.xml (  51191 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_3d.xml (  54570 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_vg.xml (   5942 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define VARYING_COMPONENT_USE_UNUSED				0x00000000
+#define VARYING_COMPONENT_USE_USED				0x00000001
+#define VARYING_COMPONENT_USE_POINTCOORD_X			0x00000002
+#define VARYING_COMPONENT_USE_POINTCOORD_Y			0x00000003
+#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK		0x000000ff
+#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT		0
+#define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x)		(((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
+#define VIVS_FE							0x00000000
+
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0)		       (0x00000600 + 0x4*(i0))
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE			0x00000004
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN			0x00000010
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK		0x0000000f
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT		0
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_BYTE			0x00000000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_BYTE	0x00000001
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_SHORT		0x00000002
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_SHORT	0x00000003
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT			0x00000004
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT		0x00000005
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FLOAT		0x00000008
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_HALF_FLOAT		0x00000009
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_FIXED		0x0000000b
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_INT_10_10_10_2	0x0000000c
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE_UNSIGNED_INT_10_10_10_2	0x0000000d
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK		0x00000030
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT		4
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE		0x00000080
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK		0x00000700
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT		8
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK			0x00003000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT		12
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK		0x0000c000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT		14
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF		0x00000000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON		0x00008000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK		0x00ff0000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT		16
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK			0xff000000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT		24
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)
+
+#define VIVS_FE_CMD_STREAM_BASE_ADDR				0x00000640
+
+#define VIVS_FE_INDEX_STREAM_BASE_ADDR				0x00000644
+
+#define VIVS_FE_INDEX_STREAM_CONTROL				0x00000648
+#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK			0x00000003
+#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT		0
+#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR		0x00000000
+#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT	0x00000001
+#define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT		0x00000002
+
+#define VIVS_FE_VERTEX_STREAM_BASE_ADDR				0x0000064c
+
+#define VIVS_FE_VERTEX_STREAM_CONTROL				0x00000650
+
+#define VIVS_FE_COMMAND_ADDRESS					0x00000654
+
+#define VIVS_FE_COMMAND_CONTROL					0x00000658
+#define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK			0x0000ffff
+#define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT			0
+#define VIVS_FE_COMMAND_CONTROL_PREFETCH(x)			(((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)
+#define VIVS_FE_COMMAND_CONTROL_ENABLE				0x00010000
+
+#define VIVS_FE_DMA_STATUS					0x0000065c
+
+#define VIVS_FE_DMA_DEBUG_STATE					0x00000660
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK			0x0000001f
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT		0
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE			0x00000000
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC			0x00000001
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0			0x00000002
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0			0x00000003
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1			0x00000004
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1			0x00000005
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR			0x00000006
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD			0x00000007
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL		0x00000008
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL		0x00000009
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA		0x0000000a
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX		0x0000000b
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW			0x0000000c
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0		0x0000000d
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1		0x0000000e
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0		0x0000000f
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1		0x00000010
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO		0x00000011
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT			0x00000012
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK			0x00000013
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END			0x00000014
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL			0x00000015
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK		0x00000300
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT		8
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE		0x00000000
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START		0x00000100
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ		0x00000200
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END		0x00000300
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK		0x00000c00
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT		10
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE		0x00000000
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID	0x00000400
+#define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID		0x00000800
+#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK		0x00003000
+#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT		12
+#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE		0x00000000
+#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX		0x00001000
+#define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL		0x00002000
+#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK			0x0000c000
+#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT		14
+#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE			0x00000000
+#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR			0x00004000
+#define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC		0x00008000
+#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK		0x00030000
+#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT		16
+#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE		0x00000000
+#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE		0x00010000
+#define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS		0x00020000
+
+#define VIVS_FE_DMA_ADDRESS					0x00000664
+
+#define VIVS_FE_DMA_LOW						0x00000668
+
+#define VIVS_FE_DMA_HIGH					0x0000066c
+
+#define VIVS_FE_AUTO_FLUSH					0x00000670
+
+#define VIVS_FE_UNK00678					0x00000678
+
+#define VIVS_FE_UNK0067C					0x0000067c
+
+#define VIVS_FE_VERTEX_STREAMS(i0)			       (0x00000000 + 0x4*(i0))
+#define VIVS_FE_VERTEX_STREAMS__ESIZE				0x00000004
+#define VIVS_FE_VERTEX_STREAMS__LEN				0x00000008
+
+#define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0)		       (0x00000680 + 0x4*(i0))
+
+#define VIVS_FE_VERTEX_STREAMS_CONTROL(i0)		       (0x000006a0 + 0x4*(i0))
+
+#define VIVS_FE_UNK00700(i0)				       (0x00000700 + 0x4*(i0))
+#define VIVS_FE_UNK00700__ESIZE					0x00000004
+#define VIVS_FE_UNK00700__LEN					0x00000010
+
+#define VIVS_FE_UNK00740(i0)				       (0x00000740 + 0x4*(i0))
+#define VIVS_FE_UNK00740__ESIZE					0x00000004
+#define VIVS_FE_UNK00740__LEN					0x00000010
+
+#define VIVS_FE_UNK00780(i0)				       (0x00000780 + 0x4*(i0))
+#define VIVS_FE_UNK00780__ESIZE					0x00000004
+#define VIVS_FE_UNK00780__LEN					0x00000010
+
+#define VIVS_GL							0x00000000
+
+#define VIVS_GL_PIPE_SELECT					0x00003800
+#define VIVS_GL_PIPE_SELECT_PIPE__MASK				0x00000001
+#define VIVS_GL_PIPE_SELECT_PIPE__SHIFT				0
+#define VIVS_GL_PIPE_SELECT_PIPE(x)				(((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)
+
+#define VIVS_GL_EVENT						0x00003804
+#define VIVS_GL_EVENT_EVENT_ID__MASK				0x0000001f
+#define VIVS_GL_EVENT_EVENT_ID__SHIFT				0
+#define VIVS_GL_EVENT_EVENT_ID(x)				(((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
+#define VIVS_GL_EVENT_FROM_FE					0x00000020
+#define VIVS_GL_EVENT_FROM_PE					0x00000040
+#define VIVS_GL_EVENT_SOURCE__MASK				0x00001f00
+#define VIVS_GL_EVENT_SOURCE__SHIFT				8
+#define VIVS_GL_EVENT_SOURCE(x)					(((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)
+
+#define VIVS_GL_SEMAPHORE_TOKEN					0x00003808
+#define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK			0x0000001f
+#define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT			0
+#define VIVS_GL_SEMAPHORE_TOKEN_FROM(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)
+#define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK			0x00001f00
+#define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT			8
+#define VIVS_GL_SEMAPHORE_TOKEN_TO(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
+
+#define VIVS_GL_FLUSH_CACHE					0x0000380c
+#define VIVS_GL_FLUSH_CACHE_DEPTH				0x00000001
+#define VIVS_GL_FLUSH_CACHE_COLOR				0x00000002
+#define VIVS_GL_FLUSH_CACHE_TEXTURE				0x00000004
+#define VIVS_GL_FLUSH_CACHE_PE2D				0x00000008
+#define VIVS_GL_FLUSH_CACHE_TEXTUREVS				0x00000010
+#define VIVS_GL_FLUSH_CACHE_SHADER_L1				0x00000020
+#define VIVS_GL_FLUSH_CACHE_SHADER_L2				0x00000040
+
+#define VIVS_GL_FLUSH_MMU					0x00003810
+#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU				0x00000001
+#define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU				0x00000002
+
+#define VIVS_GL_VERTEX_ELEMENT_CONFIG				0x00003814
+
+#define VIVS_GL_MULTI_SAMPLE_CONFIG				0x00003818
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK		0x00000003
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT		0
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE		0x00000000
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X		0x00000001
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X		0x00000002
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK		0x00000008
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK		0x000000f0
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT		4
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x)		(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK		0x00000100
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK			0x00007000
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT		12
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK			0x00008000
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK			0x00030000
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT		16
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)
+#define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK			0x00080000
+
+#define VIVS_GL_VARYING_TOTAL_COMPONENTS			0x0000381c
+#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK		0x000000ff
+#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT		0
+#define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x)			(((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
+
+#define VIVS_GL_VARYING_NUM_COMPONENTS				0x00003820
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK		0x00000007
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT		0
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR0(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR0__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK		0x00000070
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT		4
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR1(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR1__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK		0x00000700
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT		8
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR2(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR2__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK		0x00007000
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT		12
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR3(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR3__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK		0x00070000
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT		16
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR4(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR4__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK		0x00700000
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT		20
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR5(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR5__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK		0x07000000
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT		24
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR6(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR6__MASK)
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK		0x70000000
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT		28
+#define VIVS_GL_VARYING_NUM_COMPONENTS_VAR7(x)			(((x) << VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VIVS_GL_VARYING_NUM_COMPONENTS_VAR7__MASK)
+
+#define VIVS_GL_VARYING_COMPONENT_USE(i0)		       (0x00003828 + 0x4*(i0))
+#define VIVS_GL_VARYING_COMPONENT_USE__ESIZE			0x00000004
+#define VIVS_GL_VARYING_COMPONENT_USE__LEN			0x00000002
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK		0x00000003
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT		0
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK		0x0000000c
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT		2
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK		0x00000030
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT		4
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK		0x000000c0
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT		6
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK		0x00000300
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT		8
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK		0x00000c00
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT		10
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK		0x00003000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT		12
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK		0x0000c000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT		14
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK		0x00030000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT		16
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK		0x000c0000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT		18
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK		0x00300000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT		20
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK		0x00c00000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT		22
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK		0x03000000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT		24
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK		0x0c000000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT		26
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK		0x30000000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT		28
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK		0xc0000000
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT		30
+#define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
+
+#define VIVS_GL_UNK03834					0x00003834
+
+#define VIVS_GL_UNK03838					0x00003838
+
+#define VIVS_GL_API_MODE					0x0000384c
+#define VIVS_GL_API_MODE_OPENGL					0x00000000
+#define VIVS_GL_API_MODE_OPENVG					0x00000001
+#define VIVS_GL_API_MODE_OPENCL					0x00000002
+
+#define VIVS_GL_CONTEXT_POINTER					0x00003850
+
+#define VIVS_GL_UNK03A00					0x00003a00
+
+#define VIVS_GL_STALL_TOKEN					0x00003c00
+#define VIVS_GL_STALL_TOKEN_FROM__MASK				0x0000001f
+#define VIVS_GL_STALL_TOKEN_FROM__SHIFT				0
+#define VIVS_GL_STALL_TOKEN_FROM(x)				(((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)
+#define VIVS_GL_STALL_TOKEN_TO__MASK				0x00001f00
+#define VIVS_GL_STALL_TOKEN_TO__SHIFT				8
+#define VIVS_GL_STALL_TOKEN_TO(x)				(((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)
+#define VIVS_GL_STALL_TOKEN_FLIP0				0x40000000
+#define VIVS_GL_STALL_TOKEN_FLIP1				0x80000000
+
+#define VIVS_DUMMY						0x00000000
+
+#define VIVS_DUMMY_DUMMY					0x0003fffc
+
+
+#endif /* STATE_XML */
diff --git a/src/gallium/drivers/etna/hw/state_2d.xml.h b/src/gallium/drivers/etna/hw/state_2d.xml.h
new file mode 100644
index 0000000000..b9b6a5b863
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/state_2d.xml.h
@@ -0,0 +1,1473 @@
+#ifndef STATE_2D_XML
+#define STATE_2D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/state.xml    (  18526 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml   (  18379 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_hi.xml (  22495 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_2d.xml (  51191 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_3d.xml (  54570 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_vg.xml (   5942 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define DE_FORMAT_X4R4G4B4					0x00000000
+#define DE_FORMAT_A4R4G4B4					0x00000001
+#define DE_FORMAT_X1R5G5B5					0x00000002
+#define DE_FORMAT_A1R5G5B5					0x00000003
+#define DE_FORMAT_R5G6B5					0x00000004
+#define DE_FORMAT_X8R8G8B8					0x00000005
+#define DE_FORMAT_A8R8G8B8					0x00000006
+#define DE_FORMAT_YUY2						0x00000007
+#define DE_FORMAT_UYVY						0x00000008
+#define DE_FORMAT_INDEX8					0x00000009
+#define DE_FORMAT_MONOCHROME					0x0000000a
+#define DE_FORMAT_YV12						0x0000000f
+#define DE_FORMAT_A8						0x00000010
+#define DE_FORMAT_NV12						0x00000011
+#define DE_FORMAT_NV16						0x00000012
+#define DE_FORMAT_RG16						0x00000013
+#define DE_SWIZZLE_ARGB						0x00000000
+#define DE_SWIZZLE_RGBA						0x00000001
+#define DE_SWIZZLE_ABGR						0x00000002
+#define DE_SWIZZLE_BGRA						0x00000003
+#define DE_BLENDMODE_ZERO					0x00000000
+#define DE_BLENDMODE_ONE					0x00000001
+#define DE_BLENDMODE_NORMAL					0x00000002
+#define DE_BLENDMODE_INVERSED					0x00000003
+#define DE_BLENDMODE_COLOR					0x00000004
+#define DE_BLENDMODE_COLOR_INVERSED				0x00000005
+#define DE_BLENDMODE_SATURATED_ALPHA				0x00000006
+#define DE_BLENDMODE_SATURATED_DEST_ALPHA			0x00000007
+#define DE_COMPONENT_BLUE					0x00000000
+#define DE_COMPONENT_GREEN					0x00000001
+#define DE_COMPONENT_RED					0x00000002
+#define DE_COMPONENT_ALPHA					0x00000003
+#define DE_ROT_MODE_ROT0					0x00000000
+#define DE_ROT_MODE_FLIP_X					0x00000001
+#define DE_ROT_MODE_FLIP_Y					0x00000002
+#define DE_ROT_MODE_ROT90					0x00000004
+#define DE_ROT_MODE_ROT180					0x00000005
+#define DE_ROT_MODE_ROT270					0x00000006
+#define DE_MIRROR_MODE_NONE					0x00000000
+#define DE_MIRROR_MODE_MIRROR_X					0x00000001
+#define DE_MIRROR_MODE_MIRROR_Y					0x00000002
+#define DE_MIRROR_MODE_MIRROR_XY				0x00000003
+#define DE_COLOR_BLUE__MASK					0x000000ff
+#define DE_COLOR_BLUE__SHIFT					0
+#define DE_COLOR_BLUE(x)					(((x) << DE_COLOR_BLUE__SHIFT) & DE_COLOR_BLUE__MASK)
+#define DE_COLOR_GREEN__MASK					0x0000ff00
+#define DE_COLOR_GREEN__SHIFT					8
+#define DE_COLOR_GREEN(x)					(((x) << DE_COLOR_GREEN__SHIFT) & DE_COLOR_GREEN__MASK)
+#define DE_COLOR_RED__MASK					0x00ff0000
+#define DE_COLOR_RED__SHIFT					16
+#define DE_COLOR_RED(x)						(((x) << DE_COLOR_RED__SHIFT) & DE_COLOR_RED__MASK)
+#define DE_COLOR_ALPHA__MASK					0xff000000
+#define DE_COLOR_ALPHA__SHIFT					24
+#define DE_COLOR_ALPHA(x)					(((x) << DE_COLOR_ALPHA__SHIFT) & DE_COLOR_ALPHA__MASK)
+#define VIVS_DE							0x00000000
+
+#define VIVS_DE_SRC_ADDRESS					0x00001200
+
+#define VIVS_DE_SRC_STRIDE					0x00001204
+#define VIVS_DE_SRC_STRIDE_STRIDE__MASK				0x0003ffff
+#define VIVS_DE_SRC_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_SRC_STRIDE_STRIDE(x)				(((x) << VIVS_DE_SRC_STRIDE_STRIDE__SHIFT) & VIVS_DE_SRC_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_SRC_ROTATION_CONFIG				0x00001208
+#define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__MASK			0x0000ffff
+#define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__SHIFT		0
+#define VIVS_DE_SRC_ROTATION_CONFIG_WIDTH(x)			(((x) << VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_SRC_ROTATION_CONFIG_WIDTH__MASK)
+#define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION__MASK		0x00010000
+#define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION__SHIFT		16
+#define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION_DISABLE		0x00000000
+#define VIVS_DE_SRC_ROTATION_CONFIG_ROTATION_ENABLE		0x00010000
+
+#define VIVS_DE_SRC_CONFIG					0x0000120c
+#define VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT__MASK		0x0000000f
+#define VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT__SHIFT		0
+#define VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT(x)		(((x) << VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT__SHIFT) & VIVS_DE_SRC_CONFIG_PE10_SOURCE_FORMAT__MASK)
+#define VIVS_DE_SRC_CONFIG_TRANSPARENCY__MASK			0x00000030
+#define VIVS_DE_SRC_CONFIG_TRANSPARENCY__SHIFT			4
+#define VIVS_DE_SRC_CONFIG_TRANSPARENCY(x)			(((x) << VIVS_DE_SRC_CONFIG_TRANSPARENCY__SHIFT) & VIVS_DE_SRC_CONFIG_TRANSPARENCY__MASK)
+#define VIVS_DE_SRC_CONFIG_SRC_RELATIVE__MASK			0x00000040
+#define VIVS_DE_SRC_CONFIG_SRC_RELATIVE__SHIFT			6
+#define VIVS_DE_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE		0x00000000
+#define VIVS_DE_SRC_CONFIG_SRC_RELATIVE_RELATIVE		0x00000040
+#define VIVS_DE_SRC_CONFIG_TILED__MASK				0x00000080
+#define VIVS_DE_SRC_CONFIG_TILED__SHIFT				7
+#define VIVS_DE_SRC_CONFIG_TILED_DISABLE			0x00000000
+#define VIVS_DE_SRC_CONFIG_TILED_ENABLE				0x00000080
+#define VIVS_DE_SRC_CONFIG_LOCATION__MASK			0x00000100
+#define VIVS_DE_SRC_CONFIG_LOCATION__SHIFT			8
+#define VIVS_DE_SRC_CONFIG_LOCATION_MEMORY			0x00000000
+#define VIVS_DE_SRC_CONFIG_LOCATION_STREAM			0x00000100
+#define VIVS_DE_SRC_CONFIG_PACK__MASK				0x00003000
+#define VIVS_DE_SRC_CONFIG_PACK__SHIFT				12
+#define VIVS_DE_SRC_CONFIG_PACK_PACKED8				0x00000000
+#define VIVS_DE_SRC_CONFIG_PACK_PACKED16			0x00001000
+#define VIVS_DE_SRC_CONFIG_PACK_PACKED32			0x00002000
+#define VIVS_DE_SRC_CONFIG_PACK_UNPACKED			0x00003000
+#define VIVS_DE_SRC_CONFIG_MONO_TRANSPARENCY__MASK		0x00008000
+#define VIVS_DE_SRC_CONFIG_MONO_TRANSPARENCY__SHIFT		15
+#define VIVS_DE_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND		0x00000000
+#define VIVS_DE_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND		0x00008000
+#define VIVS_DE_SRC_CONFIG_UNK16				0x00010000
+#define VIVS_DE_SRC_CONFIG_SWIZZLE__MASK			0x00300000
+#define VIVS_DE_SRC_CONFIG_SWIZZLE__SHIFT			20
+#define VIVS_DE_SRC_CONFIG_SWIZZLE(x)				(((x) << VIVS_DE_SRC_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_SRC_CONFIG_SWIZZLE__MASK)
+#define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__MASK			0x1f000000
+#define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__SHIFT			24
+#define VIVS_DE_SRC_CONFIG_SOURCE_FORMAT(x)			(((x) << VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_DE_SRC_CONFIG_SOURCE_FORMAT__MASK)
+#define VIVS_DE_SRC_CONFIG_DISABLE420_L2_CACHE			0x20000000
+#define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__MASK			0xc0000000
+#define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__SHIFT		30
+#define VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL(x)			(((x) << VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_SRC_CONFIG_ENDIAN_CONTROL__MASK)
+
+#define VIVS_DE_SRC_ORIGIN					0x00001210
+#define VIVS_DE_SRC_ORIGIN_X__MASK				0x0000ffff
+#define VIVS_DE_SRC_ORIGIN_X__SHIFT				0
+#define VIVS_DE_SRC_ORIGIN_X(x)					(((x) << VIVS_DE_SRC_ORIGIN_X__SHIFT) & VIVS_DE_SRC_ORIGIN_X__MASK)
+#define VIVS_DE_SRC_ORIGIN_Y__MASK				0xffff0000
+#define VIVS_DE_SRC_ORIGIN_Y__SHIFT				16
+#define VIVS_DE_SRC_ORIGIN_Y(x)					(((x) << VIVS_DE_SRC_ORIGIN_Y__SHIFT) & VIVS_DE_SRC_ORIGIN_Y__MASK)
+
+#define VIVS_DE_SRC_SIZE					0x00001214
+#define VIVS_DE_SRC_SIZE_X__MASK				0x0000ffff
+#define VIVS_DE_SRC_SIZE_X__SHIFT				0
+#define VIVS_DE_SRC_SIZE_X(x)					(((x) << VIVS_DE_SRC_SIZE_X__SHIFT) & VIVS_DE_SRC_SIZE_X__MASK)
+#define VIVS_DE_SRC_SIZE_Y__MASK				0xffff0000
+#define VIVS_DE_SRC_SIZE_Y__SHIFT				16
+#define VIVS_DE_SRC_SIZE_Y(x)					(((x) << VIVS_DE_SRC_SIZE_Y__SHIFT) & VIVS_DE_SRC_SIZE_Y__MASK)
+
+#define VIVS_DE_SRC_COLOR_BG					0x00001218
+
+#define VIVS_DE_SRC_COLOR_FG					0x0000121c
+
+#define VIVS_DE_STRETCH_FACTOR_LOW				0x00001220
+#define VIVS_DE_STRETCH_FACTOR_LOW_X__MASK			0x7fffffff
+#define VIVS_DE_STRETCH_FACTOR_LOW_X__SHIFT			0
+#define VIVS_DE_STRETCH_FACTOR_LOW_X(x)				(((x) << VIVS_DE_STRETCH_FACTOR_LOW_X__SHIFT) & VIVS_DE_STRETCH_FACTOR_LOW_X__MASK)
+
+#define VIVS_DE_STRETCH_FACTOR_HIGH				0x00001224
+#define VIVS_DE_STRETCH_FACTOR_HIGH_Y__MASK			0x7fffffff
+#define VIVS_DE_STRETCH_FACTOR_HIGH_Y__SHIFT			0
+#define VIVS_DE_STRETCH_FACTOR_HIGH_Y(x)			(((x) << VIVS_DE_STRETCH_FACTOR_HIGH_Y__SHIFT) & VIVS_DE_STRETCH_FACTOR_HIGH_Y__MASK)
+
+#define VIVS_DE_DEST_ADDRESS					0x00001228
+
+#define VIVS_DE_DEST_STRIDE					0x0000122c
+#define VIVS_DE_DEST_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_DEST_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_DEST_STRIDE_STRIDE(x)				(((x) << VIVS_DE_DEST_STRIDE_STRIDE__SHIFT) & VIVS_DE_DEST_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_DEST_ROTATION_CONFIG				0x00001230
+#define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__MASK		0x0000ffff
+#define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__SHIFT		0
+#define VIVS_DE_DEST_ROTATION_CONFIG_WIDTH(x)			(((x) << VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_DEST_ROTATION_CONFIG_WIDTH__MASK)
+#define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION__MASK		0x00010000
+#define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION__SHIFT		16
+#define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION_DISABLE		0x00000000
+#define VIVS_DE_DEST_ROTATION_CONFIG_ROTATION_ENABLE		0x00010000
+
+#define VIVS_DE_DEST_CONFIG					0x00001234
+#define VIVS_DE_DEST_CONFIG_FORMAT__MASK			0x0000001f
+#define VIVS_DE_DEST_CONFIG_FORMAT__SHIFT			0
+#define VIVS_DE_DEST_CONFIG_FORMAT(x)				(((x) << VIVS_DE_DEST_CONFIG_FORMAT__SHIFT) & VIVS_DE_DEST_CONFIG_FORMAT__MASK)
+#define VIVS_DE_DEST_CONFIG_TILED__MASK				0x00000100
+#define VIVS_DE_DEST_CONFIG_TILED__SHIFT			8
+#define VIVS_DE_DEST_CONFIG_TILED_DISABLE			0x00000000
+#define VIVS_DE_DEST_CONFIG_TILED_ENABLE			0x00000100
+#define VIVS_DE_DEST_CONFIG_COMMAND__MASK			0x0000f000
+#define VIVS_DE_DEST_CONFIG_COMMAND__SHIFT			12
+#define VIVS_DE_DEST_CONFIG_COMMAND_CLEAR			0x00000000
+#define VIVS_DE_DEST_CONFIG_COMMAND_LINE			0x00001000
+#define VIVS_DE_DEST_CONFIG_COMMAND_BIT_BLT			0x00002000
+#define VIVS_DE_DEST_CONFIG_COMMAND_BIT_BLT_REVERSED		0x00003000
+#define VIVS_DE_DEST_CONFIG_COMMAND_STRETCH_BLT			0x00004000
+#define VIVS_DE_DEST_CONFIG_COMMAND_HOR_FILTER_BLT		0x00005000
+#define VIVS_DE_DEST_CONFIG_COMMAND_VER_FILTER_BLT		0x00006000
+#define VIVS_DE_DEST_CONFIG_COMMAND_ONE_PASS_FILTER_BLT		0x00007000
+#define VIVS_DE_DEST_CONFIG_COMMAND_MULTI_SOURCE_BLT		0x00008000
+#define VIVS_DE_DEST_CONFIG_SWIZZLE__MASK			0x00030000
+#define VIVS_DE_DEST_CONFIG_SWIZZLE__SHIFT			16
+#define VIVS_DE_DEST_CONFIG_SWIZZLE(x)				(((x) << VIVS_DE_DEST_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_DEST_CONFIG_SWIZZLE__MASK)
+#define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__MASK		0x00300000
+#define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__SHIFT		20
+#define VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL(x)			(((x) << VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_DEST_CONFIG_ENDIAN_CONTROL__MASK)
+#define VIVS_DE_DEST_CONFIG_GDI_STRE__MASK			0x01000000
+#define VIVS_DE_DEST_CONFIG_GDI_STRE__SHIFT			24
+#define VIVS_DE_DEST_CONFIG_GDI_STRE_DISABLE			0x00000000
+#define VIVS_DE_DEST_CONFIG_GDI_STRE_ENABLE			0x01000000
+#define VIVS_DE_DEST_CONFIG_INTER_TILE_PER_FIX__MASK		0x02000000
+#define VIVS_DE_DEST_CONFIG_INTER_TILE_PER_FIX__SHIFT		25
+#define VIVS_DE_DEST_CONFIG_INTER_TILE_PER_FIX_DISABLED		0x02000000
+#define VIVS_DE_DEST_CONFIG_INTER_TILE_PER_FIX_ENABLED		0x00000000
+#define VIVS_DE_DEST_CONFIG_MINOR_TILED__MASK			0x04000000
+#define VIVS_DE_DEST_CONFIG_MINOR_TILED__SHIFT			26
+#define VIVS_DE_DEST_CONFIG_MINOR_TILED_DISABLE			0x00000000
+#define VIVS_DE_DEST_CONFIG_MINOR_TILED_ENABLE			0x04000000
+
+#define VIVS_DE_PATTERN_ADDRESS					0x00001238
+
+#define VIVS_DE_PATTERN_CONFIG					0x0000123c
+#define VIVS_DE_PATTERN_CONFIG_FORMAT__MASK			0x0000000f
+#define VIVS_DE_PATTERN_CONFIG_FORMAT__SHIFT			0
+#define VIVS_DE_PATTERN_CONFIG_FORMAT(x)			(((x) << VIVS_DE_PATTERN_CONFIG_FORMAT__SHIFT) & VIVS_DE_PATTERN_CONFIG_FORMAT__MASK)
+#define VIVS_DE_PATTERN_CONFIG_TYPE__MASK			0x00000010
+#define VIVS_DE_PATTERN_CONFIG_TYPE__SHIFT			4
+#define VIVS_DE_PATTERN_CONFIG_TYPE_SOLID_COLOR			0x00000000
+#define VIVS_DE_PATTERN_CONFIG_TYPE_PATTERN			0x00000010
+#define VIVS_DE_PATTERN_CONFIG_COLOR_CONVERT__MASK		0x00000020
+#define VIVS_DE_PATTERN_CONFIG_COLOR_CONVERT__SHIFT		5
+#define VIVS_DE_PATTERN_CONFIG_COLOR_CONVERT_DISABLE		0x00000000
+#define VIVS_DE_PATTERN_CONFIG_COLOR_CONVERT_ENABLE		0x00000020
+#define VIVS_DE_PATTERN_CONFIG_INIT_TRIGGER__MASK		0x000000c0
+#define VIVS_DE_PATTERN_CONFIG_INIT_TRIGGER__SHIFT		6
+#define VIVS_DE_PATTERN_CONFIG_INIT_TRIGGER(x)			(((x) << VIVS_DE_PATTERN_CONFIG_INIT_TRIGGER__SHIFT) & VIVS_DE_PATTERN_CONFIG_INIT_TRIGGER__MASK)
+#define VIVS_DE_PATTERN_CONFIG_ORIGIN_X__MASK			0x00070000
+#define VIVS_DE_PATTERN_CONFIG_ORIGIN_X__SHIFT			16
+#define VIVS_DE_PATTERN_CONFIG_ORIGIN_X(x)			(((x) << VIVS_DE_PATTERN_CONFIG_ORIGIN_X__SHIFT) & VIVS_DE_PATTERN_CONFIG_ORIGIN_X__MASK)
+#define VIVS_DE_PATTERN_CONFIG_ORIGIN_Y__MASK			0x00700000
+#define VIVS_DE_PATTERN_CONFIG_ORIGIN_Y__SHIFT			20
+#define VIVS_DE_PATTERN_CONFIG_ORIGIN_Y(x)			(((x) << VIVS_DE_PATTERN_CONFIG_ORIGIN_Y__SHIFT) & VIVS_DE_PATTERN_CONFIG_ORIGIN_Y__MASK)
+
+#define VIVS_DE_PATTERN_LOW					0x00001240
+
+#define VIVS_DE_PATTERN_HIGH					0x00001244
+
+#define VIVS_DE_PATTERN_MASK_LOW				0x00001248
+
+#define VIVS_DE_PATTERN_MASK_HIGH				0x0000124c
+
+#define VIVS_DE_PATTERN_BG_COLOR				0x00001250
+
+#define VIVS_DE_PATTERN_FG_COLOR				0x00001254
+
+#define VIVS_DE_ROP						0x0000125c
+#define VIVS_DE_ROP_ROP_FG__MASK				0x000000ff
+#define VIVS_DE_ROP_ROP_FG__SHIFT				0
+#define VIVS_DE_ROP_ROP_FG(x)					(((x) << VIVS_DE_ROP_ROP_FG__SHIFT) & VIVS_DE_ROP_ROP_FG__MASK)
+#define VIVS_DE_ROP_ROP_BG__MASK				0x0000ff00
+#define VIVS_DE_ROP_ROP_BG__SHIFT				8
+#define VIVS_DE_ROP_ROP_BG(x)					(((x) << VIVS_DE_ROP_ROP_BG__SHIFT) & VIVS_DE_ROP_ROP_BG__MASK)
+#define VIVS_DE_ROP_TYPE__MASK					0x00300000
+#define VIVS_DE_ROP_TYPE__SHIFT					20
+#define VIVS_DE_ROP_TYPE_ROP2_PATTERN				0x00000000
+#define VIVS_DE_ROP_TYPE_ROP2_SOURCE				0x00100000
+#define VIVS_DE_ROP_TYPE_ROP3					0x00200000
+#define VIVS_DE_ROP_TYPE_ROP4					0x00300000
+
+#define VIVS_DE_CLIP_TOP_LEFT					0x00001260
+#define VIVS_DE_CLIP_TOP_LEFT_X__MASK				0x00007fff
+#define VIVS_DE_CLIP_TOP_LEFT_X__SHIFT				0
+#define VIVS_DE_CLIP_TOP_LEFT_X(x)				(((x) << VIVS_DE_CLIP_TOP_LEFT_X__SHIFT) & VIVS_DE_CLIP_TOP_LEFT_X__MASK)
+#define VIVS_DE_CLIP_TOP_LEFT_Y__MASK				0x7fff0000
+#define VIVS_DE_CLIP_TOP_LEFT_Y__SHIFT				16
+#define VIVS_DE_CLIP_TOP_LEFT_Y(x)				(((x) << VIVS_DE_CLIP_TOP_LEFT_Y__SHIFT) & VIVS_DE_CLIP_TOP_LEFT_Y__MASK)
+
+#define VIVS_DE_CLIP_BOTTOM_RIGHT				0x00001264
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_X__MASK			0x00007fff
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_X__SHIFT			0
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_X(x)				(((x) << VIVS_DE_CLIP_BOTTOM_RIGHT_X__SHIFT) & VIVS_DE_CLIP_BOTTOM_RIGHT_X__MASK)
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_Y__MASK			0x7fff0000
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_Y__SHIFT			16
+#define VIVS_DE_CLIP_BOTTOM_RIGHT_Y(x)				(((x) << VIVS_DE_CLIP_BOTTOM_RIGHT_Y__SHIFT) & VIVS_DE_CLIP_BOTTOM_RIGHT_Y__MASK)
+
+#define VIVS_DE_CLEAR_BYTE_MASK					0x00001268
+
+#define VIVS_DE_CONFIG						0x0000126c
+#define VIVS_DE_CONFIG_MIRROR_BLT_ENABLE__MASK			0x00000001
+#define VIVS_DE_CONFIG_MIRROR_BLT_ENABLE__SHIFT			0
+#define VIVS_DE_CONFIG_MIRROR_BLT_ENABLE_OFF			0x00000000
+#define VIVS_DE_CONFIG_MIRROR_BLT_ENABLE_ON			0x00000001
+#define VIVS_DE_CONFIG_MIRROR_BLT_MODE__MASK			0x00000030
+#define VIVS_DE_CONFIG_MIRROR_BLT_MODE__SHIFT			4
+#define VIVS_DE_CONFIG_MIRROR_BLT_MODE_NORMAL			0x00000000
+#define VIVS_DE_CONFIG_MIRROR_BLT_MODE_HMIRROR			0x00000010
+#define VIVS_DE_CONFIG_MIRROR_BLT_MODE_VMIRROR			0x00000020
+#define VIVS_DE_CONFIG_MIRROR_BLT_MODE_FULL_MIRROR		0x00000030
+#define VIVS_DE_CONFIG_SOURCE_SELECT__MASK			0x00070000
+#define VIVS_DE_CONFIG_SOURCE_SELECT__SHIFT			16
+#define VIVS_DE_CONFIG_SOURCE_SELECT(x)				(((x) << VIVS_DE_CONFIG_SOURCE_SELECT__SHIFT) & VIVS_DE_CONFIG_SOURCE_SELECT__MASK)
+#define VIVS_DE_CONFIG_DESTINATION_SELECT__MASK			0x00300000
+#define VIVS_DE_CONFIG_DESTINATION_SELECT__SHIFT		20
+#define VIVS_DE_CONFIG_DESTINATION_SELECT(x)			(((x) << VIVS_DE_CONFIG_DESTINATION_SELECT__SHIFT) & VIVS_DE_CONFIG_DESTINATION_SELECT__MASK)
+
+#define VIVS_DE_CLEAR_PIXEL_VALUE_LOW				0x00001270
+
+#define VIVS_DE_CLEAR_PIXEL_VALUE_HIGH				0x00001274
+
+#define VIVS_DE_SRC_ORIGIN_FRACTION				0x00001278
+#define VIVS_DE_SRC_ORIGIN_FRACTION_X__MASK			0x0000ffff
+#define VIVS_DE_SRC_ORIGIN_FRACTION_X__SHIFT			0
+#define VIVS_DE_SRC_ORIGIN_FRACTION_X(x)			(((x) << VIVS_DE_SRC_ORIGIN_FRACTION_X__SHIFT) & VIVS_DE_SRC_ORIGIN_FRACTION_X__MASK)
+#define VIVS_DE_SRC_ORIGIN_FRACTION_Y__MASK			0xffff0000
+#define VIVS_DE_SRC_ORIGIN_FRACTION_Y__SHIFT			16
+#define VIVS_DE_SRC_ORIGIN_FRACTION_Y(x)			(((x) << VIVS_DE_SRC_ORIGIN_FRACTION_Y__SHIFT) & VIVS_DE_SRC_ORIGIN_FRACTION_Y__MASK)
+
+#define VIVS_DE_ALPHA_CONTROL					0x0000127c
+#define VIVS_DE_ALPHA_CONTROL_ENABLE__MASK			0x00000001
+#define VIVS_DE_ALPHA_CONTROL_ENABLE__SHIFT			0
+#define VIVS_DE_ALPHA_CONTROL_ENABLE_OFF			0x00000000
+#define VIVS_DE_ALPHA_CONTROL_ENABLE_ON				0x00000001
+#define VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__MASK	0x00ff0000
+#define VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__SHIFT	16
+#define VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA(x)		(((x) << VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__SHIFT) & VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__MASK)
+#define VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__MASK	0xff000000
+#define VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__SHIFT	24
+#define VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA(x)		(((x) << VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__SHIFT) & VIVS_DE_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__MASK)
+
+#define VIVS_DE_ALPHA_MODES					0x00001280
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_MODE__MASK		0x00000001
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_MODE__SHIFT		0
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL		0x00000000
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED		0x00000001
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_MODE__MASK		0x00000010
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_MODE__SHIFT		4
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_MODE_NORMAL		0x00000000
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_MODE_INVERSED		0x00000010
+#define VIVS_DE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE__MASK		0x00000300
+#define VIVS_DE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE__SHIFT	8
+#define VIVS_DE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL	0x00000100
+#define VIVS_DE_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED	0x00000200
+#define VIVS_DE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE__MASK		0x00003000
+#define VIVS_DE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE__SHIFT	12
+#define VIVS_DE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL	0x00001000
+#define VIVS_DE_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED	0x00002000
+#define VIVS_DE_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY__MASK	0x00010000
+#define VIVS_DE_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY__SHIFT	16
+#define VIVS_DE_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY_ENABLE	0x00010000
+#define VIVS_DE_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY__MASK	0x00100000
+#define VIVS_DE_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY__SHIFT	20
+#define VIVS_DE_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY_ENABLE	0x00100000
+#define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__MASK		0x07000000
+#define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT		24
+#define VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE(x)		(((x) << VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT) & VIVS_DE_ALPHA_MODES_SRC_BLENDING_MODE__MASK)
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR__MASK		0x08000000
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR__SHIFT		27
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLE		0x00000000
+#define VIVS_DE_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLE		0x08000000
+#define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__MASK		0x70000000
+#define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__SHIFT		28
+#define VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE(x)		(((x) << VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__SHIFT) & VIVS_DE_ALPHA_MODES_DST_BLENDING_MODE__MASK)
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR__MASK		0x80000000
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR__SHIFT		31
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLE		0x00000000
+#define VIVS_DE_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLE		0x80000000
+
+#define VIVS_DE_UPLANE_ADDRESS					0x00001284
+
+#define VIVS_DE_UPLANE_STRIDE					0x00001288
+#define VIVS_DE_UPLANE_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_UPLANE_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_UPLANE_STRIDE_STRIDE(x)				(((x) << VIVS_DE_UPLANE_STRIDE_STRIDE__SHIFT) & VIVS_DE_UPLANE_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_VPLANE_ADDRESS					0x0000128c
+
+#define VIVS_DE_VPLANE_STRIDE					0x00001290
+#define VIVS_DE_VPLANE_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_VPLANE_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_VPLANE_STRIDE_STRIDE(x)				(((x) << VIVS_DE_VPLANE_STRIDE_STRIDE__SHIFT) & VIVS_DE_VPLANE_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_VR_CONFIG					0x00001294
+#define VIVS_DE_VR_CONFIG_START__MASK				0x00000003
+#define VIVS_DE_VR_CONFIG_START__SHIFT				0
+#define VIVS_DE_VR_CONFIG_START_HORIZONTAL_BLIT			0x00000000
+#define VIVS_DE_VR_CONFIG_START_VERTICAL_BLIT			0x00000001
+#define VIVS_DE_VR_CONFIG_START_ONE_PASS_BLIT			0x00000002
+#define VIVS_DE_VR_CONFIG_START_MASK				0x00000008
+
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW				0x00001298
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__MASK			0x0000ffff
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__SHIFT			0
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_LOW_LEFT__MASK)
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__MASK			0xffff0000
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__SHIFT			16
+#define VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_LOW_TOP__MASK)
+
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH				0x0000129c
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__MASK		0x0000ffff
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__SHIFT		0
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_HIGH_RIGHT__MASK)
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__MASK		0xffff0000
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__SHIFT		16
+#define VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM(x)			(((x) << VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__SHIFT) & VIVS_DE_VR_SOURCE_IMAGE_HIGH_BOTTOM__MASK)
+
+#define VIVS_DE_VR_SOURCE_ORIGIN_LOW				0x000012a0
+#define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__MASK			0xffffffff
+#define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__SHIFT			0
+#define VIVS_DE_VR_SOURCE_ORIGIN_LOW_X(x)			(((x) << VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__SHIFT) & VIVS_DE_VR_SOURCE_ORIGIN_LOW_X__MASK)
+
+#define VIVS_DE_VR_SOURCE_ORIGIN_HIGH				0x000012a4
+#define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__MASK			0xffffffff
+#define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__SHIFT			0
+#define VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y(x)			(((x) << VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__SHIFT) & VIVS_DE_VR_SOURCE_ORIGIN_HIGH_Y__MASK)
+
+#define VIVS_DE_VR_TARGET_WINDOW_LOW				0x000012a8
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__MASK			0x0000ffff
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__SHIFT		0
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_LOW_LEFT__MASK)
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__MASK			0xffff0000
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__SHIFT			16
+#define VIVS_DE_VR_TARGET_WINDOW_LOW_TOP(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_LOW_TOP__MASK)
+
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH				0x000012ac
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__MASK		0x0000ffff
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__SHIFT		0
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_HIGH_RIGHT__MASK)
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__MASK		0xffff0000
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__SHIFT		16
+#define VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM(x)			(((x) << VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__SHIFT) & VIVS_DE_VR_TARGET_WINDOW_HIGH_BOTTOM__MASK)
+
+#define VIVS_DE_PE_CONFIG					0x000012b0
+#define VIVS_DE_PE_CONFIG_DESTINATION_FETCH__MASK		0x00000003
+#define VIVS_DE_PE_CONFIG_DESTINATION_FETCH__SHIFT		0
+#define VIVS_DE_PE_CONFIG_DESTINATION_FETCH_DISABLE		0x00000000
+#define VIVS_DE_PE_CONFIG_DESTINATION_FETCH_DEFAULT		0x00000001
+#define VIVS_DE_PE_CONFIG_DESTINATION_FETCH_ALWAYS		0x00000002
+#define VIVS_DE_PE_CONFIG_DESTINATION_FETCH_MASK		0x00000008
+
+#define VIVS_DE_DEST_ROTATION_HEIGHT				0x000012b4
+#define VIVS_DE_DEST_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
+#define VIVS_DE_DEST_ROTATION_HEIGHT_HEIGHT__SHIFT		0
+#define VIVS_DE_DEST_ROTATION_HEIGHT_HEIGHT(x)			(((x) << VIVS_DE_DEST_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_DEST_ROTATION_HEIGHT_HEIGHT__MASK)
+
+#define VIVS_DE_SRC_ROTATION_HEIGHT				0x000012b8
+#define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
+#define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT		0
+#define VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT(x)			(((x) << VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_SRC_ROTATION_HEIGHT_HEIGHT__MASK)
+
+#define VIVS_DE_ROT_ANGLE					0x000012bc
+#define VIVS_DE_ROT_ANGLE_SRC__MASK				0x00000007
+#define VIVS_DE_ROT_ANGLE_SRC__SHIFT				0
+#define VIVS_DE_ROT_ANGLE_SRC(x)				(((x) << VIVS_DE_ROT_ANGLE_SRC__SHIFT) & VIVS_DE_ROT_ANGLE_SRC__MASK)
+#define VIVS_DE_ROT_ANGLE_DST__MASK				0x00000038
+#define VIVS_DE_ROT_ANGLE_DST__SHIFT				3
+#define VIVS_DE_ROT_ANGLE_DST(x)				(((x) << VIVS_DE_ROT_ANGLE_DST__SHIFT) & VIVS_DE_ROT_ANGLE_DST__MASK)
+#define VIVS_DE_ROT_ANGLE_SRC_MASK				0x00000100
+#define VIVS_DE_ROT_ANGLE_DST_MASK				0x00000200
+#define VIVS_DE_ROT_ANGLE_SRC_MIRROR__MASK			0x00003000
+#define VIVS_DE_ROT_ANGLE_SRC_MIRROR__SHIFT			12
+#define VIVS_DE_ROT_ANGLE_SRC_MIRROR(x)				(((x) << VIVS_DE_ROT_ANGLE_SRC_MIRROR__SHIFT) & VIVS_DE_ROT_ANGLE_SRC_MIRROR__MASK)
+#define VIVS_DE_ROT_ANGLE_SRC_MIRROR_MASK			0x00008000
+#define VIVS_DE_ROT_ANGLE_DST_MIRROR__MASK			0x00030000
+#define VIVS_DE_ROT_ANGLE_DST_MIRROR__SHIFT			16
+#define VIVS_DE_ROT_ANGLE_DST_MIRROR(x)				(((x) << VIVS_DE_ROT_ANGLE_DST_MIRROR__SHIFT) & VIVS_DE_ROT_ANGLE_DST_MIRROR__MASK)
+#define VIVS_DE_ROT_ANGLE_DST_MIRROR_MASK			0x00080000
+
+#define VIVS_DE_CLEAR_PIXEL_VALUE32				0x000012c0
+
+#define VIVS_DE_DEST_COLOR_KEY					0x000012c4
+
+#define VIVS_DE_GLOBAL_SRC_COLOR				0x000012c8
+
+#define VIVS_DE_GLOBAL_DEST_COLOR				0x000012cc
+
+#define VIVS_DE_COLOR_MULTIPLY_MODES				0x000012d0
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY__MASK	0x00000001
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY__SHIFT	0
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE	0x00000001
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY__MASK	0x00000010
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY__SHIFT	4
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE	0x00000010
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY__MASK	0x00000300
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY__SHIFT	8
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA	0x00000100
+#define VIVS_DE_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR	0x00000200
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY__MASK	0x00100000
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY__SHIFT	20
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE	0x00100000
+
+#define VIVS_DE_PE_TRANSPARENCY					0x000012d4
+#define VIVS_DE_PE_TRANSPARENCY_SOURCE__MASK			0x00000003
+#define VIVS_DE_PE_TRANSPARENCY_SOURCE__SHIFT			0
+#define VIVS_DE_PE_TRANSPARENCY_SOURCE_OPAQUE			0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_SOURCE_MASK			0x00000001
+#define VIVS_DE_PE_TRANSPARENCY_SOURCE_KEY			0x00000002
+#define VIVS_DE_PE_TRANSPARENCY_PATTERN__MASK			0x00000030
+#define VIVS_DE_PE_TRANSPARENCY_PATTERN__SHIFT			4
+#define VIVS_DE_PE_TRANSPARENCY_PATTERN_OPAQUE			0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_PATTERN_MASK			0x00000010
+#define VIVS_DE_PE_TRANSPARENCY_PATTERN_KEY			0x00000020
+#define VIVS_DE_PE_TRANSPARENCY_DESTINATION__MASK		0x00000300
+#define VIVS_DE_PE_TRANSPARENCY_DESTINATION__SHIFT		8
+#define VIVS_DE_PE_TRANSPARENCY_DESTINATION_OPAQUE		0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_DESTINATION_MASK		0x00000100
+#define VIVS_DE_PE_TRANSPARENCY_DESTINATION_KEY			0x00000200
+#define VIVS_DE_PE_TRANSPARENCY_TRANSPARENCY_MASK		0x00001000
+#define VIVS_DE_PE_TRANSPARENCY_USE_SRC_OVERRIDE__MASK		0x00030000
+#define VIVS_DE_PE_TRANSPARENCY_USE_SRC_OVERRIDE__SHIFT		16
+#define VIVS_DE_PE_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE	0x00010000
+#define VIVS_DE_PE_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE	0x00020000
+#define VIVS_DE_PE_TRANSPARENCY_USE_PAT_OVERRIDE__MASK		0x00300000
+#define VIVS_DE_PE_TRANSPARENCY_USE_PAT_OVERRIDE__SHIFT		20
+#define VIVS_DE_PE_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE	0x00100000
+#define VIVS_DE_PE_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE	0x00200000
+#define VIVS_DE_PE_TRANSPARENCY_USE_DST_OVERRIDE__MASK		0x03000000
+#define VIVS_DE_PE_TRANSPARENCY_USE_DST_OVERRIDE__SHIFT		24
+#define VIVS_DE_PE_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE	0x01000000
+#define VIVS_DE_PE_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE	0x02000000
+#define VIVS_DE_PE_TRANSPARENCY_RESOURCE_OVERRIDE_MASK		0x10000000
+#define VIVS_DE_PE_TRANSPARENCY_DFB_COLOR_KEY__MASK		0x20000000
+#define VIVS_DE_PE_TRANSPARENCY_DFB_COLOR_KEY__SHIFT		29
+#define VIVS_DE_PE_TRANSPARENCY_DFB_COLOR_KEY_DISABLE		0x00000000
+#define VIVS_DE_PE_TRANSPARENCY_DFB_COLOR_KEY_ENABLE		0x20000000
+#define VIVS_DE_PE_TRANSPARENCY_DFB_COLOR_KEY_MASK		0x80000000
+
+#define VIVS_DE_PE_CONTROL					0x000012d8
+#define VIVS_DE_PE_CONTROL_YUV__MASK				0x00000001
+#define VIVS_DE_PE_CONTROL_YUV__SHIFT				0
+#define VIVS_DE_PE_CONTROL_YUV_601				0x00000000
+#define VIVS_DE_PE_CONTROL_YUV_709				0x00000001
+#define VIVS_DE_PE_CONTROL_YUV_MASK				0x00000008
+#define VIVS_DE_PE_CONTROL_UV_SWIZZLE__MASK			0x00000010
+#define VIVS_DE_PE_CONTROL_UV_SWIZZLE__SHIFT			4
+#define VIVS_DE_PE_CONTROL_UV_SWIZZLE_UV			0x00000000
+#define VIVS_DE_PE_CONTROL_UV_SWIZZLE_VU			0x00000010
+#define VIVS_DE_PE_CONTROL_UV_SWIZZLE_MASK			0x00000080
+#define VIVS_DE_PE_CONTROL_YUVRGB__MASK				0x00000100
+#define VIVS_DE_PE_CONTROL_YUVRGB__SHIFT			8
+#define VIVS_DE_PE_CONTROL_YUVRGB_DISABLE			0x00000000
+#define VIVS_DE_PE_CONTROL_YUVRGB_ENABLE			0x00000100
+#define VIVS_DE_PE_CONTROL_YUVRGB_MASK				0x00000800
+
+#define VIVS_DE_SRC_COLOR_KEY_HIGH				0x000012dc
+
+#define VIVS_DE_DEST_COLOR_KEY_HIGH				0x000012e0
+
+#define VIVS_DE_VR_CONFIG_EX					0x000012e4
+#define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH__MASK		0x00000003
+#define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH__SHIFT		0
+#define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_AUTO		0x00000000
+#define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_PIXELS16	0x00000001
+#define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_PIXELS32	0x00000002
+#define VIVS_DE_VR_CONFIG_EX_VERTICAL_LINE_WIDTH_MASK		0x00000008
+#define VIVS_DE_VR_CONFIG_EX_FILTER_TAP__MASK			0x000000f0
+#define VIVS_DE_VR_CONFIG_EX_FILTER_TAP__SHIFT			4
+#define VIVS_DE_VR_CONFIG_EX_FILTER_TAP(x)			(((x) << VIVS_DE_VR_CONFIG_EX_FILTER_TAP__SHIFT) & VIVS_DE_VR_CONFIG_EX_FILTER_TAP__MASK)
+#define VIVS_DE_VR_CONFIG_EX_FILTER_TAP_MASK			0x00000100
+
+#define VIVS_DE_PE_DITHER_LOW					0x000012e8
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__MASK			0x0000000f
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__SHIFT		0
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y0__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__MASK			0x000000f0
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__SHIFT		4
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y0__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__MASK			0x00000f00
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__SHIFT		8
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y0__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__MASK			0x0000f000
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__SHIFT		12
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y0__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__MASK			0x000f0000
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__SHIFT		16
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X0_Y1__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__MASK			0x00f00000
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__SHIFT		20
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X1_Y1__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__MASK			0x0f000000
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__SHIFT		24
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X2_Y1__MASK)
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__MASK			0xf0000000
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__SHIFT		28
+#define VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1(x)			(((x) << VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__SHIFT) & VIVS_DE_PE_DITHER_LOW_PIXEL_X3_Y1__MASK)
+
+#define VIVS_DE_PE_DITHER_HIGH					0x000012ec
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__MASK		0x0000000f
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__SHIFT		0
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y2__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__MASK		0x000000f0
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__SHIFT		4
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y2__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__MASK		0x00000f00
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__SHIFT		8
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y2__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__MASK		0x0000f000
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__SHIFT		12
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y2__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__MASK		0x000f0000
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__SHIFT		16
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X0_Y3__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__MASK		0x00f00000
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__SHIFT		20
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X1_Y3__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__MASK		0x0f000000
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__SHIFT		24
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X2_Y3__MASK)
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__MASK		0xf0000000
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__SHIFT		28
+#define VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3(x)			(((x) << VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__SHIFT) & VIVS_DE_PE_DITHER_HIGH_PIXEL_X3_Y3__MASK)
+
+#define VIVS_DE_BW_CONFIG					0x000012f0
+#define VIVS_DE_BW_CONFIG_BLOCK_CONFIG__MASK			0x00000001
+#define VIVS_DE_BW_CONFIG_BLOCK_CONFIG__SHIFT			0
+#define VIVS_DE_BW_CONFIG_BLOCK_CONFIG_AUTO			0x00000000
+#define VIVS_DE_BW_CONFIG_BLOCK_CONFIG_CUSTOMIZE		0x00000001
+#define VIVS_DE_BW_CONFIG_BLOCK_CONFIG_MASK			0x00000008
+#define VIVS_DE_BW_CONFIG_BLOCK_WALK_DIRECTION__MASK		0x00000010
+#define VIVS_DE_BW_CONFIG_BLOCK_WALK_DIRECTION__SHIFT		4
+#define VIVS_DE_BW_CONFIG_BLOCK_WALK_DIRECTION_RIGHT_BOTTOM	0x00000000
+#define VIVS_DE_BW_CONFIG_BLOCK_WALK_DIRECTION_BOTTOM_RIGHT	0x00000010
+#define VIVS_DE_BW_CONFIG_BLOCK_WALK_DIRECTION_MASK		0x00000080
+#define VIVS_DE_BW_CONFIG_TILE_WALK_DIRECTION__MASK		0x00000100
+#define VIVS_DE_BW_CONFIG_TILE_WALK_DIRECTION__SHIFT		8
+#define VIVS_DE_BW_CONFIG_TILE_WALK_DIRECTION_RIGHT_BOTTOM	0x00000000
+#define VIVS_DE_BW_CONFIG_TILE_WALK_DIRECTION_BOTTOM_RIGHT	0x00000100
+#define VIVS_DE_BW_CONFIG_TILE_WALK_DIRECTION_MASK		0x00000800
+#define VIVS_DE_BW_CONFIG_PIXEL_WALK_DIRECTION__MASK		0x00001000
+#define VIVS_DE_BW_CONFIG_PIXEL_WALK_DIRECTION__SHIFT		12
+#define VIVS_DE_BW_CONFIG_PIXEL_WALK_DIRECTION_RIGHT_BOTTOM	0x00000000
+#define VIVS_DE_BW_CONFIG_PIXEL_WALK_DIRECTION_BOTTOM_RIGHT	0x00001000
+#define VIVS_DE_BW_CONFIG_PIXEL_WALK_DIRECTION_MASK		0x00008000
+
+#define VIVS_DE_BW_BLOCK_SIZE					0x000012f4
+#define VIVS_DE_BW_BLOCK_SIZE_WIDTH__MASK			0x0000ffff
+#define VIVS_DE_BW_BLOCK_SIZE_WIDTH__SHIFT			0
+#define VIVS_DE_BW_BLOCK_SIZE_WIDTH(x)				(((x) << VIVS_DE_BW_BLOCK_SIZE_WIDTH__SHIFT) & VIVS_DE_BW_BLOCK_SIZE_WIDTH__MASK)
+#define VIVS_DE_BW_BLOCK_SIZE_HEIGHT__MASK			0xffff0000
+#define VIVS_DE_BW_BLOCK_SIZE_HEIGHT__SHIFT			16
+#define VIVS_DE_BW_BLOCK_SIZE_HEIGHT(x)				(((x) << VIVS_DE_BW_BLOCK_SIZE_HEIGHT__SHIFT) & VIVS_DE_BW_BLOCK_SIZE_HEIGHT__MASK)
+
+#define VIVS_DE_BW_TILE_SIZE					0x000012f8
+#define VIVS_DE_BW_TILE_SIZE_WIDTH__MASK			0x0000ffff
+#define VIVS_DE_BW_TILE_SIZE_WIDTH__SHIFT			0
+#define VIVS_DE_BW_TILE_SIZE_WIDTH(x)				(((x) << VIVS_DE_BW_TILE_SIZE_WIDTH__SHIFT) & VIVS_DE_BW_TILE_SIZE_WIDTH__MASK)
+#define VIVS_DE_BW_TILE_SIZE_HEIGHT__MASK			0xffff0000
+#define VIVS_DE_BW_TILE_SIZE_HEIGHT__SHIFT			16
+#define VIVS_DE_BW_TILE_SIZE_HEIGHT(x)				(((x) << VIVS_DE_BW_TILE_SIZE_HEIGHT__SHIFT) & VIVS_DE_BW_TILE_SIZE_HEIGHT__MASK)
+
+#define VIVS_DE_BW_BLOCK_MASK					0x000012fc
+#define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__MASK			0x0000ffff
+#define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__SHIFT			0
+#define VIVS_DE_BW_BLOCK_MASK_HORIZONTAL(x)			(((x) << VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__SHIFT) & VIVS_DE_BW_BLOCK_MASK_HORIZONTAL__MASK)
+#define VIVS_DE_BW_BLOCK_MASK_VERTICAL__MASK			0xffff0000
+#define VIVS_DE_BW_BLOCK_MASK_VERTICAL__SHIFT			16
+#define VIVS_DE_BW_BLOCK_MASK_VERTICAL(x)			(((x) << VIVS_DE_BW_BLOCK_MASK_VERTICAL__SHIFT) & VIVS_DE_BW_BLOCK_MASK_VERTICAL__MASK)
+
+#define VIVS_DE_SRC_EX_CONFIG					0x00001300
+#define VIVS_DE_SRC_EX_CONFIG_MULTI_TILED__MASK			0x00000001
+#define VIVS_DE_SRC_EX_CONFIG_MULTI_TILED__SHIFT		0
+#define VIVS_DE_SRC_EX_CONFIG_MULTI_TILED_DISABLE		0x00000000
+#define VIVS_DE_SRC_EX_CONFIG_MULTI_TILED_ENABLE		0x00000001
+#define VIVS_DE_SRC_EX_CONFIG_SUPER_TILED__MASK			0x00000008
+#define VIVS_DE_SRC_EX_CONFIG_SUPER_TILED__SHIFT		3
+#define VIVS_DE_SRC_EX_CONFIG_SUPER_TILED_DISABLE		0x00000000
+#define VIVS_DE_SRC_EX_CONFIG_SUPER_TILED_ENABLE		0x00000008
+#define VIVS_DE_SRC_EX_CONFIG_MINOR_TILED__MASK			0x00000100
+#define VIVS_DE_SRC_EX_CONFIG_MINOR_TILED__SHIFT		8
+#define VIVS_DE_SRC_EX_CONFIG_MINOR_TILED_DISABLE		0x00000000
+#define VIVS_DE_SRC_EX_CONFIG_MINOR_TILED_ENABLE		0x00000100
+
+#define VIVS_DE_SRC_EX_ADDRESS					0x00001304
+
+#define VIVS_DE_DE_MULTI_SOURCE					0x00001308
+#define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__MASK		0x00000007
+#define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__SHIFT		0
+#define VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE(x)			(((x) << VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__SHIFT) & VIVS_DE_DE_MULTI_SOURCE_MAX_SOURCE__MASK)
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK__MASK		0x00000700
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK__SHIFT		8
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL16	0x00000000
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL32	0x00000100
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL64	0x00000200
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL128	0x00000300
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL256	0x00000400
+#define VIVS_DE_DE_MULTI_SOURCE_HORIZONTAL_BLOCK_PIXEL512	0x00000500
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK__MASK		0x00070000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK__SHIFT		16
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE1		0x00000000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE2		0x00010000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE4		0x00020000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE8		0x00030000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE16		0x00040000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE32		0x00050000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE64		0x00060000
+#define VIVS_DE_DE_MULTI_SOURCE_VERTICAL_BLOCK_LINE128		0x00070000
+
+#define VIVS_DE_DEYUV_CONVERSION				0x0000130c
+#define VIVS_DE_DEYUV_CONVERSION_ENABLE__MASK			0x00000003
+#define VIVS_DE_DEYUV_CONVERSION_ENABLE__SHIFT			0
+#define VIVS_DE_DEYUV_CONVERSION_ENABLE_OFF			0x00000000
+#define VIVS_DE_DEYUV_CONVERSION_ENABLE_PLANE1			0x00000001
+#define VIVS_DE_DEYUV_CONVERSION_ENABLE_PLANE2			0x00000002
+#define VIVS_DE_DEYUV_CONVERSION_ENABLE_PLANE3			0x00000003
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__MASK		0x0000000c
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__SHIFT		2
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_COUNT__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__MASK		0x00000030
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__SHIFT		4
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_COUNT__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__MASK		0x000000c0
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__SHIFT		6
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_COUNT__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__MASK		0x00000300
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__SHIFT	8
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_B__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__MASK		0x00000c00
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__SHIFT	10
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_G__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__MASK		0x00003000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__SHIFT	12
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_R__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__MASK		0x0000c000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__SHIFT	14
+#define VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE1_SWIZZLE_A__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__MASK		0x00030000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__SHIFT	16
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_B__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__MASK		0x000c0000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__SHIFT	18
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_G__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__MASK		0x00300000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__SHIFT	20
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_R__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__MASK		0x00c00000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__SHIFT	22
+#define VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE2_SWIZZLE_A__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__MASK		0x03000000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__SHIFT	24
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_B__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__MASK		0x0c000000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__SHIFT	26
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_G__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__MASK		0x30000000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__SHIFT	28
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_R__MASK)
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__MASK		0xc0000000
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__SHIFT	30
+#define VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A(x)		(((x) << VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__SHIFT) & VIVS_DE_DEYUV_CONVERSION_PLANE3_SWIZZLE_A__MASK)
+
+#define VIVS_DE_DE_PLANE2_ADDRESS				0x00001310
+
+#define VIVS_DE_DE_PLANE2_STRIDE				0x00001314
+#define VIVS_DE_DE_PLANE2_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_DE_PLANE2_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_DE_PLANE2_STRIDE_STRIDE(x)			(((x) << VIVS_DE_DE_PLANE2_STRIDE_STRIDE__SHIFT) & VIVS_DE_DE_PLANE2_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_DE_PLANE3_ADDRESS				0x00001318
+
+#define VIVS_DE_DE_PLANE3_STRIDE				0x0000131c
+#define VIVS_DE_DE_PLANE3_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_DE_PLANE3_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_DE_PLANE3_STRIDE_STRIDE(x)			(((x) << VIVS_DE_DE_PLANE3_STRIDE_STRIDE__SHIFT) & VIVS_DE_DE_PLANE3_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_DE_STALL_DE					0x00001320
+#define VIVS_DE_DE_STALL_DE_ENABLE__MASK			0x00000001
+#define VIVS_DE_DE_STALL_DE_ENABLE__SHIFT			0
+#define VIVS_DE_DE_STALL_DE_ENABLE_DISABLE			0x00000000
+#define VIVS_DE_DE_STALL_DE_ENABLE_ENABLE			0x00000001
+
+#define VIVS_DE_FILTER_KERNEL(i0)			       (0x00001800 + 0x4*(i0))
+#define VIVS_DE_FILTER_KERNEL__ESIZE				0x00000004
+#define VIVS_DE_FILTER_KERNEL__LEN				0x00000080
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT0__MASK		0x0000ffff
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT0__SHIFT		0
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT0(x)			(((x) << VIVS_DE_FILTER_KERNEL_COEFFICIENT0__SHIFT) & VIVS_DE_FILTER_KERNEL_COEFFICIENT0__MASK)
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT1__MASK		0xffff0000
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT1__SHIFT		16
+#define VIVS_DE_FILTER_KERNEL_COEFFICIENT1(x)			(((x) << VIVS_DE_FILTER_KERNEL_COEFFICIENT1__SHIFT) & VIVS_DE_FILTER_KERNEL_COEFFICIENT1__MASK)
+
+#define VIVS_DE_INDEX_COLOR_TABLE(i0)			       (0x00001c00 + 0x4*(i0))
+#define VIVS_DE_INDEX_COLOR_TABLE__ESIZE			0x00000004
+#define VIVS_DE_INDEX_COLOR_TABLE__LEN				0x00000100
+
+#define VIVS_DE_HORI_FILTER_KERNEL(i0)			       (0x00002800 + 0x4*(i0))
+#define VIVS_DE_HORI_FILTER_KERNEL__ESIZE			0x00000004
+#define VIVS_DE_HORI_FILTER_KERNEL__LEN				0x00000080
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__MASK		0x0000ffff
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__SHIFT		0
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0(x)		(((x) << VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__SHIFT) & VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT0__MASK)
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__MASK		0xffff0000
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__SHIFT		16
+#define VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1(x)		(((x) << VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__SHIFT) & VIVS_DE_HORI_FILTER_KERNEL_COEFFICIENT1__MASK)
+
+#define VIVS_DE_VERTI_FILTER_KERNEL(i0)			       (0x00002a00 + 0x4*(i0))
+#define VIVS_DE_VERTI_FILTER_KERNEL__ESIZE			0x00000004
+#define VIVS_DE_VERTI_FILTER_KERNEL__LEN			0x00000080
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__MASK		0x0000ffff
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__SHIFT		0
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0(x)		(((x) << VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__SHIFT) & VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT0__MASK)
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__MASK		0xffff0000
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__SHIFT		16
+#define VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1(x)		(((x) << VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__SHIFT) & VIVS_DE_VERTI_FILTER_KERNEL_COEFFICIENT1__MASK)
+
+#define VIVS_DE_INDEX_COLOR_TABLE32(i0)			       (0x00003400 + 0x4*(i0))
+#define VIVS_DE_INDEX_COLOR_TABLE32__ESIZE			0x00000004
+#define VIVS_DE_INDEX_COLOR_TABLE32__LEN			0x00000100
+
+#define VIVS_DE_BLOCK4						0x00000000
+
+#define VIVS_DE_BLOCK4_SRC_ADDRESS(i0)			       (0x00012800 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_ADDRESS__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_ADDRESS__LEN				0x00000004
+
+#define VIVS_DE_BLOCK4_SRC_STRIDE(i0)			       (0x00012810 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_STRIDE__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_STRIDE__LEN				0x00000004
+#define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE(x)			(((x) << VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__SHIFT) & VIVS_DE_BLOCK4_SRC_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG(i0)		       (0x00012820 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG__ESIZE		0x00000004
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG__LEN			0x00000004
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__MASK		0x0000ffff
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__SHIFT		0
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH(x)		(((x) << VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_WIDTH__MASK)
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION__MASK	0x00010000
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION__SHIFT	16
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_SRC_ROTATION_CONFIG_ROTATION_ENABLE	0x00010000
+
+#define VIVS_DE_BLOCK4_SRC_CONFIG(i0)			       (0x00012830 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_CONFIG__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_CONFIG__LEN				0x00000004
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PE10_SOURCE_FORMAT__MASK	0x0000000f
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PE10_SOURCE_FORMAT__SHIFT	0
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PE10_SOURCE_FORMAT(x)		(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_PE10_SOURCE_FORMAT__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_PE10_SOURCE_FORMAT__MASK)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TRANSPARENCY__MASK		0x00000030
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TRANSPARENCY__SHIFT		4
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TRANSPARENCY(x)		(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_TRANSPARENCY__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_TRANSPARENCY__MASK)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SRC_RELATIVE__MASK		0x00000040
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SRC_RELATIVE__SHIFT		6
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE		0x00000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SRC_RELATIVE_RELATIVE		0x00000040
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TILED__MASK			0x00000080
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TILED__SHIFT			7
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TILED_DISABLE			0x00000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_TILED_ENABLE			0x00000080
+#define VIVS_DE_BLOCK4_SRC_CONFIG_LOCATION__MASK		0x00000100
+#define VIVS_DE_BLOCK4_SRC_CONFIG_LOCATION__SHIFT		8
+#define VIVS_DE_BLOCK4_SRC_CONFIG_LOCATION_MEMORY		0x00000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_LOCATION_STREAM		0x00000100
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PACK__MASK			0x00003000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PACK__SHIFT			12
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PACK_PACKED8			0x00000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PACK_PACKED16			0x00001000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PACK_PACKED32			0x00002000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_PACK_UNPACKED			0x00003000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY__MASK	0x00008000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY__SHIFT	15
+#define VIVS_DE_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND	0x00000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND	0x00008000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_UNK16				0x00010000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__MASK			0x00300000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__SHIFT		20
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE(x)			(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_SWIZZLE__MASK)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__MASK		0x1f000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__SHIFT		24
+#define VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT(x)		(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_SOURCE_FORMAT__MASK)
+#define VIVS_DE_BLOCK4_SRC_CONFIG_DISABLE420_L2_CACHE		0x20000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__MASK		0xc0000000
+#define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__SHIFT		30
+#define VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL(x)		(((x) << VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_BLOCK4_SRC_CONFIG_ENDIAN_CONTROL__MASK)
+
+#define VIVS_DE_BLOCK4_SRC_ORIGIN(i0)			       (0x00012840 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_ORIGIN__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_ORIGIN__LEN				0x00000004
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_X__MASK			0x0000ffff
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_X__SHIFT			0
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_X(x)				(((x) << VIVS_DE_BLOCK4_SRC_ORIGIN_X__SHIFT) & VIVS_DE_BLOCK4_SRC_ORIGIN_X__MASK)
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_Y__MASK			0xffff0000
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_Y__SHIFT			16
+#define VIVS_DE_BLOCK4_SRC_ORIGIN_Y(x)				(((x) << VIVS_DE_BLOCK4_SRC_ORIGIN_Y__SHIFT) & VIVS_DE_BLOCK4_SRC_ORIGIN_Y__MASK)
+
+#define VIVS_DE_BLOCK4_SRC_SIZE(i0)			       (0x00012850 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_SIZE__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_SRC_SIZE__LEN				0x00000004
+#define VIVS_DE_BLOCK4_SRC_SIZE_X__MASK				0x0000ffff
+#define VIVS_DE_BLOCK4_SRC_SIZE_X__SHIFT			0
+#define VIVS_DE_BLOCK4_SRC_SIZE_X(x)				(((x) << VIVS_DE_BLOCK4_SRC_SIZE_X__SHIFT) & VIVS_DE_BLOCK4_SRC_SIZE_X__MASK)
+#define VIVS_DE_BLOCK4_SRC_SIZE_Y__MASK				0xffff0000
+#define VIVS_DE_BLOCK4_SRC_SIZE_Y__SHIFT			16
+#define VIVS_DE_BLOCK4_SRC_SIZE_Y(x)				(((x) << VIVS_DE_BLOCK4_SRC_SIZE_Y__SHIFT) & VIVS_DE_BLOCK4_SRC_SIZE_Y__MASK)
+
+#define VIVS_DE_BLOCK4_SRC_COLOR_BG(i0)			       (0x00012860 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_COLOR_BG__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_COLOR_BG__LEN			0x00000004
+
+#define VIVS_DE_BLOCK4_ROP(i0)				       (0x00012870 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_ROP__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_ROP__LEN					0x00000004
+#define VIVS_DE_BLOCK4_ROP_ROP_FG__MASK				0x000000ff
+#define VIVS_DE_BLOCK4_ROP_ROP_FG__SHIFT			0
+#define VIVS_DE_BLOCK4_ROP_ROP_FG(x)				(((x) << VIVS_DE_BLOCK4_ROP_ROP_FG__SHIFT) & VIVS_DE_BLOCK4_ROP_ROP_FG__MASK)
+#define VIVS_DE_BLOCK4_ROP_ROP_BG__MASK				0x0000ff00
+#define VIVS_DE_BLOCK4_ROP_ROP_BG__SHIFT			8
+#define VIVS_DE_BLOCK4_ROP_ROP_BG(x)				(((x) << VIVS_DE_BLOCK4_ROP_ROP_BG__SHIFT) & VIVS_DE_BLOCK4_ROP_ROP_BG__MASK)
+#define VIVS_DE_BLOCK4_ROP_TYPE__MASK				0x00300000
+#define VIVS_DE_BLOCK4_ROP_TYPE__SHIFT				20
+#define VIVS_DE_BLOCK4_ROP_TYPE_ROP2_PATTERN			0x00000000
+#define VIVS_DE_BLOCK4_ROP_TYPE_ROP2_SOURCE			0x00100000
+#define VIVS_DE_BLOCK4_ROP_TYPE_ROP3				0x00200000
+#define VIVS_DE_BLOCK4_ROP_TYPE_ROP4				0x00300000
+
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL(i0)		       (0x00012880 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL__LEN			0x00000004
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_ENABLE__MASK		0x00000001
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_ENABLE__SHIFT		0
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_ENABLE_OFF			0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_ENABLE_ON			0x00000001
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__MASK	0x00ff0000
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__SHIFT	16
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA(x)	(((x) << VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__SHIFT) & VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__MASK)
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__MASK	0xff000000
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__SHIFT	24
+#define VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA(x)	(((x) << VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__SHIFT) & VIVS_DE_BLOCK4_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__MASK)
+
+#define VIVS_DE_BLOCK4_ALPHA_MODES(i0)			       (0x00012890 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_ALPHA_MODES__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_ALPHA_MODES__LEN				0x00000004
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE__MASK		0x00000001
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE__SHIFT	0
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED	0x00000001
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE__MASK		0x00000010
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE__SHIFT	4
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_MODE_INVERSED	0x00000010
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE__MASK	0x00000300
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE__SHIFT	8
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL	0x00000100
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED	0x00000200
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE__MASK	0x00003000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE__SHIFT	12
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL	0x00001000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED	0x00002000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY__MASK	0x00010000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY__SHIFT	16
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY_ENABLE	0x00010000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY__MASK	0x00100000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY__SHIFT	20
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY_ENABLE	0x00100000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__MASK	0x07000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT	24
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK4_ALPHA_MODES_SRC_BLENDING_MODE__MASK)
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR__MASK	0x08000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR__SHIFT	27
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLE	0x08000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__MASK	0x70000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__SHIFT	28
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK4_ALPHA_MODES_DST_BLENDING_MODE__MASK)
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR__MASK	0x80000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR__SHIFT	31
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLE	0x80000000
+
+#define VIVS_DE_BLOCK4_ADDRESS_U(i0)			       (0x000128a0 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_ADDRESS_U__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_ADDRESS_U__LEN				0x00000004
+
+#define VIVS_DE_BLOCK4_STRIDE_U(i0)			       (0x000128b0 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_STRIDE_U__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_STRIDE_U__LEN				0x00000004
+#define VIVS_DE_BLOCK4_STRIDE_U_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_BLOCK4_STRIDE_U_STRIDE__SHIFT			0
+#define VIVS_DE_BLOCK4_STRIDE_U_STRIDE(x)			(((x) << VIVS_DE_BLOCK4_STRIDE_U_STRIDE__SHIFT) & VIVS_DE_BLOCK4_STRIDE_U_STRIDE__MASK)
+
+#define VIVS_DE_BLOCK4_ADDRESS_V(i0)			       (0x000128c0 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_ADDRESS_V__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_ADDRESS_V__LEN				0x00000004
+
+#define VIVS_DE_BLOCK4_STRIDE_V(i0)			       (0x000128d0 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_STRIDE_V__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_STRIDE_V__LEN				0x00000004
+#define VIVS_DE_BLOCK4_STRIDE_V_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_BLOCK4_STRIDE_V_STRIDE__SHIFT			0
+#define VIVS_DE_BLOCK4_STRIDE_V_STRIDE(x)			(((x) << VIVS_DE_BLOCK4_STRIDE_V_STRIDE__SHIFT) & VIVS_DE_BLOCK4_STRIDE_V_STRIDE__MASK)
+
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT(i0)		       (0x000128e0 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT__ESIZE		0x00000004
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT__LEN			0x00000004
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT	0
+#define VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT(x)		(((x) << VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_BLOCK4_SRC_ROTATION_HEIGHT_HEIGHT__MASK)
+
+#define VIVS_DE_BLOCK4_ROT_ANGLE(i0)			       (0x000128f0 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_ROT_ANGLE__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_ROT_ANGLE__LEN				0x00000004
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC__MASK			0x00000007
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC__SHIFT			0
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC(x)				(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_SRC__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_SRC__MASK)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST__MASK			0x00000038
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST__SHIFT			3
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST(x)				(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_DST__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_DST__MASK)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MASK			0x00000100
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MASK			0x00000200
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__MASK		0x00003000
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__SHIFT		12
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR(x)			(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR__MASK)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_SRC_MIRROR_MASK		0x00008000
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__MASK		0x00030000
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__SHIFT		16
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR(x)			(((x) << VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__SHIFT) & VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR__MASK)
+#define VIVS_DE_BLOCK4_ROT_ANGLE_DST_MIRROR_MASK		0x00080000
+
+#define VIVS_DE_BLOCK4_GLOBAL_SRC_COLOR(i0)		       (0x00012900 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_GLOBAL_SRC_COLOR__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_GLOBAL_SRC_COLOR__LEN			0x00000004
+
+#define VIVS_DE_BLOCK4_GLOBAL_DEST_COLOR(i0)		       (0x00012910 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_GLOBAL_DEST_COLOR__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_GLOBAL_DEST_COLOR__LEN			0x00000004
+
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES(i0)		       (0x00012920 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES__ESIZE		0x00000004
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES__LEN		0x00000004
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY__MASK	0x00000001
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY__SHIFT	0
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE	0x00000001
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY__MASK	0x00000010
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY__SHIFT	4
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE	0x00000010
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY__MASK	0x00000300
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY__SHIFT	8
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA	0x00000100
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR	0x00000200
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY__MASK	0x00100000
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY__SHIFT	20
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE	0x00100000
+
+#define VIVS_DE_BLOCK4_TRANSPARENCY(i0)			       (0x00012930 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_TRANSPARENCY__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_TRANSPARENCY__LEN			0x00000004
+#define VIVS_DE_BLOCK4_TRANSPARENCY_SOURCE__MASK		0x00000003
+#define VIVS_DE_BLOCK4_TRANSPARENCY_SOURCE__SHIFT		0
+#define VIVS_DE_BLOCK4_TRANSPARENCY_SOURCE_OPAQUE		0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_SOURCE_MASK			0x00000001
+#define VIVS_DE_BLOCK4_TRANSPARENCY_SOURCE_KEY			0x00000002
+#define VIVS_DE_BLOCK4_TRANSPARENCY_PATTERN__MASK		0x00000030
+#define VIVS_DE_BLOCK4_TRANSPARENCY_PATTERN__SHIFT		4
+#define VIVS_DE_BLOCK4_TRANSPARENCY_PATTERN_OPAQUE		0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_PATTERN_MASK		0x00000010
+#define VIVS_DE_BLOCK4_TRANSPARENCY_PATTERN_KEY			0x00000020
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DESTINATION__MASK		0x00000300
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DESTINATION__SHIFT		8
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DESTINATION_OPAQUE		0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DESTINATION_MASK		0x00000100
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DESTINATION_KEY		0x00000200
+#define VIVS_DE_BLOCK4_TRANSPARENCY_TRANSPARENCY_MASK		0x00001000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE__MASK	0x00030000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE__SHIFT	16
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE	0x00010000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE	0x00020000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE__MASK	0x00300000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE__SHIFT	20
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE	0x00100000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE	0x00200000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE__MASK	0x03000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE__SHIFT	24
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE	0x01000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE	0x02000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_RESOURCE_OVERRIDE_MASK	0x10000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY__MASK		0x20000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY__SHIFT	29
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_ENABLE	0x20000000
+#define VIVS_DE_BLOCK4_TRANSPARENCY_DFB_COLOR_KEY_MASK		0x80000000
+
+#define VIVS_DE_BLOCK4_CONTROL(i0)			       (0x00012940 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_CONTROL__ESIZE				0x00000004
+#define VIVS_DE_BLOCK4_CONTROL__LEN				0x00000004
+#define VIVS_DE_BLOCK4_CONTROL_YUV__MASK			0x00000001
+#define VIVS_DE_BLOCK4_CONTROL_YUV__SHIFT			0
+#define VIVS_DE_BLOCK4_CONTROL_YUV_601				0x00000000
+#define VIVS_DE_BLOCK4_CONTROL_YUV_709				0x00000001
+#define VIVS_DE_BLOCK4_CONTROL_YUV_MASK				0x00000008
+#define VIVS_DE_BLOCK4_CONTROL_UV_SWIZZLE__MASK			0x00000010
+#define VIVS_DE_BLOCK4_CONTROL_UV_SWIZZLE__SHIFT		4
+#define VIVS_DE_BLOCK4_CONTROL_UV_SWIZZLE_UV			0x00000000
+#define VIVS_DE_BLOCK4_CONTROL_UV_SWIZZLE_VU			0x00000010
+#define VIVS_DE_BLOCK4_CONTROL_UV_SWIZZLE_MASK			0x00000080
+#define VIVS_DE_BLOCK4_CONTROL_YUVRGB__MASK			0x00000100
+#define VIVS_DE_BLOCK4_CONTROL_YUVRGB__SHIFT			8
+#define VIVS_DE_BLOCK4_CONTROL_YUVRGB_DISABLE			0x00000000
+#define VIVS_DE_BLOCK4_CONTROL_YUVRGB_ENABLE			0x00000100
+#define VIVS_DE_BLOCK4_CONTROL_YUVRGB_MASK			0x00000800
+
+#define VIVS_DE_BLOCK4_SRC_COLOR_KEY_HIGH(i0)		       (0x00012950 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_COLOR_KEY_HIGH__ESIZE		0x00000004
+#define VIVS_DE_BLOCK4_SRC_COLOR_KEY_HIGH__LEN			0x00000004
+
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG(i0)		       (0x00012960 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG__LEN			0x00000004
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MULTI_TILED__MASK		0x00000001
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MULTI_TILED__SHIFT		0
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MULTI_TILED_ENABLE		0x00000001
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_SUPER_TILED__MASK		0x00000008
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_SUPER_TILED__SHIFT		3
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_SUPER_TILED_ENABLE		0x00000008
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MINOR_TILED__MASK		0x00000100
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MINOR_TILED__SHIFT		8
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_DISABLE	0x00000000
+#define VIVS_DE_BLOCK4_SRC_EX_CONFIG_MINOR_TILED_ENABLE		0x00000100
+
+#define VIVS_DE_BLOCK4_SRC_EX_ADDRESS(i0)		       (0x00012970 + 0x4*(i0))
+#define VIVS_DE_BLOCK4_SRC_EX_ADDRESS__ESIZE			0x00000004
+#define VIVS_DE_BLOCK4_SRC_EX_ADDRESS__LEN			0x00000004
+
+#define VIVS_DE_BLOCK8						0x00000000
+
+#define VIVS_DE_BLOCK8_SRC_ADDRESS(i0)			       (0x00012a00 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_ADDRESS__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_ADDRESS__LEN				0x00000008
+
+#define VIVS_DE_BLOCK8_SRC_STRIDE(i0)			       (0x00012a20 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_STRIDE__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_STRIDE__LEN				0x00000008
+#define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__SHIFT			0
+#define VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE(x)			(((x) << VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__SHIFT) & VIVS_DE_BLOCK8_SRC_STRIDE_STRIDE__MASK)
+
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG(i0)		       (0x00012a40 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG__ESIZE		0x00000004
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG__LEN			0x00000008
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__MASK		0x0000ffff
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__SHIFT		0
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH(x)		(((x) << VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__SHIFT) & VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_WIDTH__MASK)
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION__MASK	0x00010000
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION__SHIFT	16
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_SRC_ROTATION_CONFIG_ROTATION_ENABLE	0x00010000
+
+#define VIVS_DE_BLOCK8_SRC_CONFIG(i0)			       (0x00012a60 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_CONFIG__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_CONFIG__LEN				0x00000008
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PE10_SOURCE_FORMAT__MASK	0x0000000f
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PE10_SOURCE_FORMAT__SHIFT	0
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PE10_SOURCE_FORMAT(x)		(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_PE10_SOURCE_FORMAT__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_PE10_SOURCE_FORMAT__MASK)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TRANSPARENCY__MASK		0x00000030
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TRANSPARENCY__SHIFT		4
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TRANSPARENCY(x)		(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_TRANSPARENCY__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_TRANSPARENCY__MASK)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SRC_RELATIVE__MASK		0x00000040
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SRC_RELATIVE__SHIFT		6
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SRC_RELATIVE_ABSOLUTE		0x00000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SRC_RELATIVE_RELATIVE		0x00000040
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TILED__MASK			0x00000080
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TILED__SHIFT			7
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TILED_DISABLE			0x00000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_TILED_ENABLE			0x00000080
+#define VIVS_DE_BLOCK8_SRC_CONFIG_LOCATION__MASK		0x00000100
+#define VIVS_DE_BLOCK8_SRC_CONFIG_LOCATION__SHIFT		8
+#define VIVS_DE_BLOCK8_SRC_CONFIG_LOCATION_MEMORY		0x00000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_LOCATION_STREAM		0x00000100
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PACK__MASK			0x00003000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PACK__SHIFT			12
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PACK_PACKED8			0x00000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PACK_PACKED16			0x00001000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PACK_PACKED32			0x00002000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_PACK_UNPACKED			0x00003000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY__MASK	0x00008000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY__SHIFT	15
+#define VIVS_DE_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_BACKGROUND	0x00000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_MONO_TRANSPARENCY_FOREGROUND	0x00008000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_UNK16				0x00010000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__MASK			0x00300000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__SHIFT		20
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE(x)			(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_SWIZZLE__MASK)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__MASK		0x1f000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__SHIFT		24
+#define VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT(x)		(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_SOURCE_FORMAT__MASK)
+#define VIVS_DE_BLOCK8_SRC_CONFIG_DISABLE420_L2_CACHE		0x20000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__MASK		0xc0000000
+#define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__SHIFT		30
+#define VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL(x)		(((x) << VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__SHIFT) & VIVS_DE_BLOCK8_SRC_CONFIG_ENDIAN_CONTROL__MASK)
+
+#define VIVS_DE_BLOCK8_SRC_ORIGIN(i0)			       (0x00012a80 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_ORIGIN__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_ORIGIN__LEN				0x00000008
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_X__MASK			0x0000ffff
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_X__SHIFT			0
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_X(x)				(((x) << VIVS_DE_BLOCK8_SRC_ORIGIN_X__SHIFT) & VIVS_DE_BLOCK8_SRC_ORIGIN_X__MASK)
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_Y__MASK			0xffff0000
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_Y__SHIFT			16
+#define VIVS_DE_BLOCK8_SRC_ORIGIN_Y(x)				(((x) << VIVS_DE_BLOCK8_SRC_ORIGIN_Y__SHIFT) & VIVS_DE_BLOCK8_SRC_ORIGIN_Y__MASK)
+
+#define VIVS_DE_BLOCK8_SRC_SIZE(i0)			       (0x00012aa0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_SIZE__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_SRC_SIZE__LEN				0x00000008
+#define VIVS_DE_BLOCK8_SRC_SIZE_X__MASK				0x0000ffff
+#define VIVS_DE_BLOCK8_SRC_SIZE_X__SHIFT			0
+#define VIVS_DE_BLOCK8_SRC_SIZE_X(x)				(((x) << VIVS_DE_BLOCK8_SRC_SIZE_X__SHIFT) & VIVS_DE_BLOCK8_SRC_SIZE_X__MASK)
+#define VIVS_DE_BLOCK8_SRC_SIZE_Y__MASK				0xffff0000
+#define VIVS_DE_BLOCK8_SRC_SIZE_Y__SHIFT			16
+#define VIVS_DE_BLOCK8_SRC_SIZE_Y(x)				(((x) << VIVS_DE_BLOCK8_SRC_SIZE_Y__SHIFT) & VIVS_DE_BLOCK8_SRC_SIZE_Y__MASK)
+
+#define VIVS_DE_BLOCK8_SRC_COLOR_BG(i0)			       (0x00012ac0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_COLOR_BG__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_COLOR_BG__LEN			0x00000008
+
+#define VIVS_DE_BLOCK8_ROP(i0)				       (0x00012ae0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_ROP__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_ROP__LEN					0x00000008
+#define VIVS_DE_BLOCK8_ROP_ROP_FG__MASK				0x000000ff
+#define VIVS_DE_BLOCK8_ROP_ROP_FG__SHIFT			0
+#define VIVS_DE_BLOCK8_ROP_ROP_FG(x)				(((x) << VIVS_DE_BLOCK8_ROP_ROP_FG__SHIFT) & VIVS_DE_BLOCK8_ROP_ROP_FG__MASK)
+#define VIVS_DE_BLOCK8_ROP_ROP_BG__MASK				0x0000ff00
+#define VIVS_DE_BLOCK8_ROP_ROP_BG__SHIFT			8
+#define VIVS_DE_BLOCK8_ROP_ROP_BG(x)				(((x) << VIVS_DE_BLOCK8_ROP_ROP_BG__SHIFT) & VIVS_DE_BLOCK8_ROP_ROP_BG__MASK)
+#define VIVS_DE_BLOCK8_ROP_TYPE__MASK				0x00300000
+#define VIVS_DE_BLOCK8_ROP_TYPE__SHIFT				20
+#define VIVS_DE_BLOCK8_ROP_TYPE_ROP2_PATTERN			0x00000000
+#define VIVS_DE_BLOCK8_ROP_TYPE_ROP2_SOURCE			0x00100000
+#define VIVS_DE_BLOCK8_ROP_TYPE_ROP3				0x00200000
+#define VIVS_DE_BLOCK8_ROP_TYPE_ROP4				0x00300000
+
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL(i0)		       (0x00012b00 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL__LEN			0x00000008
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_ENABLE__MASK		0x00000001
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_ENABLE__SHIFT		0
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_ENABLE_OFF			0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_ENABLE_ON			0x00000001
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__MASK	0x00ff0000
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__SHIFT	16
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA(x)	(((x) << VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__SHIFT) & VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_SRC_ALPHA__MASK)
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__MASK	0xff000000
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__SHIFT	24
+#define VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA(x)	(((x) << VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__SHIFT) & VIVS_DE_BLOCK8_ALPHA_CONTROL_PE10_GLOBAL_DST_ALPHA__MASK)
+
+#define VIVS_DE_BLOCK8_ALPHA_MODES(i0)			       (0x00012b20 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_ALPHA_MODES__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_ALPHA_MODES__LEN				0x00000008
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE__MASK		0x00000001
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE__SHIFT	0
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_MODE_INVERSED	0x00000001
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE__MASK		0x00000010
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE__SHIFT	4
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_MODE_INVERSED	0x00000010
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE__MASK	0x00000300
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE__SHIFT	8
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_GLOBAL	0x00000100
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_SRC_ALPHA_MODE_SCALED	0x00000200
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE__MASK	0x00003000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE__SHIFT	12
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_NORMAL	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_GLOBAL	0x00001000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_GLOBAL_DST_ALPHA_MODE_SCALED	0x00002000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY__MASK	0x00010000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY__SHIFT	16
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_SRC_COLOR_MULTIPLY_ENABLE	0x00010000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY__MASK	0x00100000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY__SHIFT	20
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_PE10_DST_COLOR_MULTIPLY_ENABLE	0x00100000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__MASK	0x07000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT	24
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK8_ALPHA_MODES_SRC_BLENDING_MODE__MASK)
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR__MASK	0x08000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR__SHIFT	27
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_SRC_ALPHA_FACTOR_ENABLE	0x08000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__MASK	0x70000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__SHIFT	28
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE(x)		(((x) << VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__SHIFT) & VIVS_DE_BLOCK8_ALPHA_MODES_DST_BLENDING_MODE__MASK)
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR__MASK	0x80000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR__SHIFT	31
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_ALPHA_MODES_DST_ALPHA_FACTOR_ENABLE	0x80000000
+
+#define VIVS_DE_BLOCK8_ADDRESS_U(i0)			       (0x00012b40 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_ADDRESS_U__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_ADDRESS_U__LEN				0x00000008
+
+#define VIVS_DE_BLOCK8_STRIDE_U(i0)			       (0x00012b60 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_STRIDE_U__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_STRIDE_U__LEN				0x00000008
+#define VIVS_DE_BLOCK8_STRIDE_U_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_BLOCK8_STRIDE_U_STRIDE__SHIFT			0
+#define VIVS_DE_BLOCK8_STRIDE_U_STRIDE(x)			(((x) << VIVS_DE_BLOCK8_STRIDE_U_STRIDE__SHIFT) & VIVS_DE_BLOCK8_STRIDE_U_STRIDE__MASK)
+
+#define VIVS_DE_BLOCK8_ADDRESS_V(i0)			       (0x00012b80 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_ADDRESS_V__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_ADDRESS_V__LEN				0x00000008
+
+#define VIVS_DE_BLOCK8_STRIDE_V(i0)			       (0x00012ba0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_STRIDE_V__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_STRIDE_V__LEN				0x00000008
+#define VIVS_DE_BLOCK8_STRIDE_V_STRIDE__MASK			0x0003ffff
+#define VIVS_DE_BLOCK8_STRIDE_V_STRIDE__SHIFT			0
+#define VIVS_DE_BLOCK8_STRIDE_V_STRIDE(x)			(((x) << VIVS_DE_BLOCK8_STRIDE_V_STRIDE__SHIFT) & VIVS_DE_BLOCK8_STRIDE_V_STRIDE__MASK)
+
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT(i0)		       (0x00012bc0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT__ESIZE		0x00000004
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT__LEN			0x00000008
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__MASK		0x0000ffff
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT	0
+#define VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT(x)		(((x) << VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__SHIFT) & VIVS_DE_BLOCK8_SRC_ROTATION_HEIGHT_HEIGHT__MASK)
+
+#define VIVS_DE_BLOCK8_ROT_ANGLE(i0)			       (0x00012be0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_ROT_ANGLE__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_ROT_ANGLE__LEN				0x00000008
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC__MASK			0x00000007
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC__SHIFT			0
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC(x)				(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_SRC__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_SRC__MASK)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST__MASK			0x00000038
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST__SHIFT			3
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST(x)				(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_DST__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_DST__MASK)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MASK			0x00000100
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MASK			0x00000200
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__MASK		0x00003000
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__SHIFT		12
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR(x)			(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR__MASK)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_SRC_MIRROR_MASK		0x00008000
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__MASK		0x00030000
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__SHIFT		16
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR(x)			(((x) << VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__SHIFT) & VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR__MASK)
+#define VIVS_DE_BLOCK8_ROT_ANGLE_DST_MIRROR_MASK		0x00080000
+
+#define VIVS_DE_BLOCK8_GLOBAL_SRC_COLOR(i0)		       (0x00012c00 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_GLOBAL_SRC_COLOR__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_GLOBAL_SRC_COLOR__LEN			0x00000008
+
+#define VIVS_DE_BLOCK8_GLOBAL_DEST_COLOR(i0)		       (0x00012c20 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_GLOBAL_DEST_COLOR__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_GLOBAL_DEST_COLOR__LEN			0x00000008
+
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES(i0)		       (0x00012c40 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES__ESIZE		0x00000004
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES__LEN		0x00000008
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY__MASK	0x00000001
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY__SHIFT	0
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_PREMULTIPLY_ENABLE	0x00000001
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY__MASK	0x00000010
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY__SHIFT	4
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_PREMULTIPLY_ENABLE	0x00000010
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY__MASK	0x00000300
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY__SHIFT	8
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_ALPHA	0x00000100
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_SRC_GLOBAL_PREMULTIPLY_COLOR	0x00000200
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY__MASK	0x00100000
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY__SHIFT	20
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_COLOR_MULTIPLY_MODES_DST_DEMULTIPLY_ENABLE	0x00100000
+
+#define VIVS_DE_BLOCK8_TRANSPARENCY(i0)			       (0x00012c60 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_TRANSPARENCY__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_TRANSPARENCY__LEN			0x00000008
+#define VIVS_DE_BLOCK8_TRANSPARENCY_SOURCE__MASK		0x00000003
+#define VIVS_DE_BLOCK8_TRANSPARENCY_SOURCE__SHIFT		0
+#define VIVS_DE_BLOCK8_TRANSPARENCY_SOURCE_OPAQUE		0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_SOURCE_MASK			0x00000001
+#define VIVS_DE_BLOCK8_TRANSPARENCY_SOURCE_KEY			0x00000002
+#define VIVS_DE_BLOCK8_TRANSPARENCY_PATTERN__MASK		0x00000030
+#define VIVS_DE_BLOCK8_TRANSPARENCY_PATTERN__SHIFT		4
+#define VIVS_DE_BLOCK8_TRANSPARENCY_PATTERN_OPAQUE		0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_PATTERN_MASK		0x00000010
+#define VIVS_DE_BLOCK8_TRANSPARENCY_PATTERN_KEY			0x00000020
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DESTINATION__MASK		0x00000300
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DESTINATION__SHIFT		8
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DESTINATION_OPAQUE		0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DESTINATION_MASK		0x00000100
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DESTINATION_KEY		0x00000200
+#define VIVS_DE_BLOCK8_TRANSPARENCY_TRANSPARENCY_MASK		0x00001000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE__MASK	0x00030000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE__SHIFT	16
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_USE_ENABLE	0x00010000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_SRC_OVERRIDE_USE_DISABLE	0x00020000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE__MASK	0x00300000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE__SHIFT	20
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_USE_ENABLE	0x00100000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_PAT_OVERRIDE_USE_DISABLE	0x00200000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE__MASK	0x03000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE__SHIFT	24
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_DEFAULT	0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_USE_ENABLE	0x01000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_USE_DST_OVERRIDE_USE_DISABLE	0x02000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_RESOURCE_OVERRIDE_MASK	0x10000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY__MASK		0x20000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY__SHIFT	29
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_ENABLE	0x20000000
+#define VIVS_DE_BLOCK8_TRANSPARENCY_DFB_COLOR_KEY_MASK		0x80000000
+
+#define VIVS_DE_BLOCK8_CONTROL(i0)			       (0x00012c80 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_CONTROL__ESIZE				0x00000004
+#define VIVS_DE_BLOCK8_CONTROL__LEN				0x00000008
+#define VIVS_DE_BLOCK8_CONTROL_YUV__MASK			0x00000001
+#define VIVS_DE_BLOCK8_CONTROL_YUV__SHIFT			0
+#define VIVS_DE_BLOCK8_CONTROL_YUV_601				0x00000000
+#define VIVS_DE_BLOCK8_CONTROL_YUV_709				0x00000001
+#define VIVS_DE_BLOCK8_CONTROL_YUV_MASK				0x00000008
+#define VIVS_DE_BLOCK8_CONTROL_UV_SWIZZLE__MASK			0x00000010
+#define VIVS_DE_BLOCK8_CONTROL_UV_SWIZZLE__SHIFT		4
+#define VIVS_DE_BLOCK8_CONTROL_UV_SWIZZLE_UV			0x00000000
+#define VIVS_DE_BLOCK8_CONTROL_UV_SWIZZLE_VU			0x00000010
+#define VIVS_DE_BLOCK8_CONTROL_UV_SWIZZLE_MASK			0x00000080
+#define VIVS_DE_BLOCK8_CONTROL_YUVRGB__MASK			0x00000100
+#define VIVS_DE_BLOCK8_CONTROL_YUVRGB__SHIFT			8
+#define VIVS_DE_BLOCK8_CONTROL_YUVRGB_DISABLE			0x00000000
+#define VIVS_DE_BLOCK8_CONTROL_YUVRGB_ENABLE			0x00000100
+#define VIVS_DE_BLOCK8_CONTROL_YUVRGB_MASK			0x00000800
+
+#define VIVS_DE_BLOCK8_SRC_COLOR_KEY_HIGH(i0)		       (0x00012ca0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_COLOR_KEY_HIGH__ESIZE		0x00000004
+#define VIVS_DE_BLOCK8_SRC_COLOR_KEY_HIGH__LEN			0x00000008
+
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG(i0)		       (0x00012cc0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG__LEN			0x00000008
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MULTI_TILED__MASK		0x00000001
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MULTI_TILED__SHIFT		0
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MULTI_TILED_ENABLE		0x00000001
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_SUPER_TILED__MASK		0x00000008
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_SUPER_TILED__SHIFT		3
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_SUPER_TILED_ENABLE		0x00000008
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MINOR_TILED__MASK		0x00000100
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MINOR_TILED__SHIFT		8
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_DISABLE	0x00000000
+#define VIVS_DE_BLOCK8_SRC_EX_CONFIG_MINOR_TILED_ENABLE		0x00000100
+
+#define VIVS_DE_BLOCK8_SRC_EX_ADDRESS(i0)		       (0x00012ce0 + 0x4*(i0))
+#define VIVS_DE_BLOCK8_SRC_EX_ADDRESS__ESIZE			0x00000004
+#define VIVS_DE_BLOCK8_SRC_EX_ADDRESS__LEN			0x00000008
+
+
+#endif /* STATE_2D_XML */
diff --git a/src/gallium/drivers/etna/hw/state_3d.xml.h b/src/gallium/drivers/etna/hw/state_3d.xml.h
new file mode 100644
index 0000000000..1fd10c644b
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/state_3d.xml.h
@@ -0,0 +1,1147 @@
+#ifndef STATE_3D_XML
+#define STATE_3D_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/state.xml    (  18526 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml   (  18379 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_hi.xml (  22495 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_2d.xml (  51191 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_3d.xml (  54570 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_vg.xml (   5942 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define COMPARE_FUNC_NEVER					0x00000000
+#define COMPARE_FUNC_LESS					0x00000001
+#define COMPARE_FUNC_EQUAL					0x00000002
+#define COMPARE_FUNC_LEQUAL					0x00000003
+#define COMPARE_FUNC_GREATER					0x00000004
+#define COMPARE_FUNC_NOTEQUAL					0x00000005
+#define COMPARE_FUNC_GEQUAL					0x00000006
+#define COMPARE_FUNC_ALWAYS					0x00000007
+#define STENCIL_OP_KEEP						0x00000000
+#define STENCIL_OP_ZERO						0x00000001
+#define STENCIL_OP_REPLACE					0x00000002
+#define STENCIL_OP_INCR						0x00000003
+#define STENCIL_OP_DECR						0x00000004
+#define STENCIL_OP_INVERT					0x00000005
+#define STENCIL_OP_INCR_WRAP					0x00000006
+#define STENCIL_OP_DECR_WRAP					0x00000007
+#define BLEND_EQ_ADD						0x00000000
+#define BLEND_EQ_SUBTRACT					0x00000001
+#define BLEND_EQ_REVERSE_SUBTRACT				0x00000002
+#define BLEND_EQ_MIN						0x00000003
+#define BLEND_EQ_MAX						0x00000004
+#define BLEND_FUNC_ZERO						0x00000000
+#define BLEND_FUNC_ONE						0x00000001
+#define BLEND_FUNC_SRC_COLOR					0x00000002
+#define BLEND_FUNC_ONE_MINUS_SRC_COLOR				0x00000003
+#define BLEND_FUNC_SRC_ALPHA					0x00000004
+#define BLEND_FUNC_ONE_MINUS_SRC_ALPHA				0x00000005
+#define BLEND_FUNC_DST_ALPHA					0x00000006
+#define BLEND_FUNC_ONE_MINUS_DST_ALPHA				0x00000007
+#define BLEND_FUNC_DST_COLOR					0x00000008
+#define BLEND_FUNC_ONE_MINUS_DST_COLOR				0x00000009
+#define BLEND_FUNC_SRC_ALPHA_SATURATE				0x0000000a
+#define BLEND_FUNC_CONSTANT_ALPHA				0x0000000b
+#define BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA			0x0000000c
+#define BLEND_FUNC_CONSTANT_COLOR				0x0000000d
+#define BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR			0x0000000e
+#define RS_FORMAT_X4R4G4B4					0x00000000
+#define RS_FORMAT_A4R4G4B4					0x00000001
+#define RS_FORMAT_X1R5G5B5					0x00000002
+#define RS_FORMAT_A1R5G5B5					0x00000003
+#define RS_FORMAT_R5G6B5					0x00000004
+#define RS_FORMAT_X8R8G8B8					0x00000005
+#define RS_FORMAT_A8R8G8B8					0x00000006
+#define RS_FORMAT_YUY2						0x00000007
+#define TEXTURE_FORMAT_NONE					0x00000000
+#define TEXTURE_FORMAT_A8					0x00000001
+#define TEXTURE_FORMAT_L8					0x00000002
+#define TEXTURE_FORMAT_I8					0x00000003
+#define TEXTURE_FORMAT_A8L8					0x00000004
+#define TEXTURE_FORMAT_A4R4G4B4					0x00000005
+#define TEXTURE_FORMAT_X4R4G4B4					0x00000006
+#define TEXTURE_FORMAT_A8R8G8B8					0x00000007
+#define TEXTURE_FORMAT_X8R8G8B8					0x00000008
+#define TEXTURE_FORMAT_A8B8G8R8					0x00000009
+#define TEXTURE_FORMAT_X8B8G8R8					0x0000000a
+#define TEXTURE_FORMAT_R5G6B5					0x0000000b
+#define TEXTURE_FORMAT_A1R5G5B5					0x0000000c
+#define TEXTURE_FORMAT_X1R5G5B5					0x0000000d
+#define TEXTURE_FORMAT_YUY2					0x0000000e
+#define TEXTURE_FORMAT_UYVY					0x0000000f
+#define TEXTURE_FORMAT_D16					0x00000010
+#define TEXTURE_FORMAT_D24S8					0x00000011
+#define TEXTURE_FORMAT_DXT1					0x00000013
+#define TEXTURE_FORMAT_DXT2_DXT3				0x00000014
+#define TEXTURE_FORMAT_DXT4_DXT5				0x00000015
+#define TEXTURE_FORMAT_ETC1					0x0000001e
+#define TEXTURE_FORMAT_EXT_NONE					0x00000000
+#define TEXTURE_FORMAT_EXT_A16F					0x00000007
+#define TEXTURE_FORMAT_EXT_A16L16F				0x00000008
+#define TEXTURE_FORMAT_EXT_A16B16G16R16F			0x00000009
+#define TEXTURE_FORMAT_EXT_A32F					0x0000000a
+#define TEXTURE_FORMAT_EXT_A32L32F				0x0000000b
+#define TEXTURE_FORMAT_EXT_A2B10G10R10				0x0000000c
+#define TEXTURE_FILTER_NONE					0x00000000
+#define TEXTURE_FILTER_NEAREST					0x00000001
+#define TEXTURE_FILTER_LINEAR					0x00000002
+#define TEXTURE_FILTER_ANISOTROPIC				0x00000003
+#define TEXTURE_TYPE_NONE					0x00000000
+#define TEXTURE_TYPE_2D						0x00000002
+#define TEXTURE_TYPE_CUBE_MAP					0x00000005
+#define TEXTURE_WRAPMODE_REPEAT					0x00000000
+#define TEXTURE_WRAPMODE_MIRRORED_REPEAT			0x00000001
+#define TEXTURE_WRAPMODE_CLAMP_TO_EDGE				0x00000002
+#define TEXTURE_FACE_POS_X					0x00000000
+#define TEXTURE_FACE_NEG_X					0x00000001
+#define TEXTURE_FACE_POS_Y					0x00000002
+#define TEXTURE_FACE_NEG_Y					0x00000003
+#define TEXTURE_FACE_POS_Z					0x00000004
+#define TEXTURE_FACE_NEG_Z					0x00000005
+#define TEXTURE_SWIZZLE_RED					0x00000000
+#define TEXTURE_SWIZZLE_GREEN					0x00000001
+#define TEXTURE_SWIZZLE_BLUE					0x00000002
+#define TEXTURE_SWIZZLE_ALPHA					0x00000003
+#define TEXTURE_SWIZZLE_ZERO					0x00000004
+#define TEXTURE_SWIZZLE_ONE					0x00000005
+#define TEXTURE_HALIGN_FOUR					0x00000000
+#define TEXTURE_HALIGN_SIXTEEN					0x00000001
+#define TEXTURE_HALIGN_SUPER_TILED				0x00000002
+#define TEXTURE_HALIGN_SPLIT_TILED				0x00000003
+#define TEXTURE_HALIGN_SPLIT_SUPER_TILED			0x00000004
+#define LOGIC_OP_CLEAR						0x00000000
+#define LOGIC_OP_NOR						0x00000001
+#define LOGIC_OP_AND_INVERTED					0x00000002
+#define LOGIC_OP_COPY_INVERTED					0x00000003
+#define LOGIC_OP_AND_REVERSE					0x00000004
+#define LOGIC_OP_INVERT						0x00000005
+#define LOGIC_OP_XOR						0x00000006
+#define LOGIC_OP_NAND						0x00000007
+#define LOGIC_OP_AND						0x00000008
+#define LOGIC_OP_EQUIV						0x00000009
+#define LOGIC_OP_NOOP						0x0000000a
+#define LOGIC_OP_OR_INVERTED					0x0000000b
+#define LOGIC_OP_COPY						0x0000000c
+#define LOGIC_OP_OR_REVERSE					0x0000000d
+#define LOGIC_OP_OR						0x0000000e
+#define LOGIC_OP_SET						0x0000000f
+#define VIVS_VS							0x00000000
+
+#define VIVS_VS_END_PC						0x00000800
+
+#define VIVS_VS_OUTPUT_COUNT					0x00000804
+
+#define VIVS_VS_INPUT_COUNT					0x00000808
+#define VIVS_VS_INPUT_COUNT_COUNT__MASK				0x0000000f
+#define VIVS_VS_INPUT_COUNT_COUNT__SHIFT			0
+#define VIVS_VS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK)
+#define VIVS_VS_INPUT_COUNT_UNK8__MASK				0x00001f00
+#define VIVS_VS_INPUT_COUNT_UNK8__SHIFT				8
+#define VIVS_VS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK)
+
+#define VIVS_VS_TEMP_REGISTER_CONTROL				0x0000080c
+#define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
+#define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
+#define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
+
+#define VIVS_VS_OUTPUT(i0)				       (0x00000810 + 0x4*(i0))
+#define VIVS_VS_OUTPUT__ESIZE					0x00000004
+#define VIVS_VS_OUTPUT__LEN					0x00000004
+#define VIVS_VS_OUTPUT_O0__MASK					0x000000ff
+#define VIVS_VS_OUTPUT_O0__SHIFT				0
+#define VIVS_VS_OUTPUT_O0(x)					(((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK)
+#define VIVS_VS_OUTPUT_O1__MASK					0x0000ff00
+#define VIVS_VS_OUTPUT_O1__SHIFT				8
+#define VIVS_VS_OUTPUT_O1(x)					(((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK)
+#define VIVS_VS_OUTPUT_O2__MASK					0x00ff0000
+#define VIVS_VS_OUTPUT_O2__SHIFT				16
+#define VIVS_VS_OUTPUT_O2(x)					(((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK)
+#define VIVS_VS_OUTPUT_O3__MASK					0xff000000
+#define VIVS_VS_OUTPUT_O3__SHIFT				24
+#define VIVS_VS_OUTPUT_O3(x)					(((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK)
+
+#define VIVS_VS_INPUT(i0)				       (0x00000820 + 0x4*(i0))
+#define VIVS_VS_INPUT__ESIZE					0x00000004
+#define VIVS_VS_INPUT__LEN					0x00000004
+#define VIVS_VS_INPUT_I0__MASK					0x000000ff
+#define VIVS_VS_INPUT_I0__SHIFT					0
+#define VIVS_VS_INPUT_I0(x)					(((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK)
+#define VIVS_VS_INPUT_I1__MASK					0x0000ff00
+#define VIVS_VS_INPUT_I1__SHIFT					8
+#define VIVS_VS_INPUT_I1(x)					(((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK)
+#define VIVS_VS_INPUT_I2__MASK					0x00ff0000
+#define VIVS_VS_INPUT_I2__SHIFT					16
+#define VIVS_VS_INPUT_I2(x)					(((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK)
+#define VIVS_VS_INPUT_I3__MASK					0xff000000
+#define VIVS_VS_INPUT_I3__SHIFT					24
+#define VIVS_VS_INPUT_I3(x)					(((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK)
+
+#define VIVS_VS_LOAD_BALANCING					0x00000830
+#define VIVS_VS_LOAD_BALANCING_A__MASK				0x000000ff
+#define VIVS_VS_LOAD_BALANCING_A__SHIFT				0
+#define VIVS_VS_LOAD_BALANCING_A(x)				(((x) << VIVS_VS_LOAD_BALANCING_A__SHIFT) & VIVS_VS_LOAD_BALANCING_A__MASK)
+#define VIVS_VS_LOAD_BALANCING_B__MASK				0x0000ff00
+#define VIVS_VS_LOAD_BALANCING_B__SHIFT				8
+#define VIVS_VS_LOAD_BALANCING_B(x)				(((x) << VIVS_VS_LOAD_BALANCING_B__SHIFT) & VIVS_VS_LOAD_BALANCING_B__MASK)
+#define VIVS_VS_LOAD_BALANCING_C__MASK				0x00ff0000
+#define VIVS_VS_LOAD_BALANCING_C__SHIFT				16
+#define VIVS_VS_LOAD_BALANCING_C(x)				(((x) << VIVS_VS_LOAD_BALANCING_C__SHIFT) & VIVS_VS_LOAD_BALANCING_C__MASK)
+#define VIVS_VS_LOAD_BALANCING_D__MASK				0xff000000
+#define VIVS_VS_LOAD_BALANCING_D__SHIFT				24
+#define VIVS_VS_LOAD_BALANCING_D(x)				(((x) << VIVS_VS_LOAD_BALANCING_D__SHIFT) & VIVS_VS_LOAD_BALANCING_D__MASK)
+
+#define VIVS_VS_PERF_COUNTER					0x00000834
+
+#define VIVS_VS_START_PC					0x00000838
+
+#define VIVS_VS_UNK00850					0x00000850
+
+#define VIVS_VS_UNK00854					0x00000854
+
+#define VIVS_VS_UNK00858					0x00000858
+
+#define VIVS_VS_RANGE						0x0000085c
+#define VIVS_VS_RANGE_LOW__MASK					0x0000ffff
+#define VIVS_VS_RANGE_LOW__SHIFT				0
+#define VIVS_VS_RANGE_LOW(x)					(((x) << VIVS_VS_RANGE_LOW__SHIFT) & VIVS_VS_RANGE_LOW__MASK)
+#define VIVS_VS_RANGE_HIGH__MASK				0xffff0000
+#define VIVS_VS_RANGE_HIGH__SHIFT				16
+#define VIVS_VS_RANGE_HIGH(x)					(((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK)
+
+#define VIVS_VS_NEW_UNK00860					0x00000860
+
+#define VIVS_VS_INST_MEM(i0)				       (0x00004000 + 0x4*(i0))
+#define VIVS_VS_INST_MEM__ESIZE					0x00000004
+#define VIVS_VS_INST_MEM__LEN					0x00000400
+
+#define VIVS_VS_UNIFORMS(i0)				       (0x00005000 + 0x4*(i0))
+#define VIVS_VS_UNIFORMS__ESIZE					0x00000004
+#define VIVS_VS_UNIFORMS__LEN					0x00000400
+
+#define VIVS_CL							0x00000000
+
+#define VIVS_CL_CONFIG						0x00000900
+#define VIVS_CL_CONFIG_DIMENSIONS__MASK				0x00000003
+#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT			0
+#define VIVS_CL_CONFIG_DIMENSIONS(x)				(((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK)
+#define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK			0x00000070
+#define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT			4
+#define VIVS_CL_CONFIG_TRAVERSE_ORDER(x)			(((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK)
+#define VIVS_CL_CONFIG_ENABLE_SWATH_X				0x00000100
+#define VIVS_CL_CONFIG_ENABLE_SWATH_Y				0x00000200
+#define VIVS_CL_CONFIG_ENABLE_SWATH_Z				0x00000400
+#define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK			0x0000f000
+#define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT			12
+#define VIVS_CL_CONFIG_SWATH_SIZE_X(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK)
+#define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK			0x000f0000
+#define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT			16
+#define VIVS_CL_CONFIG_SWATH_SIZE_Y(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK)
+#define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK			0x00f00000
+#define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT			20
+#define VIVS_CL_CONFIG_SWATH_SIZE_Z(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK)
+#define VIVS_CL_CONFIG_VALUE_ORDER__MASK			0x07000000
+#define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT			24
+#define VIVS_CL_CONFIG_VALUE_ORDER(x)				(((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK)
+
+#define VIVS_CL_GLOBAL_X					0x00000904
+#define VIVS_CL_GLOBAL_X_SIZE__MASK				0x0000ffff
+#define VIVS_CL_GLOBAL_X_SIZE__SHIFT				0
+#define VIVS_CL_GLOBAL_X_SIZE(x)				(((x) << VIVS_CL_GLOBAL_X_SIZE__SHIFT) & VIVS_CL_GLOBAL_X_SIZE__MASK)
+#define VIVS_CL_GLOBAL_X_OFFSET__MASK				0xffff0000
+#define VIVS_CL_GLOBAL_X_OFFSET__SHIFT				16
+#define VIVS_CL_GLOBAL_X_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_X_OFFSET__SHIFT) & VIVS_CL_GLOBAL_X_OFFSET__MASK)
+
+#define VIVS_CL_GLOBAL_Y					0x00000908
+#define VIVS_CL_GLOBAL_Y_SIZE__MASK				0x0000ffff
+#define VIVS_CL_GLOBAL_Y_SIZE__SHIFT				0
+#define VIVS_CL_GLOBAL_Y_SIZE(x)				(((x) << VIVS_CL_GLOBAL_Y_SIZE__SHIFT) & VIVS_CL_GLOBAL_Y_SIZE__MASK)
+#define VIVS_CL_GLOBAL_Y_OFFSET__MASK				0xffff0000
+#define VIVS_CL_GLOBAL_Y_OFFSET__SHIFT				16
+#define VIVS_CL_GLOBAL_Y_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_Y_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Y_OFFSET__MASK)
+
+#define VIVS_CL_GLOBAL_Z					0x0000090c
+#define VIVS_CL_GLOBAL_Z_SIZE__MASK				0x0000ffff
+#define VIVS_CL_GLOBAL_Z_SIZE__SHIFT				0
+#define VIVS_CL_GLOBAL_Z_SIZE(x)				(((x) << VIVS_CL_GLOBAL_Z_SIZE__SHIFT) & VIVS_CL_GLOBAL_Z_SIZE__MASK)
+#define VIVS_CL_GLOBAL_Z_OFFSET__MASK				0xffff0000
+#define VIVS_CL_GLOBAL_Z_OFFSET__SHIFT				16
+#define VIVS_CL_GLOBAL_Z_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_Z_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Z_OFFSET__MASK)
+
+#define VIVS_CL_WORKGROUP_X					0x00000910
+#define VIVS_CL_WORKGROUP_X_SIZE__MASK				0x000003ff
+#define VIVS_CL_WORKGROUP_X_SIZE__SHIFT				0
+#define VIVS_CL_WORKGROUP_X_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_X_SIZE__SHIFT) & VIVS_CL_WORKGROUP_X_SIZE__MASK)
+#define VIVS_CL_WORKGROUP_X_COUNT__MASK				0xffff0000
+#define VIVS_CL_WORKGROUP_X_COUNT__SHIFT			16
+#define VIVS_CL_WORKGROUP_X_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_X_COUNT__SHIFT) & VIVS_CL_WORKGROUP_X_COUNT__MASK)
+
+#define VIVS_CL_WORKGROUP_Y					0x00000914
+#define VIVS_CL_WORKGROUP_Y_SIZE__MASK				0x000003ff
+#define VIVS_CL_WORKGROUP_Y_SIZE__SHIFT				0
+#define VIVS_CL_WORKGROUP_Y_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_Y_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Y_SIZE__MASK)
+#define VIVS_CL_WORKGROUP_Y_COUNT__MASK				0xffff0000
+#define VIVS_CL_WORKGROUP_Y_COUNT__SHIFT			16
+#define VIVS_CL_WORKGROUP_Y_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_Y_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Y_COUNT__MASK)
+
+#define VIVS_CL_WORKGROUP_Z					0x00000918
+#define VIVS_CL_WORKGROUP_Z_SIZE__MASK				0x000003ff
+#define VIVS_CL_WORKGROUP_Z_SIZE__SHIFT				0
+#define VIVS_CL_WORKGROUP_Z_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_Z_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Z_SIZE__MASK)
+#define VIVS_CL_WORKGROUP_Z_COUNT__MASK				0xffff0000
+#define VIVS_CL_WORKGROUP_Z_COUNT__SHIFT			16
+#define VIVS_CL_WORKGROUP_Z_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_Z_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Z_COUNT__MASK)
+
+#define VIVS_CL_THREAD_ALLOCATION				0x0000091c
+
+#define VIVS_CL_KICKER						0x00000920
+
+#define VIVS_CL_UNK00924					0x00000924
+
+#define VIVS_PA							0x00000000
+
+#define VIVS_PA_VIEWPORT_SCALE_X				0x00000a00
+
+#define VIVS_PA_VIEWPORT_SCALE_Y				0x00000a04
+
+#define VIVS_PA_VIEWPORT_SCALE_Z				0x00000a08
+
+#define VIVS_PA_VIEWPORT_OFFSET_X				0x00000a0c
+
+#define VIVS_PA_VIEWPORT_OFFSET_Y				0x00000a10
+
+#define VIVS_PA_VIEWPORT_OFFSET_Z				0x00000a14
+
+#define VIVS_PA_LINE_WIDTH					0x00000a18
+
+#define VIVS_PA_POINT_SIZE					0x00000a1c
+
+#define VIVS_PA_SYSTEM_MODE					0x00000a28
+#define VIVS_PA_SYSTEM_MODE_UNK0				0x00000001
+#define VIVS_PA_SYSTEM_MODE_UNK4				0x00000010
+
+#define VIVS_PA_W_CLIP_LIMIT					0x00000a2c
+
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT				0x00000a30
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK		0x000000ff
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT		0
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x)			(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK)
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK		0x0000ff00
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT		8
+#define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x)		(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK)
+
+#define VIVS_PA_CONFIG						0x00000a34
+#define VIVS_PA_CONFIG_POINT_SIZE_ENABLE			0x00000004
+#define VIVS_PA_CONFIG_POINT_SIZE_ENABLE_MASK			0x00000008
+#define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE			0x00000010
+#define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE_MASK			0x00000020
+#define VIVS_PA_CONFIG_CULL_FACE_MODE__MASK			0x00000300
+#define VIVS_PA_CONFIG_CULL_FACE_MODE__SHIFT			8
+#define VIVS_PA_CONFIG_CULL_FACE_MODE_OFF			0x00000000
+#define VIVS_PA_CONFIG_CULL_FACE_MODE_CW			0x00000100
+#define VIVS_PA_CONFIG_CULL_FACE_MODE_CCW			0x00000200
+#define VIVS_PA_CONFIG_CULL_FACE_MODE_MASK			0x00000400
+#define VIVS_PA_CONFIG_FILL_MODE__MASK				0x00003000
+#define VIVS_PA_CONFIG_FILL_MODE__SHIFT				12
+#define VIVS_PA_CONFIG_FILL_MODE_POINT				0x00000000
+#define VIVS_PA_CONFIG_FILL_MODE_WIREFRAME			0x00001000
+#define VIVS_PA_CONFIG_FILL_MODE_SOLID				0x00002000
+#define VIVS_PA_CONFIG_FILL_MODE_MASK				0x00004000
+#define VIVS_PA_CONFIG_SHADE_MODEL__MASK			0x00030000
+#define VIVS_PA_CONFIG_SHADE_MODEL__SHIFT			16
+#define VIVS_PA_CONFIG_SHADE_MODEL_FLAT				0x00000000
+#define VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH			0x00010000
+#define VIVS_PA_CONFIG_SHADE_MODEL_MASK				0x00040000
+#define VIVS_PA_CONFIG_UNK22					0x00400000
+#define VIVS_PA_CONFIG_UNK22_MASK				0x00800000
+
+#define VIVS_PA_LINE_UNK00A38					0x00000a38
+
+#define VIVS_PA_LINE_UNK00A3C					0x00000a3c
+
+#define VIVS_PA_SHADER_ATTRIBUTES(i0)			       (0x00000a40 + 0x4*(i0))
+#define VIVS_PA_SHADER_ATTRIBUTES__ESIZE			0x00000004
+#define VIVS_PA_SHADER_ATTRIBUTES__LEN				0x0000000a
+#define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT			0x00000001
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK			0x000000f0
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT			4
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK4(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK)
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK			0x00000f00
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT			8
+#define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK)
+
+#define VIVS_PA_VIEWPORT_UNK00A80				0x00000a80
+
+#define VIVS_PA_VIEWPORT_UNK00A84				0x00000a84
+
+#define VIVS_PA_VIEWPORT_UNK00A8C				0x00000a8c
+
+#define VIVS_SE							0x00000000
+
+#define VIVS_SE_SCISSOR_LEFT					0x00000c00
+
+#define VIVS_SE_SCISSOR_TOP					0x00000c04
+
+#define VIVS_SE_SCISSOR_RIGHT					0x00000c08
+
+#define VIVS_SE_SCISSOR_BOTTOM					0x00000c0c
+
+#define VIVS_SE_DEPTH_SCALE					0x00000c10
+
+#define VIVS_SE_DEPTH_BIAS					0x00000c14
+
+#define VIVS_SE_CONFIG						0x00000c18
+#define VIVS_SE_CONFIG_LAST_PIXEL_ENABLE			0x00000001
+
+#define VIVS_SE_UNK00C1C					0x00000c1c
+
+#define VIVS_SE_CLIP_RIGHT					0x00000c20
+
+#define VIVS_SE_CLIP_BOTTOM					0x00000c24
+
+#define VIVS_RA							0x00000000
+
+#define VIVS_RA_CONTROL						0x00000e00
+#define VIVS_RA_CONTROL_UNK0					0x00000001
+#define VIVS_RA_CONTROL_LAST_VARYING_2X				0x00000002
+
+#define VIVS_RA_MULTISAMPLE_UNK00E04				0x00000e04
+
+#define VIVS_RA_EARLY_DEPTH					0x00000e08
+
+#define VIVS_RA_MULTISAMPLE_UNK00E10(i0)		       (0x00000e10 + 0x4*(i0))
+#define VIVS_RA_MULTISAMPLE_UNK00E10__ESIZE			0x00000004
+#define VIVS_RA_MULTISAMPLE_UNK00E10__LEN			0x00000004
+
+#define VIVS_RA_CENTROID_TABLE(i0)			       (0x00000e40 + 0x4*(i0))
+#define VIVS_RA_CENTROID_TABLE__ESIZE				0x00000004
+#define VIVS_RA_CENTROID_TABLE__LEN				0x00000010
+
+#define VIVS_PS							0x00000000
+
+#define VIVS_PS_END_PC						0x00001000
+
+#define VIVS_PS_OUTPUT_REG					0x00001004
+
+#define VIVS_PS_INPUT_COUNT					0x00001008
+#define VIVS_PS_INPUT_COUNT_COUNT__MASK				0x0000000f
+#define VIVS_PS_INPUT_COUNT_COUNT__SHIFT			0
+#define VIVS_PS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK)
+#define VIVS_PS_INPUT_COUNT_UNK8__MASK				0x00001f00
+#define VIVS_PS_INPUT_COUNT_UNK8__SHIFT				8
+#define VIVS_PS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK)
+
+#define VIVS_PS_TEMP_REGISTER_CONTROL				0x0000100c
+#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
+#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
+#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
+
+#define VIVS_PS_CONTROL						0x00001010
+#define VIVS_PS_CONTROL_BYPASS					0x00000001
+#define VIVS_PS_CONTROL_UNK1					0x00000002
+
+#define VIVS_PS_PERF_COUNTER					0x00001014
+
+#define VIVS_PS_START_PC					0x00001018
+
+#define VIVS_PS_RANGE						0x0000101c
+#define VIVS_PS_RANGE_LOW__MASK					0x0000ffff
+#define VIVS_PS_RANGE_LOW__SHIFT				0
+#define VIVS_PS_RANGE_LOW(x)					(((x) << VIVS_PS_RANGE_LOW__SHIFT) & VIVS_PS_RANGE_LOW__MASK)
+#define VIVS_PS_RANGE_HIGH__MASK				0xffff0000
+#define VIVS_PS_RANGE_HIGH__SHIFT				16
+#define VIVS_PS_RANGE_HIGH(x)					(((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK)
+
+#define VIVS_PS_INST_MEM(i0)				       (0x00006000 + 0x4*(i0))
+#define VIVS_PS_INST_MEM__ESIZE					0x00000004
+#define VIVS_PS_INST_MEM__LEN					0x00000400
+
+#define VIVS_PS_UNIFORMS(i0)				       (0x00007000 + 0x4*(i0))
+#define VIVS_PS_UNIFORMS__ESIZE					0x00000004
+#define VIVS_PS_UNIFORMS__LEN					0x00000400
+
+#define VIVS_PE							0x00000000
+
+#define VIVS_PE_DEPTH_CONFIG					0x00001400
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__MASK			0x00000003
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__SHIFT			0
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE			0x00000000
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z			0x00000001
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_W			0x00000002
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_MASK			0x00000008
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__MASK			0x00000010
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__SHIFT		4
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16			0x00000000
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8			0x00000010
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK			0x00000020
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK			0x00000700
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT			8
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x)			(((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK)
+#define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK			0x00000800
+#define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE			0x00001000
+#define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK			0x00002000
+#define VIVS_PE_DEPTH_CONFIG_EARLY_Z				0x00010000
+#define VIVS_PE_DEPTH_CONFIG_EARLY_Z_MASK			0x00020000
+#define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH				0x00100000
+#define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH_MASK			0x00200000
+#define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS				0x01000000
+#define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS_MASK			0x02000000
+#define VIVS_PE_DEPTH_CONFIG_SUPER_TILED			0x04000000
+#define VIVS_PE_DEPTH_CONFIG_SUPER_TILED_MASK			0x08000000
+
+#define VIVS_PE_DEPTH_NEAR					0x00001404
+
+#define VIVS_PE_DEPTH_FAR					0x00001408
+
+#define VIVS_PE_DEPTH_NORMALIZE					0x0000140c
+
+#define VIVS_PE_DEPTH_ADDR					0x00001410
+
+#define VIVS_PE_DEPTH_STRIDE					0x00001414
+
+#define VIVS_PE_STENCIL_OP					0x00001418
+#define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK			0x00000007
+#define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT			0
+#define VIVS_PE_STENCIL_OP_FUNC_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK)
+#define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK			0x00000008
+#define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK			0x00000070
+#define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT			4
+#define VIVS_PE_STENCIL_OP_PASS_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK)
+#define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK			0x00000080
+#define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK			0x00000700
+#define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT			8
+#define VIVS_PE_STENCIL_OP_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK)
+#define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK			0x00000800
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK		0x00007000
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT		12
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK)
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK		0x00008000
+#define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK			0x00070000
+#define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT			16
+#define VIVS_PE_STENCIL_OP_FUNC_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK)
+#define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK			0x00080000
+#define VIVS_PE_STENCIL_OP_PASS_BACK__MASK			0x00700000
+#define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT			20
+#define VIVS_PE_STENCIL_OP_PASS_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK)
+#define VIVS_PE_STENCIL_OP_PASS_BACK_MASK			0x00800000
+#define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK			0x07000000
+#define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT			24
+#define VIVS_PE_STENCIL_OP_FAIL_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK)
+#define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK			0x08000000
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK		0x70000000
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT		28
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK)
+#define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK			0x80000000
+
+#define VIVS_PE_STENCIL_CONFIG					0x0000141c
+#define VIVS_PE_STENCIL_CONFIG_MODE__MASK			0x00000003
+#define VIVS_PE_STENCIL_CONFIG_MODE__SHIFT			0
+#define VIVS_PE_STENCIL_CONFIG_MODE_DISABLED			0x00000000
+#define VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED			0x00000001
+#define VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED			0x00000002
+#define VIVS_PE_STENCIL_CONFIG_MODE_MASK			0x00000010
+#define VIVS_PE_STENCIL_CONFIG_REF_FRONT_MASK			0x00000020
+#define VIVS_PE_STENCIL_CONFIG_MASK_FRONT_MASK			0x00000040
+#define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK			0x00000080
+#define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK			0x0000ff00
+#define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT			8
+#define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK)
+#define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK			0x00ff0000
+#define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT		16
+#define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK)
+#define VIVS_PE_STENCIL_CONFIG_WRITE_MASK__MASK			0xff000000
+#define VIVS_PE_STENCIL_CONFIG_WRITE_MASK__SHIFT		24
+#define VIVS_PE_STENCIL_CONFIG_WRITE_MASK(x)			(((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK__MASK)
+
+#define VIVS_PE_ALPHA_OP					0x00001420
+#define VIVS_PE_ALPHA_OP_ALPHA_TEST				0x00000001
+#define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK			0x00000002
+#define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK			0x00000070
+#define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT			4
+#define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK)
+#define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK			0x00000080
+#define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK			0x0000ff00
+#define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT			8
+#define VIVS_PE_ALPHA_OP_ALPHA_REF(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK)
+#define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK		0x00010000
+
+#define VIVS_PE_ALPHA_BLEND_COLOR				0x00001424
+#define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK			0x000000ff
+#define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT			0
+#define VIVS_PE_ALPHA_BLEND_COLOR_B(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK)
+#define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK			0x0000ff00
+#define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT			8
+#define VIVS_PE_ALPHA_BLEND_COLOR_G(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK)
+#define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK			0x00ff0000
+#define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT			16
+#define VIVS_PE_ALPHA_BLEND_COLOR_R(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK)
+#define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK			0xff000000
+#define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT			24
+#define VIVS_PE_ALPHA_BLEND_COLOR_A(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK)
+
+#define VIVS_PE_ALPHA_CONFIG					0x00001428
+#define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR			0x00000001
+#define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK		0x00000002
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK		0x00000004
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK		0x00000008
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK		0x000000f0
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT		4
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK)
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK		0x00000f00
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT		8
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK)
+#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK			0x00007000
+#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT			12
+#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK)
+#define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK			0x00008000
+#define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA		0x00010000
+#define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK		0x00020000
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK		0x00040000
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK		0x00080000
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK		0x00f00000
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT		20
+#define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK)
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK		0x0f000000
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT		24
+#define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK)
+#define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK			0x70000000
+#define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT			28
+#define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK)
+#define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK			0x80000000
+
+#define VIVS_PE_COLOR_FORMAT					0x0000142c
+#define VIVS_PE_COLOR_FORMAT_FORMAT__MASK			0x0000000f
+#define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT			0
+#define VIVS_PE_COLOR_FORMAT_FORMAT(x)				(((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK)
+#define VIVS_PE_COLOR_FORMAT_FORMAT_MASK			0x00000010
+#define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK			0x00000f00
+#define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT			8
+#define VIVS_PE_COLOR_FORMAT_COMPONENTS(x)			(((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK)
+#define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK			0x00001000
+#define VIVS_PE_COLOR_FORMAT_OVERWRITE				0x00010000
+#define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK			0x00020000
+#define VIVS_PE_COLOR_FORMAT_SUPER_TILED			0x00100000
+#define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK			0x00200000
+
+#define VIVS_PE_COLOR_ADDR					0x00001430
+
+#define VIVS_PE_COLOR_STRIDE					0x00001434
+
+#define VIVS_PE_HDEPTH_CONTROL					0x00001454
+#define VIVS_PE_HDEPTH_CONTROL_FORMAT__MASK			0x0000000f
+#define VIVS_PE_HDEPTH_CONTROL_FORMAT__SHIFT			0
+#define VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED			0x00000000
+#define VIVS_PE_HDEPTH_CONTROL_FORMAT_D16			0x00000005
+#define VIVS_PE_HDEPTH_CONTROL_FORMAT_D24S8			0x00000008
+
+#define VIVS_PE_HDEPTH_ADDR					0x00001458
+
+#define VIVS_PE_UNK0145C					0x0000145c
+
+#define VIVS_PE_PIPE(i0)				       (0x00000000 + 0x4*(i0))
+#define VIVS_PE_PIPE__ESIZE					0x00000004
+#define VIVS_PE_PIPE__LEN					0x00000008
+
+#define VIVS_PE_PIPE_COLOR_ADDR(i0)			       (0x00001460 + 0x4*(i0))
+
+#define VIVS_PE_PIPE_DEPTH_ADDR(i0)			       (0x00001480 + 0x4*(i0))
+
+#define VIVS_PE_PIPE_ADDR_UNK01500(i0)			       (0x00001500 + 0x4*(i0))
+
+#define VIVS_PE_PIPE_ADDR_UNK01520(i0)			       (0x00001520 + 0x4*(i0))
+
+#define VIVS_PE_STENCIL_CONFIG_EXT				0x000014a0
+#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK		0x000000ff
+#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT		0
+#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK)
+#define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK		0x00000100
+#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK			0x00000200
+#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK			0xffff0000
+#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT			16
+#define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK)
+
+#define VIVS_PE_LOGIC_OP					0x000014a4
+#define VIVS_PE_LOGIC_OP_OP__MASK				0x0000000f
+#define VIVS_PE_LOGIC_OP_OP__SHIFT				0
+#define VIVS_PE_LOGIC_OP_OP(x)					(((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK)
+#define VIVS_PE_LOGIC_OP_OP_MASK				0x00000010
+
+#define VIVS_PE_DITHER(i0)				       (0x000014a8 + 0x4*(i0))
+#define VIVS_PE_DITHER__ESIZE					0x00000004
+#define VIVS_PE_DITHER__LEN					0x00000002
+
+#define VIVS_PE_UNK014B0					0x000014b0
+
+#define VIVS_PE_UNK014B4					0x000014b4
+
+#define VIVS_PE_UNK01580(i0)				       (0x00001580 + 0x4*(i0))
+#define VIVS_PE_UNK01580__ESIZE					0x00000004
+#define VIVS_PE_UNK01580__LEN					0x00000003
+
+#define VIVS_CO							0x00000000
+
+#define VIVS_CO_UNK03008					0x00003008
+
+#define VIVS_CO_KICKER						0x0000300c
+
+#define VIVS_CO_UNK03010					0x00003010
+
+#define VIVS_CO_UNK03014					0x00003014
+
+#define VIVS_CO_UNK03018					0x00003018
+
+#define VIVS_CO_UNK0301C					0x0000301c
+
+#define VIVS_CO_UNK03020					0x00003020
+
+#define VIVS_CO_UNK03024					0x00003024
+
+#define VIVS_CO_UNK03040					0x00003040
+
+#define VIVS_CO_UNK03044					0x00003044
+
+#define VIVS_CO_UNK03048					0x00003048
+
+#define VIVS_CO_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
+#define VIVS_CO_SAMPLER__ESIZE					0x00000004
+#define VIVS_CO_SAMPLER__LEN					0x00000008
+
+#define VIVS_CO_SAMPLER_UNK03060(i0)			       (0x00003060 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK03080(i0)			       (0x00003080 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK030A0(i0)			       (0x000030a0 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK030C0(i0)			       (0x000030c0 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK030E0(i0)			       (0x000030e0 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK03100(i0)			       (0x00003100 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK03120(i0)			       (0x00003120 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK03140(i0)			       (0x00003140 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK03160(i0)			       (0x00003160 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK03180(i0)			       (0x00003180 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK031A0(i0)			       (0x000031a0 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK031C0(i0)			       (0x000031c0 + 0x4*(i0))
+
+#define VIVS_CO_SAMPLER_UNK031E0(i0)			       (0x000031e0 + 0x4*(i0))
+
+#define VIVS_CO_ADDR_UNK03200(i0)			       (0x00003200 + 0x20*(i0))
+#define VIVS_CO_ADDR_UNK03200__ESIZE				0x00000020
+#define VIVS_CO_ADDR_UNK03200__LEN				0x00000008
+
+#define VIVS_CO_ADDR_UNK03200_PPIPE(i0, i1)		       (0x00003200 + 0x20*(i0) + 0x4*(i1))
+#define VIVS_CO_ADDR_UNK03200_PPIPE__ESIZE			0x00000004
+#define VIVS_CO_ADDR_UNK03200_PPIPE__LEN			0x00000008
+
+#define VIVS_RS							0x00000000
+
+#define VIVS_RS_KICKER						0x00001600
+
+#define VIVS_RS_CONFIG						0x00001604
+#define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK			0x0000001f
+#define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT			0
+#define VIVS_RS_CONFIG_SOURCE_FORMAT(x)				(((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK)
+#define VIVS_RS_CONFIG_DOWNSAMPLE_X				0x00000020
+#define VIVS_RS_CONFIG_DOWNSAMPLE_Y				0x00000040
+#define VIVS_RS_CONFIG_SOURCE_TILED				0x00000080
+#define VIVS_RS_CONFIG_DEST_FORMAT__MASK			0x00001f00
+#define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT			8
+#define VIVS_RS_CONFIG_DEST_FORMAT(x)				(((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK)
+#define VIVS_RS_CONFIG_DEST_TILED				0x00004000
+#define VIVS_RS_CONFIG_SWAP_RB					0x20000000
+#define VIVS_RS_CONFIG_FLIP					0x40000000
+
+#define VIVS_RS_SOURCE_ADDR					0x00001608
+
+#define VIVS_RS_SOURCE_STRIDE					0x0000160c
+#define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT			0
+#define VIVS_RS_SOURCE_STRIDE_STRIDE(x)				(((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK)
+#define VIVS_RS_SOURCE_STRIDE_MULTI				0x40000000
+#define VIVS_RS_SOURCE_STRIDE_TILING				0x80000000
+
+#define VIVS_RS_DEST_ADDR					0x00001610
+
+#define VIVS_RS_DEST_STRIDE					0x00001614
+#define VIVS_RS_DEST_STRIDE_STRIDE__MASK			0x0003ffff
+#define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT			0
+#define VIVS_RS_DEST_STRIDE_STRIDE(x)				(((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK)
+#define VIVS_RS_DEST_STRIDE_MULTI				0x40000000
+#define VIVS_RS_DEST_STRIDE_TILING				0x80000000
+
+#define VIVS_RS_WINDOW_SIZE					0x00001620
+#define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK			0xffff0000
+#define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT			16
+#define VIVS_RS_WINDOW_SIZE_HEIGHT(x)				(((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK)
+#define VIVS_RS_WINDOW_SIZE_WIDTH__MASK				0x0000ffff
+#define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT			0
+#define VIVS_RS_WINDOW_SIZE_WIDTH(x)				(((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK)
+
+#define VIVS_RS_DITHER(i0)				       (0x00001630 + 0x4*(i0))
+#define VIVS_RS_DITHER__ESIZE					0x00000004
+#define VIVS_RS_DITHER__LEN					0x00000002
+
+#define VIVS_RS_CLEAR_CONTROL					0x0000163c
+#define VIVS_RS_CLEAR_CONTROL_BITS__MASK			0x0000ffff
+#define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT			0
+#define VIVS_RS_CLEAR_CONTROL_BITS(x)				(((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK)
+#define VIVS_RS_CLEAR_CONTROL_MODE__MASK			0x00030000
+#define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT			16
+#define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED			0x00000000
+#define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1			0x00010000
+#define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4			0x00020000
+#define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2			0x00030000
+
+#define VIVS_RS_FILL_VALUE(i0)				       (0x00001640 + 0x4*(i0))
+#define VIVS_RS_FILL_VALUE__ESIZE				0x00000004
+#define VIVS_RS_FILL_VALUE__LEN					0x00000004
+
+#define VIVS_RS_EXTRA_CONFIG					0x000016a0
+#define VIVS_RS_EXTRA_CONFIG_AA__MASK				0x00000003
+#define VIVS_RS_EXTRA_CONFIG_AA__SHIFT				0
+#define VIVS_RS_EXTRA_CONFIG_AA(x)				(((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK)
+#define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK			0x00000300
+#define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT			8
+#define VIVS_RS_EXTRA_CONFIG_ENDIAN(x)				(((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK)
+
+#define VIVS_RS_UNK016B4					0x000016b4
+
+#define VIVS_RS_PIPE(i0)				       (0x00000000 + 0x4*(i0))
+#define VIVS_RS_PIPE__ESIZE					0x00000004
+#define VIVS_RS_PIPE__LEN					0x00000008
+
+#define VIVS_RS_PIPE_SOURCE_ADDR(i0)			       (0x000016c0 + 0x4*(i0))
+
+#define VIVS_RS_PIPE_DEST_ADDR(i0)			       (0x000016e0 + 0x4*(i0))
+
+#define VIVS_RS_PIPE_OFFSET(i0)				       (0x00001700 + 0x4*(i0))
+#define VIVS_RS_PIPE_OFFSET_X__MASK				0x0000ffff
+#define VIVS_RS_PIPE_OFFSET_X__SHIFT				0
+#define VIVS_RS_PIPE_OFFSET_X(x)				(((x) << VIVS_RS_PIPE_OFFSET_X__SHIFT) & VIVS_RS_PIPE_OFFSET_X__MASK)
+#define VIVS_RS_PIPE_OFFSET_Y__MASK				0xffff0000
+#define VIVS_RS_PIPE_OFFSET_Y__SHIFT				16
+#define VIVS_RS_PIPE_OFFSET_Y(x)				(((x) << VIVS_RS_PIPE_OFFSET_Y__SHIFT) & VIVS_RS_PIPE_OFFSET_Y__MASK)
+
+#define VIVS_TS							0x00000000
+
+#define VIVS_TS_FLUSH_CACHE					0x00001650
+#define VIVS_TS_FLUSH_CACHE_FLUSH				0x00000001
+
+#define VIVS_TS_MEM_CONFIG					0x00001654
+#define VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR			0x00000001
+#define VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR			0x00000002
+#define VIVS_TS_MEM_CONFIG_DEPTH_16BPP				0x00000008
+#define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE			0x00000010
+#define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE			0x00000020
+#define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION			0x00000040
+#define VIVS_TS_MEM_CONFIG_MSAA					0x00000080
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__MASK			0x00000f00
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__SHIFT			8
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A4R4G4B4			0x00000000
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A1R5G5B5			0x00000100
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_R5G6B5			0x00000200
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8			0x00000300
+#define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_X8R8G8B8			0x00000400
+#define VIVS_TS_MEM_CONFIG_UNK12				0x00001000
+#define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE			0x00002000
+
+#define VIVS_TS_COLOR_STATUS_BASE				0x00001658
+
+#define VIVS_TS_COLOR_SURFACE_BASE				0x0000165c
+
+#define VIVS_TS_COLOR_CLEAR_VALUE				0x00001660
+
+#define VIVS_TS_DEPTH_STATUS_BASE				0x00001664
+
+#define VIVS_TS_DEPTH_SURFACE_BASE				0x00001668
+
+#define VIVS_TS_DEPTH_CLEAR_VALUE				0x0000166c
+
+#define VIVS_TS_DEPTH_AUTO_DISABLE_COUNT			0x00001670
+
+#define VIVS_TS_COLOR_AUTO_DISABLE_COUNT			0x00001674
+
+#define VIVS_TS_HDEPTH_STATUS_BASE				0x000016a4
+
+#define VIVS_TS_HDEPTH_CLEAR_VALUE				0x000016a8
+
+#define VIVS_TS_HDEPTH_SIZE					0x000016ac
+
+#define VIVS_TS_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
+#define VIVS_TS_SAMPLER__ESIZE					0x00000004
+#define VIVS_TS_SAMPLER__LEN					0x00000008
+
+#define VIVS_TS_SAMPLER_CONFIG(i0)			       (0x00001720 + 0x4*(i0))
+#define VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK			0x00000003
+#define VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT			0
+#define VIVS_TS_SAMPLER_CONFIG_ENABLE(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT) & VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK)
+#define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK			0x000000f0
+#define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT			4
+#define VIVS_TS_SAMPLER_CONFIG_FORMAT(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK)
+
+#define VIVS_TS_SAMPLER_STATUS_BASE(i0)			       (0x00001740 + 0x4*(i0))
+
+#define VIVS_TS_SAMPLER_CLEAR_VALUE(i0)			       (0x00001760 + 0x4*(i0))
+
+#define VIVS_YUV						0x00000000
+
+#define VIVS_YUV_UNK01678					0x00001678
+
+#define VIVS_YUV_UNK0167C					0x0000167c
+
+#define VIVS_YUV_UNK01680					0x00001680
+
+#define VIVS_YUV_UNK01684					0x00001684
+
+#define VIVS_YUV_UNK01688					0x00001688
+
+#define VIVS_YUV_UNK0168C					0x0000168c
+
+#define VIVS_YUV_UNK01690					0x00001690
+
+#define VIVS_YUV_UNK01694					0x00001694
+
+#define VIVS_YUV_UNK01698					0x00001698
+
+#define VIVS_YUV_UNK0169C					0x0000169c
+
+#define VIVS_TE							0x00000000
+
+#define VIVS_TE_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
+#define VIVS_TE_SAMPLER__ESIZE					0x00000004
+#define VIVS_TE_SAMPLER__LEN					0x0000000c
+
+#define VIVS_TE_SAMPLER_CONFIG0(i0)			       (0x00002000 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
+#define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT			0
+#define VIVS_TE_SAMPLER_CONFIG0_TYPE(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
+#define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
+#define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
+#define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
+#define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
+#define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT			7
+#define VIVS_TE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
+#define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT			9
+#define VIVS_TE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
+#define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT			11
+#define VIVS_TE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
+#define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
+#define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
+#define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
+#define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
+#define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK)
+#define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK		0xff000000
+#define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT		24
+#define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK)
+
+#define VIVS_TE_SAMPLER_SIZE(i0)			       (0x00002040 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
+#define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT			0
+#define VIVS_TE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK)
+#define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
+#define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT			16
+#define VIVS_TE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK)
+
+#define VIVS_TE_SAMPLER_LOG_SIZE(i0)			       (0x00002080 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
+#define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
+#define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK)
+#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
+#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
+#define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
+
+#define VIVS_TE_SAMPLER_LOD_CONFIG(i0)			       (0x000020c0 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK)
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
+#define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK)
+#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
+#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
+#define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK)
+
+#define VIVS_TE_SAMPLER_UNK02100(i0)			       (0x00002100 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_UNK02140(i0)			       (0x00002140 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_UNK02180(i0)			       (0x00002180 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_CONFIG1(i0)			       (0x000021c0 + 0x4*(i0))
+#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000001f
+#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
+#define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK			0x00000700
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK			0x00007000
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK			0x00070000
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK			0x00700000
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
+#define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
+#define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
+#define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
+#define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK)
+
+#define VIVS_TE_SAMPLER_UNK02200(i0)			       (0x00002200 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_UNK02240(i0)			       (0x00002240 + 0x4*(i0))
+
+#define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1)		       (0x00002400 + 0x4*(i0) + 0x40*(i1))
+#define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE				0x00000040
+#define VIVS_TE_SAMPLER_LOD_ADDR__LEN				0x0000000e
+
+#define VIVS_NTE						0x00000000
+
+#define VIVS_NTE_SAMPLER(i0)				       (0x00010000 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER__ESIZE					0x00000004
+#define VIVS_NTE_SAMPLER__LEN					0x00000020
+
+#define VIVS_NTE_SAMPLER_CONFIG0(i0)			       (0x00010000 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
+#define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT			0
+#define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
+#define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
+#define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
+#define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
+#define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
+#define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT			7
+#define VIVS_NTE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
+#define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT			9
+#define VIVS_NTE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
+#define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT			11
+#define VIVS_NTE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
+#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
+#define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
+#define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
+#define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
+#define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK		0xff000000
+#define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT		24
+#define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK)
+
+#define VIVS_NTE_SAMPLER_SIZE(i0)			       (0x00010080 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
+#define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT			0
+#define VIVS_NTE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK)
+#define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
+#define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT			16
+#define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK)
+
+#define VIVS_NTE_SAMPLER_LOG_SIZE(i0)			       (0x00010100 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
+#define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
+#define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK)
+#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
+#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
+#define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
+
+#define VIVS_NTE_SAMPLER_LOD_CONFIG(i0)			       (0x00010180 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK)
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK)
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
+#define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK)
+
+#define VIVS_NTE_SAMPLER_UNK10200(i0)			       (0x00010200 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_UNK10280(i0)			       (0x00010280 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_UNK10300(i0)			       (0x00010300 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_CONFIG1(i0)			       (0x00010380 + 0x4*(i0))
+#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000001f
+#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
+#define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK		0x00000700
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK		0x00007000
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK		0x00070000
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK		0x00700000
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
+#define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
+#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
+#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
+#define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK)
+
+#define VIVS_NTE_SAMPLER_UNK10400(i0)			       (0x00010400 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_UNK10480(i0)			       (0x00010480 + 0x4*(i0))
+
+#define VIVS_NTE_SAMPLER_ADDR(i0)			       (0x00010800 + 0x40*(i0))
+#define VIVS_NTE_SAMPLER_ADDR__ESIZE				0x00000040
+#define VIVS_NTE_SAMPLER_ADDR__LEN				0x00000020
+
+#define VIVS_NTE_SAMPLER_ADDR_LOD(i0, i1)		       (0x00010800 + 0x40*(i0) + 0x4*(i1))
+#define VIVS_NTE_SAMPLER_ADDR_LOD__ESIZE			0x00000004
+#define VIVS_NTE_SAMPLER_ADDR_LOD__LEN				0x0000000e
+
+#define VIVS_NTE_UNK12000(i0)				       (0x00012000 + 0x4*(i0))
+#define VIVS_NTE_UNK12000__ESIZE				0x00000004
+#define VIVS_NTE_UNK12000__LEN					0x00000100
+
+#define VIVS_NTE_UNK12400(i0)				       (0x00012400 + 0x4*(i0))
+#define VIVS_NTE_UNK12400__ESIZE				0x00000004
+#define VIVS_NTE_UNK12400__LEN					0x00000100
+
+#define VIVS_SH							0x00000000
+
+#define VIVS_SH_UNK20000(i0)				       (0x00020000 + 0x4*(i0))
+#define VIVS_SH_UNK20000__ESIZE					0x00000004
+#define VIVS_SH_UNK20000__LEN					0x00002000
+
+#define VIVS_SH_INST_MEM(i0)				       (0x0000c000 + 0x4*(i0))
+#define VIVS_SH_INST_MEM__ESIZE					0x00000004
+#define VIVS_SH_INST_MEM__LEN					0x00001000
+
+#define VIVS_SH_UNK0C000_MIRROR(i0)			       (0x00008000 + 0x4*(i0))
+#define VIVS_SH_UNK0C000_MIRROR__ESIZE				0x00000004
+#define VIVS_SH_UNK0C000_MIRROR__LEN				0x00001000
+
+
+#endif /* STATE_3D_XML */
diff --git a/src/gallium/drivers/etna/hw/state_hi.xml.h b/src/gallium/drivers/etna/hw/state_hi.xml.h
new file mode 100644
index 0000000000..ddf2a68d18
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/state_hi.xml.h
@@ -0,0 +1,375 @@
+#ifndef STATE_HI_XML
+#define STATE_HI_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/state.xml    (  18526 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml   (  18379 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_hi.xml (  22495 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_2d.xml (  51191 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_3d.xml (  54570 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_vg.xml (   5942 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define MMU_EXCEPTION_SLAVE_NOT_PRESENT				0x00000001
+#define MMU_EXCEPTION_PAGE_NOT_PRESENT				0x00000002
+#define MMU_EXCEPTION_WRITE_VIOLATION				0x00000003
+#define VIVS_HI							0x00000000
+
+#define VIVS_HI_CLOCK_CONTROL					0x00000000
+#define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS				0x00000001
+#define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS				0x00000002
+#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK			0x000001fc
+#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT			2
+#define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(x)			(((x) << VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__SHIFT) & VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK)
+#define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD			0x00000200
+#define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING		0x00000400
+#define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS		0x00000800
+#define VIVS_HI_CLOCK_CONTROL_SOFT_RESET			0x00001000
+#define VIVS_HI_CLOCK_CONTROL_IDLE_3D				0x00010000
+#define VIVS_HI_CLOCK_CONTROL_IDLE_2D				0x00020000
+#define VIVS_HI_CLOCK_CONTROL_IDLE_VG				0x00040000
+#define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU			0x00080000
+#define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK		0x00f00000
+#define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT		20
+#define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE(x)		(((x) << VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__SHIFT) & VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK)
+
+#define VIVS_HI_IDLE_STATE					0x00000004
+#define VIVS_HI_IDLE_STATE_FE					0x00000001
+#define VIVS_HI_IDLE_STATE_DE					0x00000002
+#define VIVS_HI_IDLE_STATE_PE					0x00000004
+#define VIVS_HI_IDLE_STATE_SH					0x00000008
+#define VIVS_HI_IDLE_STATE_PA					0x00000010
+#define VIVS_HI_IDLE_STATE_SE					0x00000020
+#define VIVS_HI_IDLE_STATE_RA					0x00000040
+#define VIVS_HI_IDLE_STATE_TX					0x00000080
+#define VIVS_HI_IDLE_STATE_VG					0x00000100
+#define VIVS_HI_IDLE_STATE_IM					0x00000200
+#define VIVS_HI_IDLE_STATE_FP					0x00000400
+#define VIVS_HI_IDLE_STATE_TS					0x00000800
+#define VIVS_HI_IDLE_STATE_AXI_LP				0x80000000
+
+#define VIVS_HI_AXI_CONFIG					0x00000008
+#define VIVS_HI_AXI_CONFIG_AWID__MASK				0x0000000f
+#define VIVS_HI_AXI_CONFIG_AWID__SHIFT				0
+#define VIVS_HI_AXI_CONFIG_AWID(x)				(((x) << VIVS_HI_AXI_CONFIG_AWID__SHIFT) & VIVS_HI_AXI_CONFIG_AWID__MASK)
+#define VIVS_HI_AXI_CONFIG_ARID__MASK				0x000000f0
+#define VIVS_HI_AXI_CONFIG_ARID__SHIFT				4
+#define VIVS_HI_AXI_CONFIG_ARID(x)				(((x) << VIVS_HI_AXI_CONFIG_ARID__SHIFT) & VIVS_HI_AXI_CONFIG_ARID__MASK)
+#define VIVS_HI_AXI_CONFIG_AWCACHE__MASK			0x00000f00
+#define VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT			8
+#define VIVS_HI_AXI_CONFIG_AWCACHE(x)				(((x) << VIVS_HI_AXI_CONFIG_AWCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_AWCACHE__MASK)
+#define VIVS_HI_AXI_CONFIG_ARCACHE__MASK			0x0000f000
+#define VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT			12
+#define VIVS_HI_AXI_CONFIG_ARCACHE(x)				(((x) << VIVS_HI_AXI_CONFIG_ARCACHE__SHIFT) & VIVS_HI_AXI_CONFIG_ARCACHE__MASK)
+
+#define VIVS_HI_AXI_STATUS					0x0000000c
+#define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK			0x0000000f
+#define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT			0
+#define VIVS_HI_AXI_STATUS_WR_ERR_ID(x)				(((x) << VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK)
+#define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK			0x000000f0
+#define VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT			4
+#define VIVS_HI_AXI_STATUS_RD_ERR_ID(x)				(((x) << VIVS_HI_AXI_STATUS_RD_ERR_ID__SHIFT) & VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK)
+#define VIVS_HI_AXI_STATUS_DET_WR_ERR				0x00000100
+#define VIVS_HI_AXI_STATUS_DET_RD_ERR				0x00000200
+
+#define VIVS_HI_INTR_ACKNOWLEDGE				0x00000010
+#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK			0x7fffffff
+#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT		0
+#define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC(x)			(((x) << VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT) & VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK)
+#define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR			0x80000000
+
+#define VIVS_HI_INTR_ENBL					0x00000014
+#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK			0xffffffff
+#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT			0
+#define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC(x)			(((x) << VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT) & VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK)
+
+#define VIVS_HI_CHIP_IDENTITY					0x00000018
+#define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK			0xff000000
+#define VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT			24
+#define VIVS_HI_CHIP_IDENTITY_FAMILY(x)				(((x) << VIVS_HI_CHIP_IDENTITY_FAMILY__SHIFT) & VIVS_HI_CHIP_IDENTITY_FAMILY__MASK)
+#define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK			0x00ff0000
+#define VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT			16
+#define VIVS_HI_CHIP_IDENTITY_PRODUCT(x)			(((x) << VIVS_HI_CHIP_IDENTITY_PRODUCT__SHIFT) & VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK)
+#define VIVS_HI_CHIP_IDENTITY_REVISION__MASK			0x0000f000
+#define VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT			12
+#define VIVS_HI_CHIP_IDENTITY_REVISION(x)			(((x) << VIVS_HI_CHIP_IDENTITY_REVISION__SHIFT) & VIVS_HI_CHIP_IDENTITY_REVISION__MASK)
+
+#define VIVS_HI_CHIP_FEATURE					0x0000001c
+
+#define VIVS_HI_CHIP_MODEL					0x00000020
+
+#define VIVS_HI_CHIP_REV					0x00000024
+
+#define VIVS_HI_CHIP_DATE					0x00000028
+
+#define VIVS_HI_CHIP_TIME					0x0000002c
+
+#define VIVS_HI_CHIP_MINOR_FEATURE_0				0x00000034
+
+#define VIVS_HI_CACHE_CONTROL					0x00000038
+
+#define VIVS_HI_MEMORY_COUNTER_RESET				0x0000003c
+
+#define VIVS_HI_PROFILE_READ_BYTES8				0x00000040
+
+#define VIVS_HI_PROFILE_WRITE_BYTES8				0x00000044
+
+#define VIVS_HI_CHIP_SPECS					0x00000048
+
+#define VIVS_HI_PROFILE_WRITE_BURSTS				0x0000004c
+
+#define VIVS_HI_PROFILE_WRITE_REQUESTS				0x00000050
+
+#define VIVS_HI_PROFILE_READ_BURSTS				0x00000058
+
+#define VIVS_HI_PROFILE_READ_REQUESTS				0x0000005c
+
+#define VIVS_HI_PROFILE_READ_LASTS				0x00000060
+
+#define VIVS_HI_GP_OUT0						0x00000064
+
+#define VIVS_HI_GP_OUT1						0x00000068
+
+#define VIVS_HI_GP_OUT2						0x0000006c
+
+#define VIVS_HI_AXI_CONTROL					0x00000070
+#define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE			0x00000001
+
+#define VIVS_HI_CHIP_MINOR_FEATURE_1				0x00000074
+
+#define VIVS_HI_PROFILE_TOTAL_CYCLES				0x00000078
+
+#define VIVS_HI_PROFILE_IDLE_CYCLES				0x0000007c
+
+#define VIVS_HI_CHIP_SPECS_2					0x00000080
+
+#define VIVS_HI_CHIP_MINOR_FEATURE_2				0x00000084
+
+#define VIVS_HI_CHIP_MINOR_FEATURE_3				0x00000088
+
+#define VIVS_HI_CHIP_MINOR_FEATURE_4				0x00000094
+
+#define VIVS_PM							0x00000000
+
+#define VIVS_PM_POWER_CONTROLS					0x00000100
+#define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING	0x00000001
+#define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING	0x00000002
+#define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING	0x00000004
+#define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK		0x000000f0
+#define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT		4
+#define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER(x)		(((x) << VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK)
+#define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK		0xffff0000
+#define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT		16
+#define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER(x)		(((x) << VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__SHIFT) & VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK)
+
+#define VIVS_PM_MODULE_CONTROLS					0x00000104
+#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE	0x00000001
+#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE	0x00000002
+#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE	0x00000004
+
+#define VIVS_PM_MODULE_STATUS					0x00000108
+#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE		0x00000001
+#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE		0x00000002
+#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE		0x00000004
+
+#define VIVS_PM_PULSE_EATER					0x0000010c
+
+#define VIVS_MMUv2						0x00000000
+
+#define VIVS_MMUv2_SAFE_ADDRESS					0x00000180
+
+#define VIVS_MMUv2_CONFIGURATION				0x00000184
+#define VIVS_MMUv2_CONFIGURATION_MODE__MASK			0x00000001
+#define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT			0
+#define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K			0x00000000
+#define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K			0x00000001
+#define VIVS_MMUv2_CONFIGURATION_MODE_MASK			0x00000008
+#define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK			0x00000010
+#define VIVS_MMUv2_CONFIGURATION_FLUSH__SHIFT			4
+#define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH			0x00000010
+#define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK			0x00000080
+#define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK			0x00000100
+#define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK			0xfffffc00
+#define VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT			10
+#define VIVS_MMUv2_CONFIGURATION_ADDRESS(x)			(((x) << VIVS_MMUv2_CONFIGURATION_ADDRESS__SHIFT) & VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK)
+
+#define VIVS_MMUv2_STATUS					0x00000188
+#define VIVS_MMUv2_STATUS_EXCEPTION0__MASK			0x00000003
+#define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT			0
+#define VIVS_MMUv2_STATUS_EXCEPTION0(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION0__MASK)
+#define VIVS_MMUv2_STATUS_EXCEPTION1__MASK			0x00000030
+#define VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT			4
+#define VIVS_MMUv2_STATUS_EXCEPTION1(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION1__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION1__MASK)
+#define VIVS_MMUv2_STATUS_EXCEPTION2__MASK			0x00000300
+#define VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT			8
+#define VIVS_MMUv2_STATUS_EXCEPTION2(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION2__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION2__MASK)
+#define VIVS_MMUv2_STATUS_EXCEPTION3__MASK			0x00003000
+#define VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT			12
+#define VIVS_MMUv2_STATUS_EXCEPTION3(x)				(((x) << VIVS_MMUv2_STATUS_EXCEPTION3__SHIFT) & VIVS_MMUv2_STATUS_EXCEPTION3__MASK)
+
+#define VIVS_MMUv2_CONTROL					0x0000018c
+#define VIVS_MMUv2_CONTROL_ENABLE				0x00000001
+
+#define VIVS_MMUv2_EXCEPTION_ADDR(i0)			       (0x00000190 + 0x4*(i0))
+#define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE			0x00000004
+#define VIVS_MMUv2_EXCEPTION_ADDR__LEN				0x00000004
+
+#define VIVS_MC							0x00000000
+
+#define VIVS_MC_MMU_FE_PAGE_TABLE				0x00000400
+
+#define VIVS_MC_MMU_TX_PAGE_TABLE				0x00000404
+
+#define VIVS_MC_MMU_PE_PAGE_TABLE				0x00000408
+
+#define VIVS_MC_MMU_PEZ_PAGE_TABLE				0x0000040c
+
+#define VIVS_MC_MMU_RA_PAGE_TABLE				0x00000410
+
+#define VIVS_MC_DEBUG_MEMORY					0x00000414
+#define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320		0x00000008
+#define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS			0x00100000
+#define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS			0x00200000
+
+#define VIVS_MC_MEMORY_BASE_ADDR_RA				0x00000418
+
+#define VIVS_MC_MEMORY_BASE_ADDR_FE				0x0000041c
+
+#define VIVS_MC_MEMORY_BASE_ADDR_TX				0x00000420
+
+#define VIVS_MC_MEMORY_BASE_ADDR_PEZ				0x00000424
+
+#define VIVS_MC_MEMORY_BASE_ADDR_PE				0x00000428
+
+#define VIVS_MC_MEMORY_TIMING_CONTROL				0x0000042c
+
+#define VIVS_MC_MEMORY_FLUSH					0x00000430
+
+#define VIVS_MC_PROFILE_CYCLE_COUNTER				0x00000438
+
+#define VIVS_MC_DEBUG_READ0					0x0000043c
+
+#define VIVS_MC_DEBUG_READ1					0x00000440
+
+#define VIVS_MC_DEBUG_WRITE					0x00000444
+
+#define VIVS_MC_PROFILE_RA_READ					0x00000448
+
+#define VIVS_MC_PROFILE_TX_READ					0x0000044c
+
+#define VIVS_MC_PROFILE_FE_READ					0x00000450
+
+#define VIVS_MC_PROFILE_PE_READ					0x00000454
+
+#define VIVS_MC_PROFILE_DE_READ					0x00000458
+
+#define VIVS_MC_PROFILE_SH_READ					0x0000045c
+
+#define VIVS_MC_PROFILE_PA_READ					0x00000460
+
+#define VIVS_MC_PROFILE_SE_READ					0x00000464
+
+#define VIVS_MC_PROFILE_MC_READ					0x00000468
+
+#define VIVS_MC_PROFILE_HI_READ					0x0000046c
+
+#define VIVS_MC_PROFILE_CONFIG0					0x00000470
+#define VIVS_MC_PROFILE_CONFIG0_FE__MASK			0x0000000f
+#define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT			0
+#define VIVS_MC_PROFILE_CONFIG0_FE_RESET			0x0000000f
+#define VIVS_MC_PROFILE_CONFIG0_DE__MASK			0x00000f00
+#define VIVS_MC_PROFILE_CONFIG0_DE__SHIFT			8
+#define VIVS_MC_PROFILE_CONFIG0_DE_RESET			0x00000f00
+#define VIVS_MC_PROFILE_CONFIG0_PE__MASK			0x000f0000
+#define VIVS_MC_PROFILE_CONFIG0_PE__SHIFT			16
+#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE	0x00000000
+#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE	0x00010000
+#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE	0x00020000
+#define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE	0x00030000
+#define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D		0x000b0000
+#define VIVS_MC_PROFILE_CONFIG0_PE_RESET			0x000f0000
+#define VIVS_MC_PROFILE_CONFIG0_SH__MASK			0x0f000000
+#define VIVS_MC_PROFILE_CONFIG0_SH__SHIFT			24
+#define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES		0x04000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER		0x07000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER	0x08000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER		0x09000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER	0x0a000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER	0x0b000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER	0x0c000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER	0x0d000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER	0x0e000000
+#define VIVS_MC_PROFILE_CONFIG0_SH_RESET			0x0f000000
+
+#define VIVS_MC_PROFILE_CONFIG1					0x00000474
+#define VIVS_MC_PROFILE_CONFIG1_PA__MASK			0x0000000f
+#define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT			0
+#define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER		0x00000003
+#define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER		0x00000004
+#define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER		0x00000005
+#define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER	0x00000006
+#define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER	0x00000007
+#define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER		0x00000008
+#define VIVS_MC_PROFILE_CONFIG1_PA_RESET			0x0000000f
+#define VIVS_MC_PROFILE_CONFIG1_SE__MASK			0x00000f00
+#define VIVS_MC_PROFILE_CONFIG1_SE__SHIFT			8
+#define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT	0x00000000
+#define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT		0x00000100
+#define VIVS_MC_PROFILE_CONFIG1_SE_RESET			0x00000f00
+#define VIVS_MC_PROFILE_CONFIG1_RA__MASK			0x000f0000
+#define VIVS_MC_PROFILE_CONFIG1_RA__SHIFT			16
+#define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT		0x00000000
+#define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT		0x00010000
+#define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z	0x00020000
+#define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT	0x00030000
+#define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER	0x00090000
+#define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER	0x000a0000
+#define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT		0x000b0000
+#define VIVS_MC_PROFILE_CONFIG1_RA_RESET			0x000f0000
+#define VIVS_MC_PROFILE_CONFIG1_TX__MASK			0x0f000000
+#define VIVS_MC_PROFILE_CONFIG1_TX__SHIFT			24
+#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS	0x00000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS	0x01000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS	0x02000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS	0x03000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN			0x04000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT		0x05000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT		0x06000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT		0x07000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT	0x08000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT	0x09000000
+#define VIVS_MC_PROFILE_CONFIG1_TX_RESET			0x0f000000
+
+#define VIVS_MC_PROFILE_CONFIG2					0x00000478
+#define VIVS_MC_PROFILE_CONFIG2_MC__MASK			0x0000000f
+#define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT			0
+#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE	0x00000001
+#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP	0x00000002
+#define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE	0x00000003
+#define VIVS_MC_PROFILE_CONFIG2_MC_RESET			0x0000000f
+#define VIVS_MC_PROFILE_CONFIG2_HI__MASK			0x00000f00
+#define VIVS_MC_PROFILE_CONFIG2_HI__SHIFT			8
+#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED	0x00000000
+#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED	0x00000100
+#define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED	0x00000200
+#define VIVS_MC_PROFILE_CONFIG2_HI_RESET			0x00000f00
+
+#define VIVS_MC_PROFILE_CONFIG3					0x0000047c
+
+#define VIVS_MC_BUS_CONFIG					0x00000480
+
+#define VIVS_MC_START_COMPOSITION				0x00000554
+
+#define VIVS_MC_128B_MERGE					0x00000558
+
+
+#endif /* STATE_HI_XML */
diff --git a/src/gallium/drivers/etna/hw/state_vg.xml.h b/src/gallium/drivers/etna/hw/state_vg.xml.h
new file mode 100644
index 0000000000..0e4c28c6d9
--- /dev/null
+++ b/src/gallium/drivers/etna/hw/state_vg.xml.h
@@ -0,0 +1,181 @@
+#ifndef STATE_VG_XML
+#define STATE_VG_XML
+
+/* Autogenerated file, DO NOT EDIT manually!
+
+This file was generated by the rules-ng-ng headergen tool in this git repository:
+http://0x04.net/cgit/index.cgi/rules-ng-ng
+git clone git://0x04.net/rules-ng-ng
+
+The rules-ng-ng source files this header was generated from are:
+- /home/lst/workdir/etna/etna_viv/rnndb/state.xml    (  18526 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/common.xml   (  18379 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_hi.xml (  22495 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_2d.xml (  51191 bytes, from 2014-07-28 13:45:49)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_3d.xml (  54570 bytes, from 2014-02-17 14:57:56)
+- /home/lst/workdir/etna/etna_viv/rnndb/state_vg.xml (   5942 bytes, from 2014-02-17 14:57:56)
+
+Copyright (C) 2014
+*/
+
+
+#define VIVS_VG							0x00000000
+
+#define VIVS_VG_UNK02800					0x00002800
+
+#define VIVS_VG_UNK02804					0x00002804
+
+#define VIVS_VG_UNK02808					0x00002808
+
+#define VIVS_VG_UNK0280C					0x0000280c
+
+#define VIVS_VG_UNK02810(i0)				       (0x00002810 + 0x4*(i0))
+#define VIVS_VG_UNK02810__ESIZE					0x00000004
+#define VIVS_VG_UNK02810__LEN					0x00000002
+
+#define VIVS_VG_UNK02818(i0)				       (0x00002818 + 0x4*(i0))
+#define VIVS_VG_UNK02818__ESIZE					0x00000004
+#define VIVS_VG_UNK02818__LEN					0x00000002
+
+#define VIVS_VG_UNK02820(i0)				       (0x00002820 + 0x4*(i0))
+#define VIVS_VG_UNK02820__ESIZE					0x00000004
+#define VIVS_VG_UNK02820__LEN					0x00000002
+
+#define VIVS_VG_UNK02828					0x00002828
+
+#define VIVS_VG_UNK0282C					0x0000282c
+
+#define VIVS_VG_UNK02830(i0)				       (0x00002830 + 0x4*(i0))
+#define VIVS_VG_UNK02830__ESIZE					0x00000004
+#define VIVS_VG_UNK02830__LEN					0x00000004
+
+#define VIVS_VG_UNK02840					0x00002840
+
+#define VIVS_VG_UNK02844					0x00002844
+
+#define VIVS_VG_UNK02848					0x00002848
+
+#define VIVS_VG_UNK0284C					0x0000284c
+
+#define VIVS_VG_UNK02850					0x00002850
+
+#define VIVS_VG_UNK02854					0x00002854
+
+#define VIVS_VG_UNK02858					0x00002858
+
+#define VIVS_VG_UNK0285C					0x0000285c
+
+#define VIVS_VG_UNK02860(i0)				       (0x00002860 + 0x4*(i0))
+#define VIVS_VG_UNK02860__ESIZE					0x00000004
+#define VIVS_VG_UNK02860__LEN					0x00000003
+
+#define VIVS_VG_UNK02870(i0)				       (0x00002870 + 0x4*(i0))
+#define VIVS_VG_UNK02870__ESIZE					0x00000004
+#define VIVS_VG_UNK02870__LEN					0x00000003
+
+#define VIVS_VG_UNK02880(i0)				       (0x00002880 + 0x4*(i0))
+#define VIVS_VG_UNK02880__ESIZE					0x00000004
+#define VIVS_VG_UNK02880__LEN					0x00000003
+
+#define VIVS_VG_UNK02890(i0)				       (0x00002890 + 0x4*(i0))
+#define VIVS_VG_UNK02890__ESIZE					0x00000004
+#define VIVS_VG_UNK02890__LEN					0x00000002
+
+#define VIVS_VG_UNK02898(i0)				       (0x00002898 + 0x4*(i0))
+#define VIVS_VG_UNK02898__ESIZE					0x00000004
+#define VIVS_VG_UNK02898__LEN					0x00000002
+
+#define VIVS_VG_UNK028A0(i0)				       (0x000028a0 + 0x4*(i0))
+#define VIVS_VG_UNK028A0__ESIZE					0x00000004
+#define VIVS_VG_UNK028A0__LEN					0x00000002
+
+#define VIVS_VG_UNK028A8(i0)				       (0x000028a8 + 0x4*(i0))
+#define VIVS_VG_UNK028A8__ESIZE					0x00000004
+#define VIVS_VG_UNK028A8__LEN					0x00000002
+
+#define VIVS_VG_UNK028B0(i0)				       (0x000028b0 + 0x4*(i0))
+#define VIVS_VG_UNK028B0__ESIZE					0x00000004
+#define VIVS_VG_UNK028B0__LEN					0x00000002
+
+#define VIVS_VG_UNK028B8(i0)				       (0x000028b8 + 0x4*(i0))
+#define VIVS_VG_UNK028B8__ESIZE					0x00000004
+#define VIVS_VG_UNK028B8__LEN					0x00000002
+
+#define VIVS_VG_UNK028C0					0x000028c0
+
+#define VIVS_VG_UNK028C4					0x000028c4
+
+#define VIVS_VG_UNK028C8					0x000028c8
+
+#define VIVS_VG_UNK028CC					0x000028cc
+
+#define VIVS_VG_UNK028D0					0x000028d0
+
+#define VIVS_VG_UNK028D4					0x000028d4
+
+#define VIVS_VG_UNK028D8					0x000028d8
+
+#define VIVS_VG_UNK028DC					0x000028dc
+
+#define VIVS_VG_UNK028E0					0x000028e0
+
+#define VIVS_VG_UNK028E4					0x000028e4
+
+#define VIVS_VG_UNK028E8					0x000028e8
+
+#define VIVS_VG_UNK028EC					0x000028ec
+
+#define VIVS_VG_UNK028F0					0x000028f0
+
+#define VIVS_VG_UNK028F8					0x000028f8
+
+#define VIVS_VG_UNK028FC					0x000028fc
+
+#define VIVS_VG_UNK02900(i0)				       (0x00002900 + 0x4*(i0))
+#define VIVS_VG_UNK02900__ESIZE					0x00000004
+#define VIVS_VG_UNK02900__LEN					0x00000006
+
+#define VIVS_VG_UNK02918					0x00002918
+
+#define VIVS_VG_UNK0291C					0x0000291c
+
+#define VIVS_VG_UNK02920					0x00002920
+
+#define VIVS_VG_UNK02924					0x00002924
+
+#define VIVS_VG_UNK02928					0x00002928
+
+#define VIVS_VG_UNK0292C					0x0000292c
+
+#define VIVS_VG_UNK02930					0x00002930
+
+#define VIVS_VG_UNK02934					0x00002934
+
+#define VIVS_VG_UNK02938					0x00002938
+
+#define VIVS_VG_UNK0293C					0x0000293c
+
+#define VIVS_VG_UNK02940(i0)				       (0x00002940 + 0x4*(i0))
+#define VIVS_VG_UNK02940__ESIZE					0x00000004
+#define VIVS_VG_UNK02940__LEN					0x00000002
+
+#define VIVS_VG_UNK02948(i0)				       (0x00002948 + 0x4*(i0))
+#define VIVS_VG_UNK02948__ESIZE					0x00000004
+#define VIVS_VG_UNK02948__LEN					0x00000002
+
+#define VIVS_VG_UNK02950					0x00002950
+
+#define VIVS_VG_UNK02954					0x00002954
+
+#define VIVS_VG_UNK02958					0x00002958
+
+#define VIVS_VG_UNK0295C					0x0000295c
+
+#define VIVS_VG_UNK02960					0x00002960
+
+#define VIVS_VG_UNK02980(i0)				       (0x00002980 + 0x4*(i0))
+#define VIVS_VG_UNK02980__ESIZE					0x00000004
+#define VIVS_VG_UNK02980__LEN					0x00000019
+
+
+#endif /* STATE_VG_XML */