armv7m: add generic trace support (TPIU, ITM, etc.)

This provides support for various trace-related subsystems in a
generic and expandable way.

Change-Id: I3a27fa7b8cfb111753088bb8c3d760dd12d1395f
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2538
Tested-by: jenkins

5 files changed, 72 insertions, 0 deletions

diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg
index 6a62992d..bd02e95b 100644
--- a/tcl/target/stm32f1x.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -93,3 +94,16 @@ if {![using_hla]} {
     # perform a soft reset
     cortex_m reset_config sysresetreq
 }
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg
index 0ac73a51..0095615d 100644
--- a/tcl/target/stm32f2x.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -77,3 +78,19 @@ if {![using_hla]} {
    # perform a soft reset
    cortex_m reset_config sysresetreq
 }
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+	mww 0xE0042008 0x00001800
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index 7ddf7d04..f3c22af7 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -118,3 +118,10 @@ proc stm32f3x_default_reset_init {} {
 $_TARGETNAME configure -event examine-end { stm32f3x_default_examine_end }
 $_TARGETNAME configure -event reset-start { stm32f3x_default_reset_start }
 $_TARGETNAME configure -event reset-init { stm32f3x_default_reset_init }
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xe0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg
index fd5cab6a..51d76e7e 100644
--- a/tcl/target/stm32f4x.cfg
+++ b/tcl/target/stm32f4x.cfg
@@ -4,6 +4,7 @@
 # stm32 devices support both JTAG and SWD transports.
 #
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -89,3 +90,19 @@ if {![using_hla]} {
    # perform a soft reset
    cortex_m reset_config sysresetreq
 }
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+	mww 0xE0042008 0x00001800
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}
diff --git a/tcl/target/stm32l1.cfg b/tcl/target/stm32l1.cfg
index d4673a10..7754c849 100644
--- a/tcl/target/stm32l1.cfg
+++ b/tcl/target/stm32l1.cfg
@@ -3,6 +3,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
@@ -107,3 +108,19 @@ $_TARGETNAME configure -event reset-init {
 $_TARGETNAME configure -event reset-start {
 	adapter_khz 300
 }
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000007 0
+
+	# Stop watchdog counters during halt
+	# DBGMCU_APB1_FZ = DBG_IWDG_STOP | DBG_WWDG_STOP
+	mww 0xE0042008 0x00001800
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}