add kernel v4.16 patches

Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>

8 files changed, 1708 insertions, 0 deletions

diff --git a/patches/linux-4.16/0001-ARM-dts-imx7d-add-imx7d-phyboard-zeta.patch b/patches/linux-4.16/0001-ARM-dts-imx7d-add-imx7d-phyboard-zeta.patch
new file mode 100644
index 0000000..f63373b
--- /dev/null
+++ b/patches/linux-4.16/0001-ARM-dts-imx7d-add-imx7d-phyboard-zeta.patch
@@ -0,0 +1,1083 @@
+From: Oleksij Rempel <linux@rempel-privat.de>
+Date: Tue, 13 Jun 2017 11:44:22 +0200
+Subject: [PATCH] ARM: dts: imx7d: add imx7d-phyboard-zeta
+
+Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
+---
+ arch/arm/boot/dts/Makefile                |   1 +
+ arch/arm/boot/dts/imx7d-pba-c-09.dtsi     | 272 ++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/imx7d-peb-av-02.dtsi    | 104 ++++++++++++
+ arch/arm/boot/dts/imx7d-peb-eval-02.dtsi  | 130 ++++++++++++++
+ arch/arm/boot/dts/imx7d-phyboard-zeta.dts | 144 ++++++++++++++++
+ arch/arm/boot/dts/imx7d-phycore-som.dtsi  | 272 ++++++++++++++++++++++++++++++
+ arch/arm/boot/dts/imx7d-pinfunc-lpsr.h    |  76 +++++++++
+ arch/arm/boot/dts/imx7s.dtsi              |   1 +
+ 8 files changed, 1000 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx7d-pba-c-09.dtsi
+ create mode 100644 arch/arm/boot/dts/imx7d-peb-av-02.dtsi
+ create mode 100644 arch/arm/boot/dts/imx7d-peb-eval-02.dtsi
+ create mode 100644 arch/arm/boot/dts/imx7d-phyboard-zeta.dts
+ create mode 100644 arch/arm/boot/dts/imx7d-phycore-som.dtsi
+ create mode 100644 arch/arm/boot/dts/imx7d-pinfunc-lpsr.h
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index ade7a38543dc..721327ad7400 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -533,6 +533,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \
+ 	imx7d-colibri-eval-v3.dtb \
+ 	imx7d-nitrogen7.dtb \
+ 	imx7d-pico-pi.dtb \
++	imx7d-phyboard-zeta.dtb \
+ 	imx7d-sbc-imx7.dtb \
+ 	imx7d-sdb.dtb \
+ 	imx7d-sdb-sht11.dtb \
+diff --git a/arch/arm/boot/dts/imx7d-pba-c-09.dtsi b/arch/arm/boot/dts/imx7d-pba-c-09.dtsi
+new file mode 100644
+index 000000000000..4150c16684b7
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-pba-c-09.dtsi
+@@ -0,0 +1,272 @@
++/*
++ * Copyright (C) 2015 PHYTEC America, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/ {
++	model = "Phytec i.MX7 phyBOARD-Zeta";
++	compatible = "phytec,imx7d-pba-c-09", "phytec,imx7d-phycore-som", "fsl,imx7d";
++
++	regulators {
++		compatible = "simple-bus";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		reg_usb_otg1_vbus: regulator@0 {
++			compatible = "regulator-fixed";
++			reg = <0>;
++			regulator-name = "usb_otg1_vbus";
++			regulator-min-microvolt = <5000000>;
++			regulator-max-microvolt = <5000000>;
++			gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++		};
++
++		reg_usb_otg2_vbus: regulator@1 {
++			compatible = "regulator-fixed";
++			reg = <1>;
++			regulator-name = "usb_otg2_vbus";
++			regulator-min-microvolt = <5000000>;
++			regulator-max-microvolt = <5000000>;
++			gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++		};
++
++		/* Enable if R9 is populated. Conflicts with userbtn2 on PEB-EVAL-02 */
++		/*
++		reg_can1_3v3: regulator@2 {
++			compatible = "regulator-fixed";
++			reg = <2>;
++			regulator-name = "can1-3v3";
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
++			enable-active-high;
++		};
++		*/
++	};
++};
++
++&iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2 &pinctrl_hog_lcd>;
++
++	pinctrl_hog_2: hoggrp-2 {
++		fsl,pins = <
++			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x59 /* SD1 CD */
++			MX7D_PAD_SD1_WP__GPIO5_IO1		0x59 /* PCIe Disable */
++			MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17	0x59 /* PCIe Reset */
++			MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14 /* USB2 pwr */
++			MX7D_PAD_GPIO1_IO09__GPIO1_IO9 		0x59 /* ETH2 Int_N */
++			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x59 /* ETH2 Reset_n */
++			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x59 /* User Button */
++			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x39 /* Boot Circuit Buffer Enable
++									5K pull-up  */
++		>;
++	};
++
++	pinctrl_usdhc1: usdhc1grp {
++		fsl,pins = <
++			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
++			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
++			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
++			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
++			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
++			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
++		>;
++	};
++
++	pinctrl_flexcan1: flexcan1grp {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX	0x59
++			MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX	0x59
++		>;
++	};
++
++	pinctrl_enet2: enet2grp {
++		fsl,pins = <
++			MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL	0x5
++			MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 	0x5
++			MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0	0x5
++			MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1	0x5
++			MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2	0x5
++			MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3	0x5
++			MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0	0x5
++			MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1	0x5
++			MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2	0x5
++			MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3	0x5
++			MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL	0x5
++			MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC	0x5
++		>;
++	};
++};
++
++&iomuxc_lpsr {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog_lpsr_1 &pinctrl_hog_lpsr_lcd>;
++
++	pinctrl_hog_lpsr_1: hoggrp-lpsr_1 {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO05__GPIO1_IO5		0x14 /* USB1 pwr */
++		>;
++	};
++
++	pinctrl_uart5: uart5grp {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO06__UART5_DCE_RX	0x79
++			MX7D_PAD_GPIO1_IO07__UART5_DCE_TX	0x79
++		>;
++	};
++
++	pinctrl_wdog: wdoggrp {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B	0x74
++		>;
++	};
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart5>;
++	assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
++	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
++	status = "disabled";
++};
++
++&usdhc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_usdhc1>;
++	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
++	no-1-8-v; /* Fixed voltage supply, doesn't support vsel */
++	enable-sdio-wakeup;
++	keep-power-in-suspend;
++	status = "disabled";
++};
++
++&flexcan1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_flexcan1>;
++	/* Enable the following if SD1_RESET_B is used to enable/disable CAN xceiver
++	 *  xceiver-supply = <&reg_can1_3v3>;
++	 */
++	status = "disabled";
++};
++
++&fec2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_enet2>;
++	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
++			<&clks IMX7D_ENET2_TIME_ROOT_CLK>;
++	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
++	assigned-clock-rates = <0>, <100000000>;
++	phy-mode = "rgmii";
++	phy-handle = <&ethphy1>;
++	fsl,magic-packet;
++	phy-reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
++	status = "disabled";
++};
++
++/* same MDIO bus as PHY on phyCORE SOM */
++&mdio {
++	ethphy1: ethernet-phy@2 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		interrupt-parent = <&gpio1>;
++		interrupts = <9 0>;
++		reg = <2>;
++		rxdv-skew-ps = <0>;
++		txen-skew-ps = <0>;
++		rxd0-skew-ps = <0>;
++		rxd1-skew-ps = <0>;
++		rxd2-skew-ps = <0>;
++		rxd3-skew-ps = <0>;
++		rxc-skew-ps = <1860>;
++		txc-skew-ps = <1860>;
++	};
++};
++
++&usbotg1 {
++	vbus-supply = <&reg_usb_otg1_vbus>;
++	dr_mode = "host";
++	status = "disabled";
++};
++
++&usbotg2 {
++	vbus-supply = <&reg_usb_otg2_vbus>;
++	status = "disabled";
++};
++
++&wdog1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_wdog>;
++	fsl,wdog_b;
++};
++
++/* DTS pinmuxing and bindings for LCD adapter PEB-AV-02 */
++
++&iomuxc {
++	pinctrl_hog_lcd: hog_lcdgrp {
++		fsl,pins = <
++			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x79
++		>;
++	};
++
++	pinctrl_i2c2: i2c2grp {
++		fsl,pins = <
++			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
++			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
++		>;
++	};
++
++	pinctrl_edt_ts_irq: tsirqgrp {
++		fsl,pins = <
++			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x59
++		>;
++	};
++};
++
++&iomuxc_lpsr {
++	pinctrl_pwm3: pwmgrp {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO03__PWM3_OUT		0x30
++		>;
++	};
++
++	pinctrl_hog_lpsr_lcd: hoggrp_lpsr_lcd {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO01__GPIO1_IO1		0x59
++		>;
++	};
++};
++
++&i2c2 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c2>;
++	status = "disabled";
++
++	ft5406: ft5406@38 {
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_edt_ts_irq>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <14 0>;
++		reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
++		status = "disabled";
++	};
++};
++
++#include "imx7d-peb-av-02.dtsi"
++
++&pwm3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_pwm3>;
++	status = "disabled";
++};
++
++&backlight {
++	pwms = <&pwm3 0 5000000>;
++	enable-gpios = <&gpio1 1 0>;
++	status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/imx7d-peb-av-02.dtsi b/arch/arm/boot/dts/imx7d-peb-av-02.dtsi
+new file mode 100644
+index 000000000000..dcf117c71a92
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-peb-av-02.dtsi
+@@ -0,0 +1,104 @@
++/*
++ * Copyright (C) 2015 PHYTEC America, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/ {
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		brightness-levels = <0 4 8 16 32 64 128 255>;
++		default-brightness-level = <6>;
++		power-supply = <&lcd_3v3>;
++		status = "disabled";
++	};
++
++	lcd_3v3: fixedregulator-lcd {
++		compatible = "regulator-fixed";
++		regulator-name = "lcd_3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-boot-on;
++	};
++};
++
++&iomuxc {
++	pinctrl_lcdif_ctrl: lcdifctrlgrp {
++		fsl,pins = <
++			MX7D_PAD_LCD_CLK__LCD_CLK	0x7e
++			MX7D_PAD_LCD_ENABLE__LCD_ENABLE	0x7e
++			MX7D_PAD_LCD_HSYNC__LCD_HSYNC	0x7e
++			MX7D_PAD_LCD_VSYNC__LCD_VSYNC	0x7e
++		>;
++	};
++
++	pinctrl_lcdif_dat: lcdifdatgrp {
++		fsl,pins = <
++			MX7D_PAD_LCD_DATA00__LCD_DATA0	0x7e
++			MX7D_PAD_LCD_DATA01__LCD_DATA1	0x7e
++			MX7D_PAD_LCD_DATA02__LCD_DATA2	0x7e
++			MX7D_PAD_LCD_DATA03__LCD_DATA3	0x7e
++			MX7D_PAD_LCD_DATA04__LCD_DATA4	0x7e
++			MX7D_PAD_LCD_DATA05__LCD_DATA5	0x7e
++			MX7D_PAD_LCD_DATA06__LCD_DATA6	0x7e
++			MX7D_PAD_LCD_DATA07__LCD_DATA7	0x7e
++			MX7D_PAD_LCD_DATA08__LCD_DATA8	0x7e
++			MX7D_PAD_LCD_DATA09__LCD_DATA9	0x7e
++			MX7D_PAD_LCD_DATA10__LCD_DATA10	0x7e
++			MX7D_PAD_LCD_DATA11__LCD_DATA11	0x7e
++			MX7D_PAD_LCD_DATA12__LCD_DATA12	0x7e
++			MX7D_PAD_LCD_DATA13__LCD_DATA13	0x7e
++			MX7D_PAD_LCD_DATA14__LCD_DATA14	0x7e
++			MX7D_PAD_LCD_DATA15__LCD_DATA15	0x7e
++			MX7D_PAD_LCD_DATA16__LCD_DATA16	0x7e
++			MX7D_PAD_LCD_DATA17__LCD_DATA17	0x7e
++			MX7D_PAD_LCD_DATA18__LCD_DATA18	0x7e
++			MX7D_PAD_LCD_DATA19__LCD_DATA19	0x7e
++			MX7D_PAD_LCD_DATA20__LCD_DATA20	0x7e
++			MX7D_PAD_LCD_DATA21__LCD_DATA21	0x7e
++			MX7D_PAD_LCD_DATA22__LCD_DATA22	0x7e
++			MX7D_PAD_LCD_DATA23__LCD_DATA23	0x7e
++		>;
++	};
++};
++
++&lcdif {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_lcdif_dat
++		&pinctrl_lcdif_ctrl>;
++	display = <&display0>;
++	lcd-supply = <&lcd_3v3>;
++	status = "disabled";
++
++	display0: display {
++		bits-per-pixel = <32>;
++		bus-width = <24>;
++
++		display-timings {
++			native-mode = <&timing0>;
++			timing0: ETM0700G0DH6 {
++				clock-frequency = <33000000>;
++				hactive = <800>;
++				vactive = <480>;
++				hfront-porch = <40>;
++				hback-porch = <216>;
++				hsync-len = <128>;
++				vback-porch = <35>;
++				vfront-porch = <10>;
++				vsync-len = <2>;
++				hsync-active = <0>;
++				vsync-active = <0>;
++				de-active = <1>;
++				pixelclk-active = <1>;
++			};
++		};
++	};
++};
++
++&ft5406 {
++	compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
++	reg = <0x38>;
++	status = "disabled";
++};
+\ No newline at end of file
+diff --git a/arch/arm/boot/dts/imx7d-peb-eval-02.dtsi b/arch/arm/boot/dts/imx7d-peb-eval-02.dtsi
+new file mode 100644
+index 000000000000..8bde5b13e702
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-peb-eval-02.dtsi
+@@ -0,0 +1,130 @@
++/*
++ * Copyright (C) 2015 PHYTEC America, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++/ {
++	phytec_leds: leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_leds_eval>;
++		status = "disabled";
++
++		led@0 {
++			label = "eval_led_1";
++			gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "gpio";
++			default-state = "on";
++		};
++
++		led@1 {
++			label = "eval_led_2";
++			gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "gpio";
++			default-state = "on";
++		};
++
++		led@2 {
++			label = "eval_led_3";
++			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "gpio";
++			default-state = "on";
++		};
++	};
++
++	phytec_buttons: gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&pinctrl_btns_eval>;
++		status = "disabled";
++
++		userbtn@0 {
++			label = "eval_button_1";
++			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
++			linux,code = <0x100>;	/* BTN_MISC */
++		};
++		userbtn@1 {
++			label = "eval_button_2";
++			gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
++			linux,code = <0x100>;   /* BTN_MISC */
++		};
++
++		userbtn@2 {
++			label = "eval_button_3";
++			gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
++			linux,code = <0x100>;	/* BTN_MISC */
++		};
++	};
++};
++
++&iomuxc {
++	pinctrl_i2c4: i2c4grp {
++		fsl,pins = <
++			MX7D_PAD_I2C4_SCL__I2C4_SCL		0x4000007f
++			MX7D_PAD_I2C4_SDA__I2C4_SDA		0x4000007f
++		>;
++	};
++
++	pinctrl_leds_eval: leds_evalgrp {
++		fsl,pins = <
++			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x79	/* Labeled UART6_RX on schematic */
++			MX7D_PAD_UART3_RX_DATA__GPIO4_IO4	0x79
++			MX7D_PAD_EPDC_DATA15__GPIO2_IO15	0x79	/* Labeled EXP_CONN_MUX5 on schematic */
++		>;
++	};
++
++	pinctrl_btns_eval: btns_evalgrp {
++		fsl,pins = <
++			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x79	/* Labeled UART6_TX on schematic */
++			MX7D_PAD_UART3_TX_DATA__GPIO4_IO5	0x79
++			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x79	/* Labeled EXP_CONN_MUX3 on schematic */
++		>;
++	};
++
++	pinctrl_uart1: uart1grp {
++		fsl,pins = <
++			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
++			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
++		>;
++	};
++
++	pinctrl_uart2: uart2grp {
++		fsl,pins = <
++			MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX	0x79
++			MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX	0x79
++		>;
++	};
++};
++
++&i2c4 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c4>;
++	status = "disabled";
++
++	i2c4_eeprom: eeprom@56 {
++		compatible = "onnn,24c32";
++		reg = <0x56>;
++		pagesize = <32>;
++		status = "disabled";
++	};
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart1>;
++	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
++	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
++	status = "disabled";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_uart2>;
++	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
++	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
++	status = "disabled";
++};
+\ No newline at end of file
+diff --git a/arch/arm/boot/dts/imx7d-phyboard-zeta.dts b/arch/arm/boot/dts/imx7d-phyboard-zeta.dts
+new file mode 100644
+index 000000000000..16cf12244f16
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-phyboard-zeta.dts
+@@ -0,0 +1,144 @@
++/*
++ * Copyright (C) 2015 PHYTEC America, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++/dts-v1/;
++
++#include "imx7d-phycore-som.dtsi"
++#include "imx7d-pba-c-09.dtsi"
++#include "imx7d-peb-eval-02.dtsi"
++
++#include "imx7s.dtsi"
++
++/ {
++	chosen {
++		stdout-path = &uart5;
++
++		environment@0 {
++			compatible = "barebox,environment";
++			device-path = &bareboxenv;
++		};
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x80000000 0x40000000>;
++	};
++};
++
++/**** SOM - PCM-061 ****/
++
++&fec1 {
++	status = "okay";
++};
++
++/* eMMC */
++&usdhc3 {
++	status = "okay";
++
++	boot0-partitions {
++		compatible = "fixed-partitions";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		barebox@0 {
++			label = "barebox";
++			reg = <0x0 0x300000>;
++		};
++
++		bareboxenv: bareboxenv@300000 {
++			label = "bareboxenv";
++			reg = <0x300000 0x0>;
++		};
++	};
++};
++
++&i2c_eeprom {
++	status = "okay";
++};
++
++&i2c_rtc {
++	status = "okay";
++};
++
++/**** Carrier Board - PBA-C-09 ****/
++
++&uart5 {
++	status = "okay";
++};
++
++&usdhc1 {
++	status = "okay";
++};
++
++&fec2 {
++	status = "okay";
++};
++
++/* Host mode */
++&usbotg1 {
++	status = "okay";
++};
++
++/* OTG mode */
++&usbotg2 {
++	status = "okay";
++};
++
++&flexcan1 {
++	status = "okay";
++};
++
++&wdog1 {
++	status = "okay";
++};
++
++/**** PEB-AV-02: touch controller ft5406, LCD and PWM backlight control ****/
++&i2c2 {
++	status = "okay";
++};
++
++&ft5406 {
++	status = "okay";
++};
++
++&lcdif {
++	status = "okay";
++};
++
++&pwm3 {
++	status = "okay";
++};
++
++&backlight {
++	status = "okay";
++};
++
++/**** Interfaces on PEB-EVAL-02 ****/
++
++&i2c4 {
++	status = "okay";
++};
++
++&i2c4_eeprom {
++	status = "okay";
++};
++
++&phytec_leds {
++	status = "okay";
++};
++
++&phytec_buttons {
++	status = "okay";
++};
++
++&uart1 {
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
+\ No newline at end of file
+diff --git a/arch/arm/boot/dts/imx7d-phycore-som.dtsi b/arch/arm/boot/dts/imx7d-phycore-som.dtsi
+new file mode 100644
+index 000000000000..5620e80ad517
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-phycore-som.dtsi
+@@ -0,0 +1,272 @@
++/*
++ * Copyright (C) 2015 PHYTEC America, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <dt-bindings/input/input.h>
++#include <imx7d.dtsi>
++
++/ {
++	model = "Phytec i.MX7D phyCORE";
++	compatible = "phytec,imx7d-phycore-som", "fsl,imx7d";
++
++	memory {
++		reg = <0x80000000 0x80000000>;
++	};
++};
++
++&cpu0 {
++	arm-supply = <&sw1a_reg>;
++};
++
++&i2c1 {
++	clock-frequency = <400000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_i2c1>;
++	status = "okay";
++
++	pmic: pfuze3000@08 {
++		compatible = "fsl,pfuze3000";
++		reg = <0x08>;
++
++		regulators {
++			sw1a_reg: sw1a {
++				regulator-min-microvolt = <700000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-ramp-delay = <6250>;
++			};
++
++			/* use sw1c_reg to align with pfuze100/pfuze200 */
++			sw1c_reg: sw1b {
++				regulator-min-microvolt = <700000>;
++				regulator-max-microvolt = <1475000>;
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-ramp-delay = <6250>;
++			};
++
++			sw2_reg: sw2 {
++				regulator-min-microvolt = <1500000>;
++				regulator-max-microvolt = <1850000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			sw3a_reg: sw3 {
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <1650000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			swbst_reg: swbst {
++				regulator-min-microvolt = <5000000>;
++				regulator-max-microvolt = <5150000>;
++			};
++
++			snvs_reg: vsnvs {
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			vref_reg: vrefddr {
++				regulator-boot-on;
++				regulator-always-on;
++			};
++
++			vgen1_reg: vldo1 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			vgen2_reg: vldo2 {
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1550000>;
++				regulator-always-on;
++			};
++
++			vgen3_reg: vccsd {
++				regulator-min-microvolt = <2850000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			vgen4_reg: v33 {
++				regulator-min-microvolt = <2850000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			vgen5_reg: vldo3 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			vgen6_reg: vldo4 {
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++		};
++	};
++	i2c_eeprom: eeprom@50 {
++		compatible = "atmel,24c32";
++		pagesize = <32>;
++		reg = <0x50>;
++		status = "disabled";
++	};
++
++	i2c_rtc: rtc@68 {
++		compatible = "mc,rv4162";
++		reg=<0x68>;
++		status = "disabled";
++	};
++};
++
++&iomuxc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_hog_1>;
++
++	pinctrl_hog_1: hoggrp-1 {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x59 /* PMIC VSELECT */
++			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x59 /* ENET1_RESET_B */
++			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x59 /* ENET1_INT_B */
++		>;
++	};
++
++	pinctrl_enet1: enet1grp {
++		fsl,pins = <
++			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x7
++			MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x7
++			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x5
++			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x5
++			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x5
++			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x5
++			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x5
++			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x5
++			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x5
++			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x5
++			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x5
++			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x5
++			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x5
++			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x5
++		>;
++	};
++
++	pinctrl_i2c1: i2c1grp {
++		fsl,pins = <
++			MX7D_PAD_I2C1_SDA__I2C1_SDA	0x4000007f
++			MX7D_PAD_I2C1_SCL__I2C1_SCL	0x4000007f
++		>;
++	};
++
++	pinctrl_usdhc3: usdhc3grp {
++		fsl,pins = <
++			MX7D_PAD_SD3_CMD__SD3_CMD	0x5d
++			MX7D_PAD_SD3_CLK__SD3_CLK	0x1d
++			MX7D_PAD_SD3_DATA0__SD3_DATA0	0x5d
++			MX7D_PAD_SD3_DATA1__SD3_DATA1	0x5d
++			MX7D_PAD_SD3_DATA2__SD3_DATA2	0x5d
++			MX7D_PAD_SD3_DATA3__SD3_DATA3	0x5d
++			MX7D_PAD_SD3_DATA4__SD3_DATA4	0x5d
++			MX7D_PAD_SD3_DATA5__SD3_DATA5	0x5d
++			MX7D_PAD_SD3_DATA6__SD3_DATA6	0x5d
++			MX7D_PAD_SD3_DATA7__SD3_DATA7	0x5d
++		>;
++	};
++
++	pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
++		fsl,pins = <
++			MX7D_PAD_SD3_CMD__SD3_CMD	0x5e
++			MX7D_PAD_SD3_CLK__SD3_CLK	0x1e
++			MX7D_PAD_SD3_DATA0__SD3_DATA0	0x5e
++			MX7D_PAD_SD3_DATA1__SD3_DATA1	0x5e
++			MX7D_PAD_SD3_DATA2__SD3_DATA2	0x5e
++			MX7D_PAD_SD3_DATA3__SD3_DATA3	0x5e
++			MX7D_PAD_SD3_DATA4__SD3_DATA4	0x5e
++			MX7D_PAD_SD3_DATA5__SD3_DATA5	0x5e
++			MX7D_PAD_SD3_DATA6__SD3_DATA6	0x5e
++			MX7D_PAD_SD3_DATA7__SD3_DATA7	0x5e
++		>;
++	};
++
++	pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
++		fsl,pins = <
++			MX7D_PAD_SD3_CMD__SD3_CMD	0x5f
++			MX7D_PAD_SD3_CLK__SD3_CLK	0x1f
++			MX7D_PAD_SD3_DATA0__SD3_DATA0	0x5f
++			MX7D_PAD_SD3_DATA1__SD3_DATA1	0x5f
++			MX7D_PAD_SD3_DATA2__SD3_DATA2	0x5f
++			MX7D_PAD_SD3_DATA3__SD3_DATA3	0x5f
++			MX7D_PAD_SD3_DATA4__SD3_DATA4	0x5f
++			MX7D_PAD_SD3_DATA5__SD3_DATA5	0x5f
++			MX7D_PAD_SD3_DATA6__SD3_DATA6	0x5f
++			MX7D_PAD_SD3_DATA7__SD3_DATA7	0x5f
++		>;
++	};
++
++	pinctrl_qspi1_1: qspi1grp_1 {
++		fsl,pins = <
++			MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0	0x51
++			MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1	0x51
++			MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2	0x51
++			MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3	0x51
++			MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK	0x51
++			MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B	0x51
++		>;
++	};
++};
++
++&sdma {
++	status = "okay";
++};
++
++&fec1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pinctrl_enet1>;
++	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
++			<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
++	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
++	assigned-clock-rates = <0>, <100000000>;
++	phy-mode = "rgmii";
++	phy-handle = <&ethphy0>;
++	fsl,magic-packet;
++	phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
++	status = "disabled";
++
++	mdio: mdio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		/*ETH1 PHY on SOM, 25MHz crystal */
++		ethphy0: ethernet-phy@1 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			interrupt-parent = <&gpio2>;
++			interrupts = <29 0>;
++			reg = <1>;
++		};
++	};
++};
++
++&usdhc3 {
++	pinctrl-names = "default", "state_100mhz", "state_200mhz";
++	pinctrl-0 = <&pinctrl_usdhc3>;
++	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
++	assigned-clock-rates = <400000000>;
++	bus-width = <8>;
++	tuning-step = <2>;
++	non-removable;
++	status = "disabled";
++};
+diff --git a/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h
+new file mode 100644
+index 000000000000..378694ee05c2
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-pinfunc-lpsr.h
+@@ -0,0 +1,76 @@
++/*
++ * Copyright (C) 2016 Freescale Semiconductor, Inc.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ */
++
++#ifndef __DTS_IMX7D_PINFUNC_LPSR_H
++#define __DTS_IMX7D_PINFUNC_LPSR_H
++
++/*
++ * The pin function ID is a tuple of
++ * <mux_reg conf_reg input_reg mux_mode input_val>
++ *
++ * NOTE: imx7d-lpsr pin groups should be put under &iomuxc_lpsr node when used
++ */
++
++#define MX7D_PAD_GPIO1_IO00__GPIO1_IO0				  0x0000 0x0030 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO00__PWM4_OUT				  0x0000 0x0030 0x0000 0x1 0x0
++#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_ANY			  0x0000 0x0030 0x0000 0x2 0x0
++#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B			  0x0000 0x0030 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO00__WDOD1_WDOG__RST_B_DEB		  0x0000 0x0030 0x0000 0x4 0x0
++#define MX7D_PAD_GPIO1_IO01__GPIO1_IO1				  0x0004 0x0034 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO01__PWM1_OUT				  0x0004 0x0034 0x0000 0x1 0x0
++#define MX7D_PAD_GPIO1_IO01__CCM_ENET_REF_CLK3			  0x0004 0x0034 0x0000 0x2 0x0
++#define MX7D_PAD_GPIO1_IO01__SAI1_MCLK				  0x0004 0x0034 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO01__ANATOP_24M_OUT			  0x0004 0x0034 0x0000 0x4 0x0
++#define MX7D_PAD_GPIO1_IO01__OBSERVE0_OUT			  0x0004 0x0034 0x0000 0x6 0x0
++#define MX7D_PAD_GPIO1_IO02__GPIO1_IO2				  0x0008 0x0038 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO02__PWM2_OUT				  0x0008 0x0038 0x0000 0x1 0x0
++#define MX7D_PAD_GPIO1_IO02__CCM_ENET_REF_CLK1			  0x0008 0x0038 0x0564 0x2 0x3
++#define MX7D_PAD_GPIO1_IO02__SAI2_MCLK				  0x0008 0x0038 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO02__CCM_CLKO1				  0x0008 0x0038 0x0000 0x5 0x0
++#define MX7D_PAD_GPIO1_IO02__OBSERVE1_OUT			  0x0008 0x0038 0x0000 0x6 0x0
++#define MX7D_PAD_GPIO1_IO02__USB_OTG1_ID			  0x0008 0x0038 0x0734 0x7 0x3
++#define MX7D_PAD_GPIO1_IO03__GPIO1_IO3				  0x000C 0x003C 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO03__PWM3_OUT				  0x000C 0x003C 0x0000 0x1 0x0
++#define MX7D_PAD_GPIO1_IO03__CCM_ENET_REF_CLK2			  0x000C 0x003C 0x0570 0x2 0x3
++#define MX7D_PAD_GPIO1_IO03__SAI3_MCLK				  0x000C 0x003C 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO03__CCM_CLKO2				  0x000C 0x003C 0x0000 0x5 0x0
++#define MX7D_PAD_GPIO1_IO03__OBSERVE2_OUT			  0x000C 0x003C 0x0000 0x6 0x0
++#define MX7D_PAD_GPIO1_IO03__USB_OTG2_ID			  0x000C 0x003C 0x0730 0x7 0x3
++#define MX7D_PAD_GPIO1_IO04__GPIO1_IO4				  0x0010 0x0040 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO04__USB_OTG1_OC			  0x0010 0x0040 0x072C 0x1 0x1
++#define MX7D_PAD_GPIO1_IO04__FLEXTIMER1_CH4			  0x0010 0x0040 0x0594 0x2 0x1
++#define MX7D_PAD_GPIO1_IO04__UART5_DCE_CTS			  0x0010 0x0040 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO04__UART5_DTE_RTS			  0x0010 0x0040 0x0710 0x3 0x4
++#define MX7D_PAD_GPIO1_IO04__I2C1_SCL				  0x0010 0x0040 0x05D4 0x4 0x2
++#define MX7D_PAD_GPIO1_IO04__OBSERVE3_OUT			  0x0010 0x0040 0x0000 0x6 0x0
++#define MX7D_PAD_GPIO1_IO05__GPIO1_IO5				  0x0014 0x0044 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR			  0x0014 0x0044 0x0000 0x1 0x0
++#define MX7D_PAD_GPIO1_IO05__FLEXTIMER1_CH5			  0x0014 0x0044 0x0598 0x2 0x1
++#define MX7D_PAD_GPIO1_IO05__UART5_DCE_RTS			  0x0014 0x0044 0x0710 0x3 0x5
++#define MX7D_PAD_GPIO1_IO05__UART5_DTE_CTS			  0x0014 0x0044 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO05__I2C1_SDA				  0x0014 0x0044 0x05D8 0x4 0x2
++#define MX7D_PAD_GPIO1_IO05__OBSERVE4_OUT			  0x0014 0x0044 0x0000 0x6 0x0
++#define MX7D_PAD_GPIO1_IO06__GPIO1_IO6				  0x0018 0x0048 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO06__USB_OTG2_OC			  0x0018 0x0048 0x0728 0x1 0x1
++#define MX7D_PAD_GPIO1_IO06__FLEXTIMER1_CH6			  0x0018 0x0048 0x059C 0x2 0x1
++#define MX7D_PAD_GPIO1_IO06__UART5_DCE_RX			  0x0018 0x0048 0x0714 0x3 0x4
++#define MX7D_PAD_GPIO1_IO06__UART5_DTE_TX			  0x0018 0x0048 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO06__I2C2_SCL				  0x0018 0x0048 0x05DC 0x4 0x2
++#define MX7D_PAD_GPIO1_IO06__CCM_WAIT				  0x0018 0x0048 0x0000 0x5 0x0
++#define MX7D_PAD_GPIO1_IO06__KPP_ROW4				  0x0018 0x0048 0x0624 0x6 0x1
++#define MX7D_PAD_GPIO1_IO07__GPIO1_IO7				  0x001C 0x004C 0x0000 0x0 0x0
++#define MX7D_PAD_GPIO1_IO07__USB_OTG2_PWR			  0x001C 0x004C 0x0000 0x1 0x0
++#define MX7D_PAD_GPIO1_IO07__FLEXTIMER1_CH7			  0x001C 0x004C 0x05A0 0x2 0x1
++#define MX7D_PAD_GPIO1_IO07__UART5_DCE_TX			  0x001C 0x004C 0x0000 0x3 0x0
++#define MX7D_PAD_GPIO1_IO07__UART5_DTE_RX			  0x001C 0x004C 0x0714 0x3 0x5
++#define MX7D_PAD_GPIO1_IO07__I2C2_SDA				  0x001C 0x004C 0x05E0 0x4 0x2
++#define MX7D_PAD_GPIO1_IO07__CCM_STOP				  0x001C 0x004C 0x0000 0x5 0x0
++#define MX7D_PAD_GPIO1_IO07__KPP_COL4				  0x001C 0x004C 0x0604 0x6 0x1
++
++#endif /* __DTS_IMX7D_PINFUNC_LPSR_H */
+diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
+index 9aa2bb998552..05b949806533 100644
+--- a/arch/arm/boot/dts/imx7s.dtsi
++++ b/arch/arm/boot/dts/imx7s.dtsi
+@@ -47,6 +47,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include "imx7d-pinfunc.h"
++#include "imx7d-pinfunc-lpsr.h"
+ 
+ / {
+ 	#address-cells = <1>;
diff --git a/patches/linux-4.16/0002-ARM-dts-imx7s-add-rproc-node.patch b/patches/linux-4.16/0002-ARM-dts-imx7s-add-rproc-node.patch
new file mode 100644
index 0000000..d5c0b67
--- /dev/null
+++ b/patches/linux-4.16/0002-ARM-dts-imx7s-add-rproc-node.patch
@@ -0,0 +1,79 @@
+From: Oleksij Rempel <linux@rempel-privat.de>
+Date: Wed, 14 Jun 2017 22:10:16 +0200
+Subject: [PATCH] ARM: dts: imx7s: add rproc node
+
+Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
+---
+ arch/arm/boot/dts/imx7d-phyboard-zeta.dts | 34 ++++++++++++++++++++++++++-----
+ arch/arm/boot/dts/imx7s.dtsi              |  6 ++++++
+ 2 files changed, 35 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm/boot/dts/imx7d-phyboard-zeta.dts b/arch/arm/boot/dts/imx7d-phyboard-zeta.dts
+index 16cf12244f16..95dd5631a2af 100644
+--- a/arch/arm/boot/dts/imx7d-phyboard-zeta.dts
++++ b/arch/arm/boot/dts/imx7d-phyboard-zeta.dts
+@@ -27,6 +27,34 @@
+ 		device_type = "memory";
+ 		reg = <0x80000000 0x40000000>;
+ 	};
++
++	reserved-memory {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++
++		m4_reserved_sysmem1: rproc@88000000 {
++			reg = <0x88000000 0x4000000>;
++			no-map;
++		};
++
++		/* not really needed node. used as example */
++		m4_reserved_sysmem2: rproc@88080000 {
++			reg = <0x8c000000 0x80000>;
++			no-map;
++		};
++	};
++};
++
++&imx_rproc {
++	status = "okay";
++	memory-region = <&m4_reserved_sysmem1>,
++			<&m4_reserved_sysmem2>;
++
++	/* clocks for HW used by M4: uart1, gpt  */
++	remote-clocks = <&clks IMX7D_UART1_ROOT_CLK>,
++			<&clks IMX7D_GPT2_ROOT_CLK>;
++	remote-clock-rates = <240000000>, <24000000>;
+ };
+ 
+ /**** SOM - PCM-061 ****/
+@@ -135,10 +163,6 @@
+ 	status = "okay";
+ };
+ 
+-&uart1 {
+-	status = "okay";
+-};
+-
+ &uart2 {
+ 	status = "okay";
+-};
+\ No newline at end of file
++};
+diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
+index 05b949806533..d25fcb5aee04 100644
+--- a/arch/arm/boot/dts/imx7s.dtsi
++++ b/arch/arm/boot/dts/imx7s.dtsi
+@@ -184,6 +184,12 @@
+ 		interrupt-parent = <&gpc>;
+ 		ranges;
+ 
++		imx_rproc: imx7d-rp0@0 {
++			compatible	= "fsl,imx7d-cm4";
++			syscon		= <&src>;
++			clocks		= <&clks IMX7D_ARM_M4_ROOT_CLK>;
++		};
++
+ 		funnel@30041000 {
+ 			compatible = "arm,coresight-funnel", "arm,primecell";
+ 			reg = <0x30041000 0x1000>;
diff --git a/patches/linux-4.16/0003-ARM-imx-add-imx7d-m4.patch b/patches/linux-4.16/0003-ARM-imx-add-imx7d-m4.patch
new file mode 100644
index 0000000..a912a8c
--- /dev/null
+++ b/patches/linux-4.16/0003-ARM-imx-add-imx7d-m4.patch
@@ -0,0 +1,150 @@
+From: Oleksij Rempel <linux@rempel-privat.de>
+Date: Thu, 31 Aug 2017 12:45:43 +0200
+Subject: [PATCH] ARM: imx: add imx7d-m4
+
+Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
+---
+ arch/arm/Kconfig-nommu            |  2 ++
+ arch/arm/boot/dts/Makefile        |  2 +-
+ arch/arm/include/debug/imx-uart.h |  2 ++
+ arch/arm/mach-imx/Kconfig         | 33 +++++++++++++++++++++------------
+ arch/arm/mach-imx/Makefile        |  3 ++-
+ arch/arm/mach-imx/mach-imx7d-m4.c | 21 +++++++++++++++++++++
+ 6 files changed, 49 insertions(+), 14 deletions(-)
+ create mode 100644 arch/arm/mach-imx/mach-imx7d-m4.c
+
+diff --git a/arch/arm/Kconfig-nommu b/arch/arm/Kconfig-nommu
+index 1168a03c8525..aced2bf585e8 100644
+--- a/arch/arm/Kconfig-nommu
++++ b/arch/arm/Kconfig-nommu
+@@ -12,10 +12,12 @@ config SET_MEM_PARAM
+ 
+ config DRAM_BASE
+ 	hex '(S)DRAM Base Address' if SET_MEM_PARAM
++	default 0x18000000 if SOC_IMX7D_M4
+ 	default 0x00800000
+ 
+ config DRAM_SIZE
+ 	hex '(S)DRAM SIZE' if SET_MEM_PARAM
++	default 0x04000000 if SOC_IMX7D_M4
+ 	default 0x00800000
+ 
+ config FLASH_MEM_BASE
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index 721327ad7400..d8f9d38c8059 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -527,7 +527,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
+ 	imx6ul-tx6ul-0011.dtb \
+ 	imx6ul-tx6ul-mainboard.dtb \
+ 	imx6ull-14x14-evk.dtb
+-dtb-$(CONFIG_SOC_IMX7D) += \
++dtb-$(CONFIG_SOC_IMX7D_A7) += \
+ 	imx7d-cl-som-imx7.dtb \
+ 	imx7d-colibri-emmc-eval-v3.dtb \
+ 	imx7d-colibri-eval-v3.dtb \
+diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
+index bce58e975ad1..efe0acdf5c5a 100644
+--- a/arch/arm/include/debug/imx-uart.h
++++ b/arch/arm/include/debug/imx-uart.h
+@@ -111,6 +111,8 @@
+ #define IMX7D_UART_BASE_ADDR(n) IMX7D_UART##n##_BASE_ADDR
+ #define IMX7D_UART_BASE(n)	IMX7D_UART_BASE_ADDR(n)
+ 
++#define IMX7D_M4_UART_BASE(n)		IMX7D_A7_UART_BASE_ADDR(n)
++
+ #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
+ 
+ #ifdef CONFIG_DEBUG_IMX1_UART
+diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
+index 782699e67600..c63065672d1c 100644
+--- a/arch/arm/mach-imx/Kconfig
++++ b/arch/arm/mach-imx/Kconfig
+@@ -528,18 +528,6 @@ config SOC_IMX6UL
+ 	help
+ 	  This enables support for Freescale i.MX6 UltraLite processor.
+ 
+-config SOC_IMX7D
+-	bool "i.MX7 Dual support"
+-	select PINCTRL_IMX7D
+-	select ARM_GIC
+-	select HAVE_ARM_ARCH_TIMER
+-	select HAVE_IMX_ANATOP
+-	select HAVE_IMX_MMDC
+-	select HAVE_IMX_SRC
+-	select IMX_GPCV2
+-	help
+-		This enables support for Freescale i.MX7 Dual processor.
+-
+ config SOC_LS1021A
+ 	bool "Freescale LS1021A support"
+ 	select ARM_GIC
+@@ -554,6 +542,27 @@ comment "Cortex-A/Cortex-M asymmetric multiprocessing platforms"
+ 
+ if ARCH_MULTI_V7 || ARM_SINGLE_ARMV7M
+ 
++config SOC_IMX7D_A7
++	bool
++	select ARM_GIC
++	select HAVE_ARM_ARCH_TIMER
++	select HAVE_IMX_ANATOP
++	select HAVE_IMX_MMDC
++	select HAVE_IMX_SRC
++	select IMX_GPCV2
++
++config SOC_IMX7D_M4
++	bool
++	select ARMV7M_SYSTICK
++
++config SOC_IMX7D
++	bool "i.MX7 Dual support"
++	select PINCTRL_IMX7D
++	select SOC_IMX7D_A7 if ARCH_MULTI_V7
++	select SOC_IMX7D_M4 if ARM_SINGLE_ARMV7M
++	help
++		This enables support for Freescale i.MX7 Dual processor.
++
+ config SOC_VF610
+ 	bool "Vybrid Family VF610 support"
+ 	select ARM_GIC if ARCH_MULTI_V7
+diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
+index 8ff71058207d..baef499c3274 100644
+--- a/arch/arm/mach-imx/Makefile
++++ b/arch/arm/mach-imx/Makefile
+@@ -80,7 +80,8 @@ obj-$(CONFIG_SOC_IMX6Q) += mach-imx6q.o
+ obj-$(CONFIG_SOC_IMX6SL) += mach-imx6sl.o
+ obj-$(CONFIG_SOC_IMX6SX) += mach-imx6sx.o
+ obj-$(CONFIG_SOC_IMX6UL) += mach-imx6ul.o
+-obj-$(CONFIG_SOC_IMX7D) += mach-imx7d.o
++obj-$(CONFIG_SOC_IMX7D_A7) += mach-imx7d.o
++obj-$(CONFIG_SOC_IMX7D_M4) += mach-imx7d-m4.o
+ 
+ ifeq ($(CONFIG_SUSPEND),y)
+ AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
+diff --git a/arch/arm/mach-imx/mach-imx7d-m4.c b/arch/arm/mach-imx/mach-imx7d-m4.c
+new file mode 100644
+index 000000000000..f9520a37db1a
+--- /dev/null
++++ b/arch/arm/mach-imx/mach-imx7d-m4.c
+@@ -0,0 +1,21 @@
++/*
++ * Copyright 2017 Pengutronix
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/kernel.h>
++#include <asm/v7m.h>
++#include <asm/mach/arch.h>
++
++static const char * const imx7d_m4_dt_compat[] __initconst = {
++	"fsl,imx7d-m4",
++	NULL,
++};
++
++DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual Cortex-M4 (Device Tree)")
++	.dt_compat = imx7d_m4_dt_compat,
++	.restart = armv7m_restart,
++MACHINE_END
diff --git a/patches/linux-4.16/0004-add-imx7d-m4.dtsi.patch b/patches/linux-4.16/0004-add-imx7d-m4.dtsi.patch
new file mode 100644
index 0000000..58dcdd3
--- /dev/null
+++ b/patches/linux-4.16/0004-add-imx7d-m4.dtsi.patch
@@ -0,0 +1,119 @@
+From: Oleksij Rempel <linux@rempel-privat.de>
+Date: Thu, 31 Aug 2017 11:52:20 +0200
+Subject: [PATCH] add imx7d-m4.dtsi
+
+Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
+---
+ arch/arm/boot/dts/imx7d-m4.dtsi | 103 ++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 103 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx7d-m4.dtsi
+
+diff --git a/arch/arm/boot/dts/imx7d-m4.dtsi b/arch/arm/boot/dts/imx7d-m4.dtsi
+new file mode 100644
+index 000000000000..2cee3cb8b5ab
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-m4.dtsi
+@@ -0,0 +1,103 @@
++/*
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ * Copyright 2016 Toradex AG
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <dt-bindings/clock/imx7d-clock.h>
++#include <dt-bindings/power/imx7-power.h>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include "imx7d-pinfunc.h"
++#include "imx7d-pinfunc-lpsr.h"
++#include "armv7-m.dtsi"
++
++/ {
++	#address-cells = <1>;
++	#size-cells = <1>;
++	chosen {};
++	memory { device_type = "memory"; reg = <0 0>; };
++
++	aliases {
++		serial0 = &uart1;
++	};
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu0: cpu@0 {
++			compatible = "arm,cortex-m4";
++			device_type = "cpu";
++			reg = <0>;
++		};
++	};
++
++	soc {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "simple-bus";
++		ranges;
++
++		aips3: aips-bus@30800000 {
++			compatible = "fsl,aips-bus", "simple-bus";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			reg = <0x30800000 0x400000>;
++			ranges;
++
++			gpt2: gpt@302e0000 {
++				compatible = "fsl,imx7d-m4-gpt", "fsl,imx6sx-gpt";
++				interrupts = <54>;
++				reg = <0x302e0000 0x10000>;
++				status = "disabled";
++			};
++
++			uart1: serial@30860000 {
++				compatible = "fsl,imx6q-uart", "fsl,imx7d-m4-uart";
++				interrupts = <26>;
++				reg = <0x30860000 0x10000>;
++				status = "disabled";
++			};
++
++		};
++	};
++};
diff --git a/patches/linux-4.16/0005-add-imx7d-m4-phyboard-zeta.dts.patch b/patches/linux-4.16/0005-add-imx7d-m4-phyboard-zeta.dts.patch
new file mode 100644
index 0000000..757e48b
--- /dev/null
+++ b/patches/linux-4.16/0005-add-imx7d-m4-phyboard-zeta.dts.patch
@@ -0,0 +1,84 @@
+From: Oleksij Rempel <linux@rempel-privat.de>
+Date: Fri, 1 Sep 2017 11:30:11 +0200
+Subject: [PATCH] add imx7d-m4-phyboard-zeta.dts
+
+Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
+---
+ arch/arm/boot/dts/Makefile                   |  2 ++
+ arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts | 54 ++++++++++++++++++++++++++++
+ 2 files changed, 56 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts
+
+diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
+index d8f9d38c8059..c44b0afdf46e 100644
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -539,6 +539,8 @@ dtb-$(CONFIG_SOC_IMX7D_A7) += \
+ 	imx7d-sdb-sht11.dtb \
+ 	imx7s-colibri-eval-v3.dtb \
+ 	imx7s-warp.dtb
++dtb-$(CONFIG_SOC_IMX7D_M4) += \
++	imx7d-m4-phyboard-zeta.dtb
+ dtb-$(CONFIG_SOC_LS1021A) += \
+ 	ls1021a-moxa-uc-8410a.dtb \
+ 	ls1021a-qds.dtb \
+diff --git a/arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts b/arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts
+new file mode 100644
+index 000000000000..f11b257ce758
+--- /dev/null
++++ b/arch/arm/boot/dts/imx7d-m4-phyboard-zeta.dts
+@@ -0,0 +1,54 @@
++/*
++ * Copyright (C) 2015 PHYTEC America, LLC
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++/dts-v1/;
++
++#include "imx7d-m4.dtsi"
++
++/ {
++	model = "Phytec i.MX7D Cortex M4 phyCORE";
++	compatible = "fsl,imx7d-m4";
++
++	chosen {
++		stdout-path = &uart1;
++	};
++
++	memory {
++		device_type = "memory";
++		reg = <0x18000000 0x04000000>;
++	};
++
++	clk24m: clk24m {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24000000>;
++		clock-output-names = "clk24m";
++	};
++
++	clk240m: clk240m {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency = <240000000>;
++		clock-output-names = "clk240m";
++	};
++};
++
++&cpu0 {
++	clocks = <&clk240m>;
++};
++
++&gpt2 {
++	clocks = <&clk24m>, <&clk24m>;
++	clock-names = "ipg", "per";
++	status = "okay";
++};
++
++&uart1 {
++	clocks = <&clk24m>, <&clk24m>;
++	clock-names = "ipg", "per";
++	status = "okay";
++};
diff --git a/patches/linux-4.16/0006-HACK-remoteproc-imx_rproc-assign-clock-for-other-dev.patch b/patches/linux-4.16/0006-HACK-remoteproc-imx_rproc-assign-clock-for-other-dev.patch
new file mode 100644
index 0000000..670c29f
--- /dev/null
+++ b/patches/linux-4.16/0006-HACK-remoteproc-imx_rproc-assign-clock-for-other-dev.patch
@@ -0,0 +1,162 @@
+From: Oleksij Rempel <linux@rempel-privat.de>
+Date: Fri, 1 Sep 2017 11:36:42 +0200
+Subject: [PATCH] HACK: remoteproc: imx_rproc: assign clock for other devices
+
+Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
+---
+ drivers/remoteproc/imx_rproc.c | 114 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 114 insertions(+)
+
+diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
+index 633268e9d550..b9e52ac6e0c5 100644
+--- a/drivers/remoteproc/imx_rproc.c
++++ b/drivers/remoteproc/imx_rproc.c
+@@ -47,6 +47,7 @@
+ 					 | IMX6SX_SW_M4C_RST)
+ 
+ #define IMX7D_RPROC_MEM_MAX		8
++#define IMX7D_RPROC_RCLKS_MAX		8
+ 
+ /**
+  * struct imx_rproc_mem - slim internal memory structure
+@@ -88,6 +89,7 @@ struct imx_rproc {
+ 	const struct imx_rproc_dcfg	*dcfg;
+ 	struct imx_rproc_mem		mem[IMX7D_RPROC_MEM_MAX];
+ 	struct clk			*clk;
++	struct clk			*rclk[IMX7D_RPROC_RCLKS_MAX];
+ };
+ 
+ static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
+@@ -165,6 +167,9 @@ static int imx_rproc_start(struct rproc *rproc)
+ 	struct device *dev = priv->dev;
+ 	int ret;
+ 
++
++	ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
++				 dcfg->src_mask, dcfg->src_stop);
+ 	ret = regmap_update_bits(priv->regmap, dcfg->src_reg,
+ 				 dcfg->src_mask, dcfg->src_start);
+ 	if (ret)
+@@ -249,6 +254,109 @@ static const struct rproc_ops imx_rproc_ops = {
+ 	.da_to_va       = imx_rproc_da_to_va,
+ };
+ 
++static int imx_rproc_set_clk_rates(struct device_node *node, bool clk_supplier)
++{
++	struct of_phandle_args clkspec;
++	struct property	*prop;
++	const __be32 *cur;
++	int rc, index = 0;
++	struct clk *clk;
++	u32 rate;
++
++	of_property_for_each_u32(node, "remote-clock-rates", prop, cur, rate) {
++		if (rate) {
++			rc = of_parse_phandle_with_args(node, "remote-clocks",
++					"#clock-cells",	index, &clkspec);
++			if (rc < 0) {
++				/* skip empty (null) phandles */
++				if (rc == -ENOENT)
++					continue;
++				else
++					return rc;
++			}
++			if (clkspec.np == node && !clk_supplier)
++				return 0;
++
++			clk = of_clk_get_from_provider(&clkspec);
++			if (IS_ERR(clk)) {
++				if (PTR_ERR(clk) != -EPROBE_DEFER)
++					pr_warn("clk: couldn't get clock %d for %s\n",
++						index, node->full_name);
++				return PTR_ERR(clk);
++			}
++
++			rc = clk_set_rate(clk, rate);
++			if (rc < 0)
++				pr_err("clk: couldn't set  clk rate to %u (%d), current rate: %lu\n",
++					rate, rc,
++				       clk_get_rate(clk));
++			clk_put(clk);
++		}
++		index++;
++	}
++	return 0;
++}
++
++static int imx_rproc_set_rclks(struct imx_rproc *priv)
++{
++	struct device *dev = priv->dev;
++	struct device_node *node = dev->of_node;
++	struct of_phandle_args clkspec;
++	int index, rc, ret, num_parents;
++	struct clk *clk, *pclk;
++
++	imx_rproc_set_clk_rates(node, 0);
++	num_parents = of_count_phandle_with_args(node, "remote-clocks",
++						 "#clock-cells");
++	if (num_parents == -EINVAL) {
++		dev_err(dev, "clk: invalid value of remote-clocks property at %s\n",
++		       node->full_name);
++		return -EINVAL;
++	}
++
++	if (IMX7D_RPROC_RCLKS_MAX < num_parents) {
++		dev_err(dev, "unsupported count of remote clocks: %i, max: %i\n",
++			 num_parents, IMX7D_RPROC_RCLKS_MAX);
++		return -EINVAL;
++	}
++
++	for (index = 0; index < num_parents; index++) {
++		rc = of_parse_phandle_with_args(node, "remote-clocks",
++					"#clock-cells", index, &clkspec);
++		if (rc < 0)
++			goto err;
++
++		if (clkspec.np == node) {
++			rc = 0;
++			goto err;
++		}
++
++		clk = of_clk_get_from_provider(&clkspec);
++		if (IS_ERR(clk)) {
++			if (PTR_ERR(clk) != -EPROBE_DEFER)
++				dev_warn(dev, "clk: couldn't get assigned clock %d for %s\n",
++					index, node->full_name);
++			rc = PTR_ERR(clk);
++			goto err;
++		}
++
++		/*
++		 * clk for M4 block including memory. Should be
++		 * enabled before .start for FW transfer.
++		 */
++		ret = clk_prepare_enable(clk);
++		if (ret) {
++			dev_err(dev, "Failed to enable clock\n");
++			return ret;
++		}
++
++	}
++	return 0;
++err:
++	return rc;
++}
++
++
+ static int imx_rproc_addr_init(struct imx_rproc *priv,
+ 			       struct platform_device *pdev)
+ {
+@@ -374,6 +482,12 @@ static int imx_rproc_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
++	ret = imx_rproc_set_rclks(priv);
++	if (ret) {
++		dev_err(dev, "filed on imx_rproc_set_rclks\n");
++		goto err_put_rproc;
++	}
++
+ 	ret = rproc_add(rproc);
+ 	if (ret) {
+ 		dev_err(dev, "rproc_add failed\n");
diff --git a/patches/linux-4.16/0007-HACK-rproc-add-address-for-0x10016.patch b/patches/linux-4.16/0007-HACK-rproc-add-address-for-0x10016.patch
new file mode 100644
index 0000000..f995912
--- /dev/null
+++ b/patches/linux-4.16/0007-HACK-rproc-add-address-for-0x10016.patch
@@ -0,0 +1,21 @@
+From: Oleksij Rempel <o.rempel@pengutronix.de>
+Date: Wed, 28 Mar 2018 08:48:54 +0200
+Subject: [PATCH] HACK: rproc: add address for 0x10016
+
+Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
+---
+ drivers/remoteproc/imx_rproc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
+index b9e52ac6e0c5..9d692d686123 100644
+--- a/drivers/remoteproc/imx_rproc.c
++++ b/drivers/remoteproc/imx_rproc.c
+@@ -110,6 +110,7 @@ static const struct imx_rproc_att imx_rproc_att_imx7d[] = {
+ 	{ 0x10000000, 0x80000000, 0x0FFF0000, 0 },
+ 
+ 	/* TCMU (Data) */
++	{ 0x00010016, 0x00800000, 0x00008000, ATT_OWN },
+ 	{ 0x20000000, 0x00800000, 0x00008000, ATT_OWN },
+ 	/* OCRAM (Data) */
+ 	{ 0x20200000, 0x00900000, 0x00020000, 0 },
diff --git a/patches/linux-4.16/series b/patches/linux-4.16/series
new file mode 100644
index 0000000..3174a39
--- /dev/null
+++ b/patches/linux-4.16/series
@@ -0,0 +1,10 @@
+# generated by git-ptx-patches
+#tag:base --start-number 1
+0001-ARM-dts-imx7d-add-imx7d-phyboard-zeta.patch
+0002-ARM-dts-imx7s-add-rproc-node.patch
+0003-ARM-imx-add-imx7d-m4.patch
+0004-add-imx7d-m4.dtsi.patch
+0005-add-imx7d-m4-phyboard-zeta.dts.patch
+0006-HACK-remoteproc-imx_rproc-assign-clock-for-other-dev.patch
+0007-HACK-rproc-add-address-for-0x10016.patch
+# 38b6db2789587f5817da7ec11acaf01e  - git-ptx-patches magic