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| author | Michael Grzeschik <m.grzeschik@pengutronix.de> | 2013-11-20 12:49:01 +0100 |
|---|---|---|
| committer | Michael Grzeschik <m.grzeschik@pengutronix.de> | 2013-11-21 15:28:31 +0100 |
| commit | 09c0238f1dc3f411ee3e81d1731eea314918db49 (patch) | |
| tree | bec09db0ddc900e161cdc8471202c14aa9e7c0f0 | |
| parent | ade8e4e8f3ebd7c47cb8cadc44c6412ad58b3c00 (diff) | |
| download | platform-pengutronix-beaglebone-09c0238f1dc3f411ee3e81d1731eea314918db49.tar.gz platform-pengutronix-beaglebone-09c0238f1dc3f411ee3e81d1731eea314918db49.tar.xz | |
barebox: update to barebox-2013.11.0
Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de>
22 files changed, 45 insertions, 2308 deletions
diff --git a/barebox-defaultenv/config b/barebox-defaultenv/config index 678e1ad..fbfa7d5 100644 --- a/barebox-defaultenv/config +++ b/barebox-defaultenv/config @@ -3,6 +3,9 @@ # change network settings in /env/network/eth0 # change mtd partition settings and automountpoints in /env/init/* +# set to false if you do not want to have colors +global.allow_color=true + # user (used for network filenames) global.user=none @@ -11,4 +14,6 @@ global.autoboot_timeout=3 # default boot entry (one of /env/boot/*) global.boot.default=sd -global.linux.bootargs.base="console=ttyO0,115200" + +# base bootargs +global.linux.bootargs.base="console=ttyO0,115200n8" diff --git a/barebox.config b/barebox.config index 294bba1..bae9385 100644 --- a/barebox.config +++ b/barebox.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Barebox/arm 2013.07.0 Configuration +# Barebox/arm 2013.11.0 Configuration # CONFIG_ARM=y CONFIG_ARM_LINUX=y @@ -21,6 +21,7 @@ CONFIG_ARM_LINUX=y # CONFIG_ARCH_NOMADIK is not set CONFIG_ARCH_OMAP=y # CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_SOCFPGA is not set # CONFIG_ARCH_S3C24xx is not set # CONFIG_ARCH_S5PCxx is not set # CONFIG_ARCH_S3C64xx is not set @@ -40,7 +41,6 @@ CONFIG_CPU_32v7=y # processor features # # CONFIG_BOOT_ENDIANNESS_SWITCH is not set -CONFIG_BOARDINFO="Texas Instrument's Beagle Bone" CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff # @@ -76,6 +76,7 @@ CONFIG_HAS_MODULES=y CONFIG_CMD_MEMORY=y CONFIG_ENV_HANDLING=y CONFIG_GENERIC_GPIO=y +CONFIG_BOOTM=y CONFIG_BLOCK=y CONFIG_BLOCK_WRITE=y CONFIG_FILETYPE=y @@ -112,6 +113,7 @@ CONFIG_MALLOC_SIZE=0x1000000 CONFIG_MALLOC_TLSF=y CONFIG_KALLSYMS=y # CONFIG_RELOCATABLE is not set +# CONFIG_PANIC_HANG is not set CONFIG_PROMPT="barebox> " CONFIG_BAUDRATE=115200 CONFIG_LONGHELP=y @@ -132,6 +134,8 @@ CONFIG_MENU=y CONFIG_DYNAMIC_CRC_TABLE=y CONFIG_ERRNO_MESSAGES=y # CONFIG_TIMESTAMP is not set +# CONFIG_BLSPEC is not set +# CONFIG_KERNEL_INSTALL_TARGET is not set CONFIG_CONSOLE_FULL=y # CONFIG_CONSOLE_SIMPLE is not set # CONFIG_CONSOLE_NONE is not set @@ -154,11 +158,10 @@ CONFIG_BAREBOXENV_TARGET=y # Debugging # CONFIG_COMPILE_LOGLEVEL=6 +CONFIG_DEFAULT_LOGLEVEL=7 CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_FLASH_NOISE is not set -# CONFIG_ENABLE_PARTITION_NOISE is not set -# CONFIG_ENABLE_DEVICE_NOISE is not set # CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_INITCALLS is not set CONFIG_HAS_DEBUG_LL=y CONFIG_COMMAND_SUPPORT=y # CONFIG_HAS_POWEROFF is not set @@ -257,6 +260,7 @@ CONFIG_CMD_UIMAGE=y # CONFIG_CMD_BOOTZ is not set CONFIG_CMD_BOOTU=y CONFIG_FLEXIBLE_BOOTARGS=y +CONFIG_CMD_BOOT=y CONFIG_CMD_RESET=y CONFIG_CMD_GO=y CONFIG_CMD_OFTREE=y @@ -266,7 +270,7 @@ CONFIG_CMD_OFTREE=y # # testing # -# CONFIG_CMD_MTEST is not set +# CONFIG_CMD_MEMTEST is not set # # video command @@ -300,6 +304,7 @@ CONFIG_OFTREE_MEM_GENERIC=y CONFIG_DTC=y CONFIG_OFDEVICE=y CONFIG_OF_NET=y +# CONFIG_OF_BAREBOX_DRIVERS is not set # # serial drivers @@ -328,6 +333,7 @@ CONFIG_DRIVER_NET_CPSW=y # CONFIG_DRIVER_NET_SMC911X is not set # CONFIG_DRIVER_NET_SMC91111 is not set # CONFIG_DRIVER_NET_KS8851_MLL is not set +# CONFIG_DRIVER_NET_DESIGNWARE is not set # # SPI drivers @@ -369,6 +375,7 @@ CONFIG_MCI_WRITE=y # # --- MCI host drivers --- # +# CONFIG_MCI_DW is not set CONFIG_MCI_OMAP_HSMMC=y # @@ -377,7 +384,6 @@ CONFIG_MCI_OMAP_HSMMC=y # CONFIG_MFD_LP3972 is not set # CONFIG_MFD_MC13XXX is not set # CONFIG_MFD_MC34704 is not set -# CONFIG_MFD_MC34708 is not set # CONFIG_MFD_MC9SDZ60 is not set # CONFIG_MFD_STMPE is not set # CONFIG_MFD_SYSCON is not set @@ -409,6 +415,7 @@ CONFIG_GPIOLIB=y # # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_IMX is not set +# CONFIG_GPIO_DESIGNWARE is not set # CONFIG_W1 is not set # @@ -421,6 +428,10 @@ CONFIG_GPIOLIB=y # CONFIG_PINCTRL_TEGRA20 is not set # +# Bus devices +# + +# # Filesystem support # CONFIG_FS=y @@ -434,6 +445,8 @@ CONFIG_FS_NFS=y CONFIG_FS_FAT=y CONFIG_FS_FAT_WRITE=y CONFIG_FS_FAT_LFN=y +# CONFIG_FS_BPKFS is not set +# CONFIG_FS_UIMAGEFS is not set # # Library routines @@ -442,6 +455,7 @@ CONFIG_PARAMETER=y CONFIG_UNCOMPRESS=y # CONFIG_ZLIB is not set # CONFIG_BZLIB is not set +# CONFIG_LZ4_DECOMPRESS is not set # CONFIG_GENERIC_FIND_NEXT_BIT is not set CONFIG_PROCESS_ESCAPE_SEQUENCE=y # CONFIG_LZO_DECOMPRESS is not set diff --git a/barebox_mlo.config b/barebox_mlo.config index 2d87086..568e206 100644 --- a/barebox_mlo.config +++ b/barebox_mlo.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Barebox/arm 2013.07.0 Configuration +# Barebox/arm 2013.11.0 Configuration # CONFIG_ARM=y @@ -19,6 +19,7 @@ CONFIG_ARM=y # CONFIG_ARCH_NOMADIK is not set CONFIG_ARCH_OMAP=y # CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_SOCFPGA is not set # CONFIG_ARCH_S3C24xx is not set # CONFIG_ARCH_S5PCxx is not set # CONFIG_ARCH_S3C64xx is not set @@ -38,7 +39,6 @@ CONFIG_CPU_32v7=y # processor features # # CONFIG_BOOT_ENDIANNESS_SWITCH is not set -CONFIG_BOARDINFO="Texas Instrument's Beagle Bone" CONFIG_BAREBOX_MAX_IMAGE_SIZE=0xffffffff # @@ -105,6 +105,7 @@ CONFIG_MALLOC_TLSF=y # CONFIG_MALLOC_DUMMY is not set # CONFIG_KALLSYMS is not set # CONFIG_RELOCATABLE is not set +# CONFIG_PANIC_HANG is not set CONFIG_PROMPT="MLO>" CONFIG_BAUDRATE=115200 CONFIG_SIMPLE_READLINE=y @@ -119,6 +120,8 @@ CONFIG_SHELL_NONE=y # CONFIG_PASSWORD is not set # CONFIG_ERRNO_MESSAGES is not set # CONFIG_TIMESTAMP is not set +# CONFIG_BLSPEC is not set +# CONFIG_KERNEL_INSTALL_TARGET is not set CONFIG_CONSOLE_FULL=y # CONFIG_CONSOLE_SIMPLE is not set # CONFIG_CONSOLE_NONE is not set @@ -137,11 +140,10 @@ CONFIG_PARTITION_DISK_DOS=y # Debugging # CONFIG_COMPILE_LOGLEVEL=6 +CONFIG_DEFAULT_LOGLEVEL=7 CONFIG_DEBUG_INFO=y -# CONFIG_ENABLE_FLASH_NOISE is not set -# CONFIG_ENABLE_PARTITION_NOISE is not set -# CONFIG_ENABLE_DEVICE_NOISE is not set # CONFIG_DEBUG_LL is not set +# CONFIG_DEBUG_INITCALLS is not set CONFIG_HAS_DEBUG_LL=y # CONFIG_HAS_POWEROFF is not set # CONFIG_NET is not set @@ -192,6 +194,7 @@ CONFIG_MCI_WRITE=y # # --- MCI host drivers --- # +# CONFIG_MCI_DW is not set CONFIG_MCI_OMAP_HSMMC=y # @@ -222,6 +225,7 @@ CONFIG_GPIOLIB=y # # CONFIG_GPIO_GENERIC_PLATFORM is not set # CONFIG_GPIO_IMX is not set +# CONFIG_GPIO_DESIGNWARE is not set # CONFIG_W1 is not set # @@ -233,6 +237,10 @@ CONFIG_GPIOLIB=y # CONFIG_PINCTRL_TEGRA20 is not set # +# Bus devices +# + +# # Filesystem support # CONFIG_FS=y @@ -243,12 +251,15 @@ CONFIG_FS=y CONFIG_FS_FAT=y # CONFIG_FS_FAT_WRITE is not set CONFIG_FS_FAT_LFN=y +# CONFIG_FS_BPKFS is not set +# CONFIG_FS_UIMAGEFS is not set # # Library routines # # CONFIG_ZLIB is not set # CONFIG_BZLIB is not set +# CONFIG_LZ4_DECOMPRESS is not set # CONFIG_GENERIC_FIND_NEXT_BIT is not set # CONFIG_PROCESS_ESCAPE_SEQUENCE is not set # CONFIG_LZO_DECOMPRESS is not set diff --git a/patches/barebox-2013.07.0/0001-scripts-genenv-remove-empty-files-from-tempdir.patch b/patches/barebox-2013.07.0/0001-scripts-genenv-remove-empty-files-from-tempdir.patch deleted file mode 100644 index 3643c08..0000000 --- a/patches/barebox-2013.07.0/0001-scripts-genenv-remove-empty-files-from-tempdir.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 8544d430c081371152796a0de45fa8edef1bf594 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Tue, 28 May 2013 09:43:29 +0200 -Subject: [PATCH 01/17] scripts: genenv: remove empty files from tempdir - -This allows leaving out default files from the environment by overriding -them with empty files in the board or BSP. - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - scripts/genenv | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/scripts/genenv b/scripts/genenv -index 374db6d..3e91062 100755 ---- a/scripts/genenv -+++ b/scripts/genenv -@@ -24,7 +24,7 @@ for i in $*; do - done - ) - --find $tempdir -name '.svn' -o -name '*~' | xargs --no-run-if-empty rm -r -+find $tempdir -name '.svn' -o -name '*~' -o -size 0 | xargs --no-run-if-empty rm -r - - $objtree/scripts/bareboxenv -s $tempdir $target - --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch b/patches/barebox-2013.07.0/0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch deleted file mode 100644 index b9811ad..0000000 --- a/patches/barebox-2013.07.0/0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch +++ /dev/null @@ -1,30 +0,0 @@ -From cd780d60b41f5b743e7c4518364053a9c266f17d Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Tue, 28 May 2013 11:04:12 +0200 -Subject: [PATCH 02/17] scripts: Makefile: do not use obj-* variables for - userspace tools - -When using obj-?, it erroneously tries to link a built-in.o. Instead -use the extra-? variable. - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - scripts/Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/scripts/Makefile b/scripts/Makefile -index 307dc3d..eaf12d9 100644 ---- a/scripts/Makefile -+++ b/scripts/Makefile -@@ -32,7 +32,7 @@ subdir- += basic kconfig setupmbr - quiet_cmd_csingle = CC $@ - cmd_csingle = $(CC) -Wp,-MD,$(depfile) $(CFLAGS) -o $@ $< - --obj-$(CONFIG_BAREBOXENV_TARGET) += bareboxenv-target -+extra-$(CONFIG_BAREBOXENV_TARGET) += bareboxenv-target - - scripts/bareboxenv-target: scripts/bareboxenv.c FORCE - $(call if_changed_dep,csingle) --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0003-console-fix-console-without-CONFIG_PARAMETER.patch b/patches/barebox-2013.07.0/0003-console-fix-console-without-CONFIG_PARAMETER.patch deleted file mode 100644 index e0a0076..0000000 --- a/patches/barebox-2013.07.0/0003-console-fix-console-without-CONFIG_PARAMETER.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 08c73dea817bc6c589e3ef4fae11fccdd562c81c Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Mon, 15 Apr 2013 18:17:30 +0200 -Subject: [PATCH 03/17] console: fix console without CONFIG_PARAMETER - -If CONFIG_PARAMETER is not set, dev_set_param() does not call the setter -function. Call it directly instead in this case. - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - common/console.c | 8 ++++++-- - 1 file changed, 6 insertions(+), 2 deletions(-) - -diff --git a/common/console.c b/common/console.c -index a0a06f6..b2d70f5 100644 ---- a/common/console.c -+++ b/common/console.c -@@ -163,8 +163,12 @@ int console_register(struct console_device *newcdev) - - list_add_tail(&newcdev->list, &console_list); - -- if (activate) -- dev_set_param(dev, "active", "ioe"); -+ if (activate) { -+ if (IS_ENABLED(CONFIG_PARAMETER)) -+ dev_set_param(dev, "active", "ioe"); -+ else -+ console_std_set(dev, NULL, "ioe"); -+ } - - return 0; - } --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0004-beaglebone-fix-booting.patch b/patches/barebox-2013.07.0/0004-beaglebone-fix-booting.patch deleted file mode 100644 index fb5d09c..0000000 --- a/patches/barebox-2013.07.0/0004-beaglebone-fix-booting.patch +++ /dev/null @@ -1,63 +0,0 @@ -From 3c44683c4f806eedf920704b768f178221e652e1 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 14 Jul 2013 13:21:00 +0200 -Subject: [PATCH 04/17] beaglebone: fix booting - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/lowlevel.c | 17 ++++++++++++++--- - 1 file changed, 14 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c -index 28959ff..2a8e677 100644 ---- a/arch/arm/boards/beaglebone/lowlevel.c -+++ b/arch/arm/boards/beaglebone/lowlevel.c -@@ -1,6 +1,7 @@ - #include <init.h> - #include <sizes.h> - #include <io.h> -+#include <asm/armlinux.h> - #include <asm/barebox-arm-head.h> - #include <asm/barebox-arm.h> - #include <mach/am33xx-silicon.h> -@@ -201,6 +202,9 @@ void beaglebone_sram_init(void) - - beaglebone_config_ddr(); - -+ /* Enable pin mux */ -+ am33xx_enable_uart0_pin_mux(); -+ - /* UART softreset */ - uart_base = AM33XX_UART0_BASE; - -@@ -242,17 +246,24 @@ static int beaglebone_board_init(void) - if (!in_sdram) - beaglebone_sram_init(); - -- /* Enable pin mux */ -- am33xx_enable_uart0_pin_mux(); -+ return 0; -+} -+ -+static int beaglebone_sram_mem_init(void) -+{ -+ if (!running_in_sdram()) -+ arm_add_mem_device("sram", 0x402F0400, 0x4030CE00-0x402F0400); - - return 0; - } -+mem_initcall(beaglebone_sram_mem_init); - --void __naked barebox_arm_reset_vector(void) -+void __bare_init __naked barebox_arm_reset_vector(void) - { - arm_cpu_lowlevel_init(); - - beaglebone_board_init(); - - barebox_arm_entry(0x80000000, SZ_256M, 0); -+ /* barebox_arm_entry(0x402F0400, 0x4030CE00-0x402F0400, 0); */ /* for SRAM */ - } --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0005-beaglebone-env-use-config-board-instead-of-config.patch b/patches/barebox-2013.07.0/0005-beaglebone-env-use-config-board-instead-of-config.patch deleted file mode 100644 index e9e2db1..0000000 --- a/patches/barebox-2013.07.0/0005-beaglebone-env-use-config-board-instead-of-config.patch +++ /dev/null @@ -1,56 +0,0 @@ -From d4a3d4e53d37d64a7c2490b103356b18cf0999be Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Mon, 8 Apr 2013 18:05:35 +0200 -Subject: [PATCH 05/17] beaglebone: env: use config-board instead of config - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/env/config | 21 --------------------- - arch/arm/boards/beaglebone/env/config-board | 7 +++++++ - 2 files changed, 7 insertions(+), 21 deletions(-) - delete mode 100644 arch/arm/boards/beaglebone/env/config - create mode 100644 arch/arm/boards/beaglebone/env/config-board - -diff --git a/arch/arm/boards/beaglebone/env/config b/arch/arm/boards/beaglebone/env/config -deleted file mode 100644 -index 4b7a635..0000000 ---- a/arch/arm/boards/beaglebone/env/config -+++ /dev/null -@@ -1,21 +0,0 @@ --#!/bin/sh -- --# change network settings in /env/network/eth0 --# change mtd partition settings and automountpoints in /env/init/* -- --global.hostname=beaglebone -- --# set to false if you do not want to have colors --global.allow_color=true -- --# user (used for network filenames) --global.user=none -- --# timeout in seconds before the default boot entry is started --global.autoboot_timeout=3 -- --# default boot entry (one of /env/boot/*) --global.boot.default=sd -- --# base bootargs --global.linux.bootargs.base="console=ttyO0,115200n8" -diff --git a/arch/arm/boards/beaglebone/env/config-board b/arch/arm/boards/beaglebone/env/config-board -new file mode 100644 -index 0000000..f9a2db7 ---- /dev/null -+++ b/arch/arm/boards/beaglebone/env/config-board -@@ -0,0 +1,7 @@ -+#!/bin/sh -+ -+# board defaults, do not change in running system. Change /env/config -+# instead -+ -+global.hostname=beaglebone -+global.linux.bootargs.base="console=ttyO0,115200n8" --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch b/patches/barebox-2013.07.0/0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch deleted file mode 100644 index 7f346d1..0000000 --- a/patches/barebox-2013.07.0/0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 6bf54b3d1cc8b5506781fc3e754e38a65371e9b1 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 31 Mar 2013 12:28:01 +0200 -Subject: [PATCH 06/17] WIP: beaglebone: add simple script to change usb - current limit - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/env/init/usb-limit-1300 | 5 +++++ - 1 file changed, 5 insertions(+) - create mode 100644 arch/arm/boards/beaglebone/env/init/usb-limit-1300 - -diff --git a/arch/arm/boards/beaglebone/env/init/usb-limit-1300 b/arch/arm/boards/beaglebone/env/init/usb-limit-1300 -new file mode 100644 -index 0000000..56313bf ---- /dev/null -+++ b/arch/arm/boards/beaglebone/env/init/usb-limit-1300 -@@ -0,0 +1,5 @@ -+#!/bin/sh -+ -+echo -n "changing USB current limit to 1300 mA... " -+i2c_write -b 0 -a 0x24 -r 0x01 0x3e -+echo "done" --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0007-ARM-AM33xx-Add-gpio-support.patch b/patches/barebox-2013.07.0/0007-ARM-AM33xx-Add-gpio-support.patch deleted file mode 100644 index 4740391..0000000 --- a/patches/barebox-2013.07.0/0007-ARM-AM33xx-Add-gpio-support.patch +++ /dev/null @@ -1,41 +0,0 @@ -From af8dbd7d41f9a57791b2bd04c277728ad3ea5138 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> -Date: Tue, 9 Jul 2013 11:23:13 +0200 -Subject: [PATCH 07/17] ARM: AM33xx: Add gpio support -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Register GPIO banks for AM33xx boards. - -Signed-off-by: Teresa Gámez <t.gamez@phytec.de> -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> ---- - arch/arm/mach-omap/am33xx_generic.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - -diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c -index 96432c9..3ab16b0 100644 ---- a/arch/arm/mach-omap/am33xx_generic.c -+++ b/arch/arm/mach-omap/am33xx_generic.c -@@ -126,3 +126,17 @@ int am33xx_register_ethaddr(int eth_id, int mac_id) - - return -ENODEV; - } -+ -+static int am33xx_gpio_init(void) -+{ -+ add_generic_device("omap-gpio", 0, NULL, AM33XX_GPIO0_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ add_generic_device("omap-gpio", 1, NULL, AM33XX_GPIO1_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ add_generic_device("omap-gpio", 2, NULL, AM33XX_GPIO2_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ add_generic_device("omap-gpio", 3, NULL, AM33XX_GPIO3_BASE, -+ 0xf00, IORESOURCE_MEM, NULL); -+ return 0; -+} -+coredevice_initcall(am33xx_gpio_init); --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch b/patches/barebox-2013.07.0/0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch deleted file mode 100644 index 654c58f..0000000 --- a/patches/barebox-2013.07.0/0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch +++ /dev/null @@ -1,40 +0,0 @@ -From b284ba947ff3626063aabd0e5bb9ec16aba8e145 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> -Date: Tue, 9 Jul 2013 11:23:17 +0200 -Subject: [PATCH 08/17] ARM: AM33xx: Enable clock for all GPIO banks -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Teresa Gámez <t.gamez@phytec.de> -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> ---- - arch/arm/mach-omap/am33xx_clock.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - -diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c -index 4451d62..e4d9d77 100644 ---- a/arch/arm/mach-omap/am33xx_clock.c -+++ b/arch/arm/mach-omap/am33xx_clock.c -@@ -53,6 +53,18 @@ static void interface_clocks_enable(void) - /* GPIO0 */ - __raw_writel(PRCM_MOD_EN, CM_WKUP_GPIO0_CLKCTRL); - while (__raw_readl(CM_WKUP_GPIO0_CLKCTRL) != PRCM_MOD_EN); -+ -+ /* GPIO1 */ -+ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO1_CLKCTRL); -+ while (__raw_readl(CM_PER_GPIO1_CLKCTRL) != PRCM_MOD_EN); -+ -+ /* GPIO2 */ -+ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO2_CLKCTRL); -+ while (__raw_readl(CM_PER_GPIO2_CLKCTRL) != PRCM_MOD_EN); -+ -+ /* GPIO3 */ -+ __raw_writel(PRCM_MOD_EN, CM_PER_GPIO3_CLKCTRL); -+ while (__raw_readl(CM_PER_GPIO3_CLKCTRL) != PRCM_MOD_EN); - } - - static void power_domain_transition_enable(void) --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch b/patches/barebox-2013.07.0/0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch deleted file mode 100644 index 76ebeae..0000000 --- a/patches/barebox-2013.07.0/0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 16f580940c592e26d9e816be330509e16a2741da Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> -Date: Tue, 9 Jul 2013 11:23:19 +0200 -Subject: [PATCH 09/17] ARM: AM33xx: Make mpu pll configurable by lowlevel - board code -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Signed-off-by: Teresa Gámez <t.gamez@phytec.de> -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> ---- - arch/arm/boards/beaglebone/lowlevel.c | 2 +- - arch/arm/mach-omap/am33xx_clock.c | 4 ++-- - arch/arm/mach-omap/include/mach/am33xx-clock.h | 2 +- - 3 files changed, 4 insertions(+), 4 deletions(-) - -diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c -index 2a8e677..ebbd960 100644 ---- a/arch/arm/boards/beaglebone/lowlevel.c -+++ b/arch/arm/boards/beaglebone/lowlevel.c -@@ -198,7 +198,7 @@ void beaglebone_sram_init(void) - u32 regVal, uart_base; - - /* Setup the PLLs and the clocks for the peripherals */ -- pll_init(); -+ pll_init(MPUPLL_M_500); - - beaglebone_config_ddr(); - -diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c -index e4d9d77..9928e9f 100644 ---- a/arch/arm/mach-omap/am33xx_clock.c -+++ b/arch/arm/mach-omap/am33xx_clock.c -@@ -294,9 +294,9 @@ void enable_ddr_clocks(void) - /* - * Configure the PLL/PRCM for necessary peripherals - */ --void pll_init() -+void pll_init(int mpupll_M) - { -- mpu_pll_config(MPUPLL_M_500); -+ mpu_pll_config(mpupll_M); - core_pll_config(); - per_pll_config(); - ddr_pll_config(); -diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h -index 3d1f074..968509e 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-clock.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h -@@ -187,7 +187,7 @@ - - #define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL - --extern void pll_init(void); -+extern void pll_init(int mpupll_M); - extern void enable_ddr_clocks(void); - - #endif /* endif _AM33XX_CLOCKS_H_ */ --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0010-arm-omap-store-boot-source-info-from-ROM-loader.patch b/patches/barebox-2013.07.0/0010-arm-omap-store-boot-source-info-from-ROM-loader.patch deleted file mode 100644 index 3edcb3a..0000000 --- a/patches/barebox-2013.07.0/0010-arm-omap-store-boot-source-info-from-ROM-loader.patch +++ /dev/null @@ -1,481 +0,0 @@ -From 989eded334449152f1a3a162dd20939a7c9de388 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> -Date: Tue, 9 Jul 2013 11:23:20 +0200 -Subject: [PATCH 10/17] arm: omap: store boot source info from ROM loader -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The ROM loader passes the address of a buffer to the MLO in -register 0. Store this data so we can find the boot source later. -On the same way the bootinformation are passed to the barebox, -then. It has to be enshured that r0 contains always the -buffer or the boot source detection will not work. - -Applied this on all OMAPs. This patch is based on work of -Jan Luebbe <jlu@pengutronix.de>. - -Compile tested on all OMAP boards. -Tested on pcm049, phyCARD-A-L1 and pcm051. - -Signed-off-by: Teresa Gámez <t.gamez@phytec.de> -Tested-by: Christoph Fritz <chf.fritz@googlemail.com> -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> ---- - arch/arm/boards/archosg9/lowlevel.c | 5 ++++- - arch/arm/boards/beagle/lowlevel.c | 6 +++++- - arch/arm/boards/beaglebone/lowlevel.c | 5 ++++- - arch/arm/boards/omap343xdsp/lowlevel.c | 6 +++++- - arch/arm/boards/omap3evm/lowlevel.c | 5 ++++- - arch/arm/boards/panda/lowlevel.c | 6 +++++- - arch/arm/boards/pcm049/lowlevel.c | 6 +++++- - arch/arm/boards/phycard-a-l1/lowlevel.c | 5 ++++- - arch/arm/boards/phycard-a-xl2/lowlevel.c | 6 +++++- - arch/arm/mach-omap/Makefile | 4 ++-- - arch/arm/mach-omap/am33xx_generic.c | 18 +++++++++++++++++- - arch/arm/mach-omap/include/mach/generic.h | 3 +++ - arch/arm/mach-omap/omap3_generic.c | 16 +++++++++++++--- - arch/arm/mach-omap/omap4_generic.c | 18 +++++++++++++----- - arch/arm/mach-omap/omap_bootinfo.S | 25 +++++++++++++++++++++++++ - arch/arm/mach-omap/xload.c | 8 ++++++-- - 16 files changed, 120 insertions(+), 22 deletions(-) - create mode 100644 arch/arm/mach-omap/omap_bootinfo.S - -diff --git a/arch/arm/boards/archosg9/lowlevel.c b/arch/arm/boards/archosg9/lowlevel.c -index 0334693..d443a60 100644 ---- a/arch/arm/boards/archosg9/lowlevel.c -+++ b/arch/arm/boards/archosg9/lowlevel.c -@@ -14,6 +14,7 @@ - #include <io.h> - #include <init.h> - #include <sizes.h> -+#include <mach/generic.h> - #include <mach/omap4-mux.h> - #include <mach/omap4-silicon.h> - #include <mach/omap4-clock.h> -@@ -65,8 +66,10 @@ static noinline void archosg9_init_lowlevel(void) - omap4_ddr_init(&ddr_regs_400_mhz_2cs, &core); - } - --void __naked __bare_init barebox_arm_reset_vector(void) -+void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) -diff --git a/arch/arm/boards/beagle/lowlevel.c b/arch/arm/boards/beagle/lowlevel.c -index d0fd066..ef7e3c0 100644 ---- a/arch/arm/boards/beagle/lowlevel.c -+++ b/arch/arm/boards/beagle/lowlevel.c -@@ -1,8 +1,10 @@ -+#include <init.h> - #include <io.h> - #include <sizes.h> - #include <asm/barebox-arm-head.h> - #include <asm/barebox-arm.h> - #include <mach/control.h> -+#include <mach/generic.h> - #include <mach/omap3-silicon.h> - #include <mach/omap3-mux.h> - #include <mach/sdrc.h> -@@ -178,8 +180,10 @@ static int beagle_board_init(void) - return 0; - } - --void __naked barebox_arm_reset_vector(void) -+void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - beagle_board_init(); -diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c -index ebbd960..59d9ff1 100644 ---- a/arch/arm/boards/beaglebone/lowlevel.c -+++ b/arch/arm/boards/beaglebone/lowlevel.c -@@ -6,6 +6,7 @@ - #include <asm/barebox-arm.h> - #include <mach/am33xx-silicon.h> - #include <mach/am33xx-clock.h> -+#include <mach/generic.h> - #include <mach/sdrc.h> - #include <mach/sys_info.h> - #include <mach/syslib.h> -@@ -258,8 +259,10 @@ static int beaglebone_sram_mem_init(void) - } - mem_initcall(beaglebone_sram_mem_init); - --void __bare_init __naked barebox_arm_reset_vector(void) -+void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - beaglebone_board_init(); -diff --git a/arch/arm/boards/omap343xdsp/lowlevel.c b/arch/arm/boards/omap343xdsp/lowlevel.c -index ed675ad..61b7f99 100644 ---- a/arch/arm/boards/omap343xdsp/lowlevel.c -+++ b/arch/arm/boards/omap343xdsp/lowlevel.c -@@ -1,8 +1,10 @@ - #include <common.h> -+#include <init.h> - #include <io.h> - #include <sizes.h> - #include <asm/barebox-arm-head.h> - #include <asm/barebox-arm.h> -+#include <mach/generic.h> - #include <mach/omap3-mux.h> - #include <mach/sdrc.h> - #include <mach/control.h> -@@ -545,8 +547,10 @@ static int sdp343x_board_init(void) - return 0; - } - --void __naked barebox_arm_reset_vector(void) -+void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - sdp343x_board_init(); -diff --git a/arch/arm/boards/omap3evm/lowlevel.c b/arch/arm/boards/omap3evm/lowlevel.c -index 2d9e130..ea92835 100644 ---- a/arch/arm/boards/omap3evm/lowlevel.c -+++ b/arch/arm/boards/omap3evm/lowlevel.c -@@ -3,6 +3,7 @@ - #include <sizes.h> - #include <asm/barebox-arm-head.h> - #include <asm/barebox-arm.h> -+#include <mach/generic.h> - #include <mach/omap3-mux.h> - #include <mach/sdrc.h> - #include <mach/control.h> -@@ -159,8 +160,10 @@ static int omap3_evm_board_init(void) - return 0; - } - --void __naked barebox_arm_reset_vector(void) -+void __naked __bare_init barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - omap3_evm_board_init(); -diff --git a/arch/arm/boards/panda/lowlevel.c b/arch/arm/boards/panda/lowlevel.c -index ed1dc6f..76ef83b 100644 ---- a/arch/arm/boards/panda/lowlevel.c -+++ b/arch/arm/boards/panda/lowlevel.c -@@ -17,8 +17,10 @@ - * - */ - #include <common.h> -+#include <init.h> - #include <io.h> - #include <sizes.h> -+#include <mach/generic.h> - #include <mach/omap4-mux.h> - #include <mach/omap4-silicon.h> - #include <mach/omap4-clock.h> -@@ -73,8 +75,10 @@ static void noinline panda_init_lowlevel(void) - omap4_scale_vcores(TPS62361_VSEL0_GPIO); - } - --void barebox_arm_reset_vector(void) -+void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) -diff --git a/arch/arm/boards/pcm049/lowlevel.c b/arch/arm/boards/pcm049/lowlevel.c -index 8bcecb1..e409ad8 100644 ---- a/arch/arm/boards/pcm049/lowlevel.c -+++ b/arch/arm/boards/pcm049/lowlevel.c -@@ -17,8 +17,10 @@ - * - */ - #include <common.h> -+#include <init.h> - #include <io.h> - #include <sizes.h> -+#include <mach/generic.h> - #include <mach/omap4-mux.h> - #include <mach/omap4-silicon.h> - #include <mach/omap4-clock.h> -@@ -102,8 +104,10 @@ static void noinline pcm049_init_lowlevel(void) - sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3); /* enable clocks */ - } - --void barebox_arm_reset_vector(void) -+void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) -diff --git a/arch/arm/boards/phycard-a-l1/lowlevel.c b/arch/arm/boards/phycard-a-l1/lowlevel.c -index 30379d8..7855040 100644 ---- a/arch/arm/boards/phycard-a-l1/lowlevel.c -+++ b/arch/arm/boards/phycard-a-l1/lowlevel.c -@@ -5,6 +5,7 @@ - #include <asm/barebox-arm-head.h> - #include <asm/barebox-arm.h> - #include <mach/omap3-mux.h> -+#include <mach/generic.h> - #include <mach/sdrc.h> - #include <mach/control.h> - #include <mach/syslib.h> -@@ -250,8 +251,10 @@ static int pcaal1_board_init(void) - return 0; - } - --void __naked barebox_arm_reset_vector(void) -+void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - pcaal1_board_init(); -diff --git a/arch/arm/boards/phycard-a-xl2/lowlevel.c b/arch/arm/boards/phycard-a-xl2/lowlevel.c -index 07505ff..5e68334 100644 ---- a/arch/arm/boards/phycard-a-xl2/lowlevel.c -+++ b/arch/arm/boards/phycard-a-xl2/lowlevel.c -@@ -17,8 +17,10 @@ - * - */ - #include <common.h> -+#include <init.h> - #include <io.h> - #include <sizes.h> -+#include <mach/generic.h> - #include <mach/omap4-mux.h> - #include <mach/omap4-silicon.h> - #include <mach/omap4-clock.h> -@@ -83,8 +85,10 @@ static noinline void pcaaxl2_init_lowlevel(void) - sr32(0x4A30a110, 2, 2, 0x3); /* enable clocks */ - } - --void barebox_arm_reset_vector(void) -+void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) - { -+ omap_save_bootinfo(); -+ - arm_cpu_lowlevel_init(); - - if (get_pc() > 0x80000000) -diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile -index 973068d..d42de48 100644 ---- a/arch/arm/mach-omap/Makefile -+++ b/arch/arm/mach-omap/Makefile -@@ -15,8 +15,8 @@ - # GNU General Public License for more details. - # - # --obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o --pbl-$(CONFIG_ARCH_OMAP) += syslib.o -+obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_bootinfo.o -+pbl-$(CONFIG_ARCH_OMAP) += syslib.o omap_bootinfo.o - obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o - obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER0) += dmtimer0.o - obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o -diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c -index 3ab16b0..45fefb4 100644 ---- a/arch/arm/mach-omap/am33xx_generic.c -+++ b/arch/arm/mach-omap/am33xx_generic.c -@@ -25,6 +25,7 @@ - #include <net.h> - #include <mach/am33xx-silicon.h> - #include <mach/am33xx-clock.h> -+#include <mach/generic.h> - #include <mach/sys_info.h> - #include <mach/am33xx-generic.h> - -@@ -97,7 +98,22 @@ u32 running_in_sdram(void) - - static int am33xx_bootsource(void) - { -- bootsource_set(BOOTSOURCE_MMC); /* only MMC for now */ -+ enum bootsource src; -+ -+ switch (omap_bootinfo[2] & 0xFF) { -+ case 0x05: -+ src = BOOTSOURCE_NAND; -+ break; -+ case 0x08: -+ src = BOOTSOURCE_MMC; -+ break; -+ case 0x0b: -+ src = BOOTSOURCE_SPI; -+ break; -+ default: -+ src = BOOTSOURCE_UNKNOWN; -+ } -+ bootsource_set(src); - bootsource_set_instance(0); - return 0; - } -diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h -index 5a10a54..f1a3efe 100644 ---- a/arch/arm/mach-omap/include/mach/generic.h -+++ b/arch/arm/mach-omap/include/mach/generic.h -@@ -27,4 +27,7 @@ - #define cpu_is_omap4xxx() (0) - #endif - -+extern uint32_t omap_bootinfo[3]; -+void omap_save_bootinfo(void); -+ - #endif -diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c -index f144813..8b661ff 100644 ---- a/arch/arm/mach-omap/omap3_generic.c -+++ b/arch/arm/mach-omap/omap3_generic.c -@@ -33,6 +33,7 @@ - #include <io.h> - #include <mach/omap3-silicon.h> - #include <mach/gpmc.h> -+#include <mach/generic.h> - #include <mach/sdrc.h> - #include <mach/control.h> - #include <mach/omap3-smx.h> -@@ -468,12 +469,21 @@ void omap3_core_init(void) - static int omap3_bootsource(void) - { - enum bootsource src = BOOTSOURCE_UNKNOWN; -- u32 bootsrc = readl(OMAP3_TRACING_VECTOR1); - -- if (bootsrc & (1 << 2)) -+ switch (omap_bootinfo[1] & 0xFF) { -+ case 0x02: - src = BOOTSOURCE_NAND; -- if (bootsrc & (1 << 6)) -+ break; -+ case 0x06: - src = BOOTSOURCE_MMC; -+ break; -+ case 0x11: -+ src = BOOTSOURCE_USB; -+ break; -+ default: -+ src = BOOTSOURCE_UNKNOWN; -+ } -+ - bootsource_set(src); - bootsource_set_instance(0); - -diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c -index 7d71fdc..4e98205 100644 ---- a/arch/arm/mach-omap/omap4_generic.c -+++ b/arch/arm/mach-omap/omap4_generic.c -@@ -6,6 +6,7 @@ - #include <mach/omap4-silicon.h> - #include <mach/omap4-mux.h> - #include <mach/syslib.h> -+#include <mach/generic.h> - #include <mach/gpmc.h> - #include <mach/gpio.h> - #include <mach/omap4_rom_usb.h> -@@ -504,14 +505,21 @@ static int omap_vector_init(void) - static int omap4_bootsource(void) - { - enum bootsource src = BOOTSOURCE_UNKNOWN; -- u32 bootsrc = readl(OMAP4_TRACING_VECTOR3); - -- if (bootsrc & (1 << 5)) -- src = BOOTSOURCE_MMC; -- else if (bootsrc & (1 << 3)) -+ switch (omap_bootinfo[2] & 0xFF) { -+ case 0x03: - src = BOOTSOURCE_NAND; -- else if (bootsrc & (1<<20)) -+ break; -+ case 0x05: -+ src = BOOTSOURCE_MMC; -+ break; -+ case 0x20: - src = BOOTSOURCE_USB; -+ break; -+ default: -+ src = BOOTSOURCE_UNKNOWN; -+ } -+ - bootsource_set(src); - bootsource_set_instance(0); - -diff --git a/arch/arm/mach-omap/omap_bootinfo.S b/arch/arm/mach-omap/omap_bootinfo.S -new file mode 100644 -index 0000000..ffd0a3d ---- /dev/null -+++ b/arch/arm/mach-omap/omap_bootinfo.S -@@ -0,0 +1,25 @@ -+#include <config.h> -+#include <linux/linkage.h> -+#include <asm/assembler.h> -+ -+.section ".text_bare_init","ax" -+.globl omap_bootinfo -+omap_bootinfo: -+ .word 0x0 -+ .word 0x0 -+ .word 0x0 -+ -+.section ".text_bare_init","ax" -+ENTRY(omap_save_bootinfo) -+ /* -+ * save data from rom boot loader -+ */ -+ adr r2, omap_bootinfo -+ ldr r1, [r0, #0x00] -+ str r1, [r2, #0x00] -+ ldr r1, [r0, #0x04] -+ str r1, [r2, #0x04] -+ ldr r1, [r0, #0x08] -+ str r1, [r2, #0x08] -+ mov pc, lr -+ENDPROC(omap_save_bootinfo) -diff --git a/arch/arm/mach-omap/xload.c b/arch/arm/mach-omap/xload.c -index 3cce3f2..3dbdef5 100644 ---- a/arch/arm/mach-omap/xload.c -+++ b/arch/arm/mach-omap/xload.c -@@ -9,6 +9,7 @@ - #include <fcntl.h> - #include <sizes.h> - #include <filetype.h> -+#include <mach/generic.h> - - static void *read_image_head(const char *name) - { -@@ -163,7 +164,8 @@ static void *omap4_xload_boot_usb(void){ - */ - static __noreturn int omap_xload(void) - { -- int (*func)(void) = NULL; -+ int (*func)(void *) = NULL; -+ uint32_t *arg; - - switch (bootsource_get()) - { -@@ -198,8 +200,10 @@ static __noreturn int omap_xload(void) - while (1); - } - -+ arg = (uint32_t *)&omap_bootinfo; -+ - shutdown_barebox(); -- func(); -+ func(arg); - - while (1); - } --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0011-i2c-omap-cleanup-cpu_is-functions.patch b/patches/barebox-2013.07.0/0011-i2c-omap-cleanup-cpu_is-functions.patch deleted file mode 100644 index 3212c33..0000000 --- a/patches/barebox-2013.07.0/0011-i2c-omap-cleanup-cpu_is-functions.patch +++ /dev/null @@ -1,247 +0,0 @@ -From b7912f1e3d3ddebbb544e0808df65010e10efad6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> -Date: Thu, 20 Jun 2013 14:50:28 +0200 -Subject: [PATCH 11/17] i2c-omap: cleanup cpu_is functions -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -cpu_is_omap2430() is set when CONFIG_ARCH_OMAP is enabled. -This fits for all OMAP/AM33xx boards supported in barebox. -Cleaned up all conditions that use the cpu_is_omap2430(). -Also removed some unused defines. - -Signed-off-by: Teresa Gámez <t.gamez@phytec.de> -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> ---- - drivers/i2c/busses/i2c-omap.c | 159 +++++++++++++++-------------------------- - 1 file changed, 57 insertions(+), 102 deletions(-) - -diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c -index 503443f..ecb33ea 100644 ---- a/drivers/i2c/busses/i2c-omap.c -+++ b/drivers/i2c/busses/i2c-omap.c -@@ -24,10 +24,6 @@ - * GNU General Public License for more details. - */ - -- --/* #include <linux/delay.h> */ -- -- - #include <clock.h> - #include <common.h> - #include <driver.h> -@@ -44,12 +40,6 @@ - #include <mach/generic.h> - #include <mach/omap3-clock.h> - --#define OMAP_I2C_SIZE 0x3f --#define OMAP1_I2C_BASE 0xfffb3800 --#define OMAP2_I2C_BASE1 0x48070000 --#define OMAP2_I2C_BASE2 0x48072000 --#define OMAP2_I2C_BASE3 0x48060000 -- - /* This will be the driver name */ - #define DRIVER_NAME "i2c-omap" - -@@ -141,7 +131,6 @@ - #define SYSC_IDLEMODE_SMART 0x2 - #define SYSC_CLOCKACTIVITY_FCLK 0x2 - -- - struct omap_i2c_struct { - void *base; - u8 *regs; -@@ -352,63 +341,51 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap) - } - omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0); - -- /* omap1 handling is missing here */ -- -- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap4xxx()) { -- -- /* -- * HSI2C controller internal clk rate should be 19.2 Mhz for -- * HS and for all modes on 2430. On 34xx we can use lower rate -- * to get longer filter period for better noise suppression. -- * The filter is iclk (fclk for HS) period. -- */ -- if (i2c_omap->speed > 400 || cpu_is_omap2430()) -- internal_clk = 19200; -- else if (i2c_omap->speed > 100) -- internal_clk = 9600; -- else -- internal_clk = 4000; -- fclk_rate = 96000000 / 1000; -- -- /* Compute prescaler divisor */ -- psc = fclk_rate / internal_clk; -- psc = psc - 1; -- -- /* If configured for High Speed */ -- if (i2c_omap->speed > 400) { -- unsigned long scl; -- -- /* For first phase of HS mode */ -- scl = internal_clk / 400; -- fsscll = scl - (scl / 3) - 7; -- fssclh = (scl / 3) - 5; -- -- /* For second phase of HS mode */ -- scl = fclk_rate / i2c_omap->speed; -- hsscll = scl - (scl / 3) - 7; -- hssclh = (scl / 3) - 5; -- } else if (i2c_omap->speed > 100) { -- unsigned long scl; -- -- /* Fast mode */ -- scl = internal_clk / i2c_omap->speed; -- fsscll = scl - (scl / 3) - 7; -- fssclh = (scl / 3) - 5; -- } else { -- /* Standard mode */ -- fsscll = internal_clk / (i2c_omap->speed * 2) - 7; -- fssclh = internal_clk / (i2c_omap->speed * 2) - 5; -- } -- scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; -- sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; -+ /* -+ * HSI2C controller internal clk rate should be 19.2 Mhz for -+ * HS and for all modes on 2430. On 34xx we can use lower rate -+ * to get longer filter period for better noise suppression. -+ * The filter is iclk (fclk for HS) period. -+ */ -+ if (i2c_omap->speed > 400) -+ internal_clk = 19200; -+ else if (i2c_omap->speed > 100) -+ internal_clk = 9600; -+ else -+ internal_clk = 4000; -+ fclk_rate = 96000000 / 1000; -+ -+ /* Compute prescaler divisor */ -+ psc = fclk_rate / internal_clk; -+ psc = psc - 1; -+ -+ /* If configured for High Speed */ -+ if (i2c_omap->speed > 400) { -+ unsigned long scl; -+ -+ /* For first phase of HS mode */ -+ scl = internal_clk / 400; -+ fsscll = scl - (scl / 3) - 7; -+ fssclh = (scl / 3) - 5; -+ -+ /* For second phase of HS mode */ -+ scl = fclk_rate / i2c_omap->speed; -+ hsscll = scl - (scl / 3) - 7; -+ hssclh = (scl / 3) - 5; -+ } else if (i2c_omap->speed > 100) { -+ unsigned long scl; -+ -+ /* Fast mode */ -+ scl = internal_clk / i2c_omap->speed; -+ fsscll = scl - (scl / 3) - 7; -+ fssclh = (scl / 3) - 5; - } else { -- /* Program desired operating rate */ -- fclk_rate /= (psc + 1) * 1000; -- if (psc > 2) -- psc = 2; -- scll = fclk_rate / (i2c_omap->speed * 2) - 7 + psc; -- sclh = fclk_rate / (i2c_omap->speed * 2) - 7 + psc; -+ /* Standard mode */ -+ fsscll = internal_clk / (i2c_omap->speed * 2) - 7; -+ fssclh = internal_clk / (i2c_omap->speed * 2) - 5; - } -+ scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; -+ sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; - - /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ - omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, psc); -@@ -525,15 +502,6 @@ complete: - if (dev->buf_len) { - *dev->buf++ = w; - dev->buf_len--; -- /* Data reg from 2430 is 8 bit wide */ -- if (!cpu_is_omap2430() && -- !cpu_is_omap34xx() && -- !cpu_is_omap4xxx()) { -- if (dev->buf_len) { -- *dev->buf++ = w >> 8; -- dev->buf_len--; -- } -- } - } else { - if (stat & OMAP_I2C_STAT_RRDY) - dev_err(&dev->adapter.dev, -@@ -566,15 +534,6 @@ complete: - if (dev->buf_len) { - w = *dev->buf++; - dev->buf_len--; -- /* Data reg from 2430 is 8 bit wide */ -- if (!cpu_is_omap2430() && -- !cpu_is_omap34xx() && -- !cpu_is_omap4xxx()) { -- if (dev->buf_len) { -- w |= *dev->buf++ << 8; -- dev->buf_len--; -- } -- } - } else { - if (stat & OMAP_I2C_STAT_XRDY) - dev_err(&dev->adapter.dev, -@@ -776,6 +735,7 @@ i2c_omap_probe(struct device_d *pdev) - /* struct i2c_platform_data *pdata; */ - int r; - u32 speed = 0; -+ u16 s; - - i2c_omap = kzalloc(sizeof(struct omap_i2c_struct), GFP_KERNEL); - if (!i2c_omap) { -@@ -802,28 +762,23 @@ i2c_omap_probe(struct device_d *pdev) - omap_i2c_unidle(i2c_omap); - - i2c_omap->rev = omap_i2c_read_reg(i2c_omap, OMAP_I2C_REV_REG) & 0xff; -- /* i2c_omap->base = OMAP2_I2C_BASE3; */ -- -- if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap4xxx()) { -- u16 s; - -- /* Set up the fifo size - Get total size */ -- s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; -- i2c_omap->fifo_size = 0x8 << s; -+ /* Set up the fifo size - Get total size */ -+ s = (omap_i2c_read_reg(i2c_omap, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3; -+ i2c_omap->fifo_size = 0x8 << s; - -- /* -- * Set up notification threshold as half the total available -- * size. This is to ensure that we can handle the status on int -- * call back latencies. -- */ -+ /* -+ * Set up notification threshold as half the total available -+ * size. This is to ensure that we can handle the status on int -+ * call back latencies. -+ */ - -- i2c_omap->fifo_size = (i2c_omap->fifo_size / 2); -+ i2c_omap->fifo_size = (i2c_omap->fifo_size / 2); - -- if (i2c_omap->rev >= OMAP_I2C_REV_ON_4430) -- i2c_omap->b_hw = 0; /* Disable hardware fixes */ -- else -- i2c_omap->b_hw = 1; /* Enable hardware fixes */ -- } -+ if (i2c_omap->rev >= OMAP_I2C_REV_ON_4430) -+ i2c_omap->b_hw = 0; /* Disable hardware fixes */ -+ else -+ i2c_omap->b_hw = 1; /* Enable hardware fixes */ - - /* reset ASAP, clearing any IRQs */ - omap_i2c_init(i2c_omap); --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch b/patches/barebox-2013.07.0/0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch deleted file mode 100644 index 05801aa..0000000 --- a/patches/barebox-2013.07.0/0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch +++ /dev/null @@ -1,138 +0,0 @@ -From 6289d04745fe4282a5a255318bed673e73b29bd8 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Teresa=20G=C3=A1mez?= <t.gamez@phytec.de> -Date: Thu, 20 Jun 2013 14:50:29 +0200 -Subject: [PATCH 12/17] ARM: AM33xx: Add i2c support for AM33xx -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Added device register functions and cpu_is_am33xx() -function. -Adapted the i2c-omap driver. AM335x has a lower -clock rate and the timeout of polling the isr function -had to be increased. - -Based on a patch from Shravan Kumar <shravan.k@phytec.in>. - -Signed-off-by: Teresa Gámez <t.gamez@phytec.de> -Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> ---- - arch/arm/mach-omap/include/mach/am33xx-devices.h | 15 +++++++++++++++ - arch/arm/mach-omap/include/mach/am33xx-silicon.h | 5 +++++ - arch/arm/mach-omap/include/mach/generic.h | 6 ++++++ - drivers/i2c/busses/i2c-omap.c | 14 +++++++++----- - 4 files changed, 35 insertions(+), 5 deletions(-) - -diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h -index fe9fba9..edf8982 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-devices.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h -@@ -37,4 +37,19 @@ static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_d - AM335X_CPSW_BASE, SZ_32K, IORESOURCE_MEM, cpsw_data); - } - -+static inline struct device_d *am33xx_add_i2c0(void *pdata) -+{ -+ return omap_add_i2c(0, AM33XX_I2C0_BASE, pdata); -+} -+ -+static inline struct device_d *am33xx_add_i2c1(void *pdata) -+{ -+ return omap_add_i2c(1, AM33XX_I2C1_BASE, pdata); -+} -+ -+static inline struct device_d *am33xx_add_i2c2(void *pdata) -+{ -+ return omap_add_i2c(2, AM33XX_I2C2_BASE, pdata); -+} -+ - #endif /* __MACH_OMAP3_DEVICES_H */ -diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h -index 9edf4ca..9cf3e73 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h -@@ -41,6 +41,11 @@ - #define AM33XX_DRAM_ADDR_SPACE_START 0x80000000 - #define AM33XX_DRAM_ADDR_SPACE_END 0xC0000000 - -+/* I2C */ -+#define AM33XX_I2C0_BASE (AM33XX_L4_WKUP_BASE + 0x20B000) -+#define AM33XX_I2C1_BASE (AM33XX_L4_PER_BASE + 0x02A000) -+#define AM33XX_I2C2_BASE (AM33XX_L4_PER_BASE + 0x19C000) -+ - /* GPMC */ - #define AM33XX_GPMC_BASE 0x50000000 - -diff --git a/arch/arm/mach-omap/include/mach/generic.h b/arch/arm/mach-omap/include/mach/generic.h -index f1a3efe..9c474e2 100644 ---- a/arch/arm/mach-omap/include/mach/generic.h -+++ b/arch/arm/mach-omap/include/mach/generic.h -@@ -27,6 +27,12 @@ - #define cpu_is_omap4xxx() (0) - #endif - -+#ifdef CONFIG_ARCH_AM33XX -+#define cpu_is_am33xx() (1) -+#else -+#define cpu_is_am33xx() (0) -+#endif -+ - extern uint32_t omap_bootinfo[3]; - void omap_save_bootinfo(void); - -diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c -index ecb33ea..19d54ee 100644 ---- a/drivers/i2c/busses/i2c-omap.c -+++ b/drivers/i2c/busses/i2c-omap.c -@@ -245,7 +245,7 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_struct *i2c_omap, int reg) - - static void omap_i2c_unidle(struct omap_i2c_struct *i2c_omap) - { -- if (cpu_is_omap34xx()) { -+ if (cpu_is_omap34xx() || cpu_is_am33xx()) { - omap_i2c_write_reg(i2c_omap, OMAP_I2C_CON_REG, 0); - omap_i2c_write_reg(i2c_omap, OMAP_I2C_PSC_REG, i2c_omap->pscstate); - omap_i2c_write_reg(i2c_omap, OMAP_I2C_SCLL_REG, i2c_omap->scllstate); -@@ -353,7 +353,11 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap) - internal_clk = 9600; - else - internal_clk = 4000; -- fclk_rate = 96000000 / 1000; -+ -+ if (cpu_is_am33xx()) -+ fclk_rate = 48000; -+ else -+ fclk_rate = 96000; - - /* Compute prescaler divisor */ - psc = fclk_rate / internal_clk; -@@ -410,7 +414,7 @@ static int omap_i2c_init(struct omap_i2c_struct *i2c_omap) - OMAP_I2C_IE_AL) | ((i2c_omap->fifo_size) ? - (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); - omap_i2c_write_reg(i2c_omap, OMAP_I2C_IE_REG, i2c_omap->iestate); -- if (cpu_is_omap34xx()) { -+ if (cpu_is_omap34xx() || cpu_is_am33xx()) { - i2c_omap->pscstate = psc; - i2c_omap->scllstate = scll; - i2c_omap->sclhstate = sclh; -@@ -665,7 +669,7 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adapter, - ret = omap_i2c_isr(i2c_omap); - while (ret){ - ret = omap_i2c_isr(i2c_omap); -- if (is_timeout(start, MSECOND)) { -+ if (is_timeout(start, 50 * MSECOND)) { - dev_err(&adapter->dev, - "timed out on polling for " - "open i2c message handling\n"); -@@ -743,7 +747,7 @@ i2c_omap_probe(struct device_d *pdev) - goto err_free_mem; - } - -- if (cpu_is_omap4xxx()) { -+ if (cpu_is_omap4xxx() || cpu_is_am33xx()) { - i2c_omap->regs = (u8 *)omap4_reg_map; - i2c_omap->reg_shift = 0; - } else { --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0013-beaglebone-configure-I2C-EEPROM.patch b/patches/barebox-2013.07.0/0013-beaglebone-configure-I2C-EEPROM.patch deleted file mode 100644 index 9d43570..0000000 --- a/patches/barebox-2013.07.0/0013-beaglebone-configure-I2C-EEPROM.patch +++ /dev/null @@ -1,38 +0,0 @@ -From c8c5086b65d13a7f59414db2f52c5381c4279bb5 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 14 Jul 2013 14:13:02 +0200 -Subject: [PATCH 13/17] beaglebone: configure I2C EEPROM - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/board.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c -index b3f39ea..ccb7004 100644 ---- a/arch/arm/boards/beaglebone/board.c -+++ b/arch/arm/boards/beaglebone/board.c -@@ -97,11 +97,20 @@ static void beaglebone_eth_init(void) - am33xx_add_cpsw(&cpsw_data); - } - -+static struct i2c_board_info i2c0_devices[] = { -+ { -+ I2C_BOARD_INFO("24c256", 0x50) -+ }, -+}; -+ - static int beaglebone_devices_init(void) - { - am33xx_add_mmc0(NULL); - - am33xx_enable_i2c0_pin_mux(); -+ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); -+ am33xx_add_i2c0(NULL); -+ - beaglebone_eth_init(); - - armlinux_set_bootparams((void *)0x80000100); --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0014-arm-cpuinfo-display-the-core-name-and-version.patch b/patches/barebox-2013.07.0/0014-arm-cpuinfo-display-the-core-name-and-version.patch deleted file mode 100644 index bda2c18..0000000 --- a/patches/barebox-2013.07.0/0014-arm-cpuinfo-display-the-core-name-and-version.patch +++ /dev/null @@ -1,64 +0,0 @@ -From 2eb44063bbe56d7e9e1fe2cd11e3f6addf60e248 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 14 Jul 2013 15:45:03 +0200 -Subject: [PATCH 14/17] arm: cpuinfo: display the core name and version - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/cpu/cpuinfo.c | 33 +++++++++++++++++++++++++++++++++ - 1 file changed, 33 insertions(+) - -diff --git a/arch/arm/cpu/cpuinfo.c b/arch/arm/cpu/cpuinfo.c -index 8aea4b4..260d47b 100644 ---- a/arch/arm/cpu/cpuinfo.c -+++ b/arch/arm/cpu/cpuinfo.c -@@ -31,6 +31,12 @@ - #define CPU_ARCH_ARMv6 8 - #define CPU_ARCH_ARMv7 9 - -+#define ARM_CPU_PART_CORTEX_A5 0xC050 -+#define ARM_CPU_PART_CORTEX_A7 0xC070 -+#define ARM_CPU_PART_CORTEX_A8 0xC080 -+#define ARM_CPU_PART_CORTEX_A9 0xC090 -+#define ARM_CPU_PART_CORTEX_A15 0xC0F0 -+ - static void decode_cache(unsigned long size) - { - int linelen = 1 << ((size & 0x3) + 3); -@@ -154,6 +160,33 @@ static int do_cpuinfo(int argc, char *argv[]) - printf("implementer: %s\narchitecture: %s\n", - implementer, architecture); - -+ if (cpu_arch == CPU_ARCH_ARMv7) { -+ unsigned int major, minor; -+ char *part; -+ major = (mainid >> 20) & 0xf; -+ minor = mainid & 0xf; -+ switch (mainid & 0xfff0) { -+ case ARM_CPU_PART_CORTEX_A5: -+ part = "Cortex-A5"; -+ break; -+ case ARM_CPU_PART_CORTEX_A7: -+ part = "Cortex-A7"; -+ break; -+ case ARM_CPU_PART_CORTEX_A8: -+ part = "Cortex-A8"; -+ break; -+ case ARM_CPU_PART_CORTEX_A9: -+ part = "Cortex-A9"; -+ break; -+ case ARM_CPU_PART_CORTEX_A15: -+ part = "Cortex-A15"; -+ break; -+ default: -+ part = "unknown"; -+ } -+ printf("core: %s r%up%u\n", part, major, minor); -+ } -+ - if (cache & (1 << 24)) { - /* separate I/D cache */ - printf("I-cache: "); --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0015-am33xx-implement-cpu-revision-decoding.patch b/patches/barebox-2013.07.0/0015-am33xx-implement-cpu-revision-decoding.patch deleted file mode 100644 index c4154e9..0000000 --- a/patches/barebox-2013.07.0/0015-am33xx-implement-cpu-revision-decoding.patch +++ /dev/null @@ -1,113 +0,0 @@ -From 6e2126a736cb0aea390a941bbb1e735fab045def Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 14 Jul 2013 16:42:46 +0200 -Subject: [PATCH 15/17] am33xx: implement cpu revision decoding - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/mach-omap/am33xx_generic.c | 34 +++++++++++++++++++++- - arch/arm/mach-omap/include/mach/am33xx-silicon.h | 1 + - arch/arm/mach-omap/include/mach/sys_info.h | 10 +++++-- - 3 files changed, 42 insertions(+), 3 deletions(-) - -diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c -index 45fefb4..18661d7 100644 ---- a/arch/arm/mach-omap/am33xx_generic.c -+++ b/arch/arm/mach-omap/am33xx_generic.c -@@ -1,6 +1,6 @@ - /* - * (C) Copyright 2012 Teresa Gámez, Phytec Messtechnik GmbH -- * (C) Copyright 2012 Jan Luebbe <j.luebbe@pengutronix.de> -+ * (C) Copyright 2012-2013 Jan Luebbe <j.luebbe@pengutronix.de> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as -@@ -37,6 +37,38 @@ void __noreturn reset_cpu(unsigned long addr) - } - - /** -+ * @brief Extract the AM33xx ES revision -+ * -+ * The significance of the CPU revision depends upon the cpu type. -+ * Latest known revision is considered default. -+ * -+ * @return silicon version -+ */ -+u32 get_cpu_rev(void) -+{ -+ u32 version, retval; -+ -+ version = (readl(AM33XX_IDCODE_REG) >> 28) & 0xF; -+ -+ switch (version) { -+ case 0: -+ retval = AM335X_ES1_0; -+ break; -+ case 1: -+ retval = AM335X_ES2_0; -+ break; -+ case 2: -+ /* -+ * Fall through the default case. -+ */ -+ default: -+ retval = AM335X_ES2_1; -+ } -+ -+ return retval; -+} -+ -+/** - * @brief Get the upper address of current execution - * - * we can use this to figure out if we are running in SRAM / -diff --git a/arch/arm/mach-omap/include/mach/am33xx-silicon.h b/arch/arm/mach-omap/include/mach/am33xx-silicon.h -index 9cf3e73..06035c4 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-silicon.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-silicon.h -@@ -65,6 +65,7 @@ - - /* CTRL */ - #define AM33XX_CTRL_BASE (AM33XX_L4_WKUP_BASE + 0x210000) -+#define AM33XX_IDCODE_REG (AM33XX_CTRL_BASE + 0x600) - - /* Watchdog Timer */ - #define AM33XX_WDT_BASE 0x44E35000 -diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h -index 4d9b138..fce5895 100644 ---- a/arch/arm/mach-omap/include/mach/sys_info.h -+++ b/arch/arm/mach-omap/include/mach/sys_info.h -@@ -40,6 +40,7 @@ - #define CPU_1710 0x1710 - #define CPU_2420 0x2420 - #define CPU_2430 0x2430 -+#define CPU_3350 0x3350 - #define CPU_3430 0x3430 - #define CPU_3630 0x3630 - -@@ -54,6 +55,10 @@ - #define OMAP34XX_ES3 cpu_revision(CPU_3430, 3) - #define OMAP34XX_ES3_1 cpu_revision(CPU_3430, 4) - -+#define AM335X_ES1_0 cpu_revision(CPU_3350, 0) -+#define AM335X_ES2_0 cpu_revision(CPU_3350, 1) -+#define AM335X_ES2_1 cpu_revision(CPU_3350, 2) -+ - #define OMAP36XX_ES1 cpu_revision(CPU_3630, 0) - #define OMAP36XX_ES1_1 cpu_revision(CPU_3630, 1) - #define OMAP36XX_ES1_2 cpu_revision(CPU_3630, 2) -@@ -76,8 +81,9 @@ - /** - * Hawkeye definitions to identify silicon families - */ --#define OMAP_HAWKEYE_34XX 0xB7AE --#define OMAP_HAWKEYE_36XX 0xB891 -+#define OMAP_HAWKEYE_34XX 0xB7AE /* OMAP34xx */ -+#define OMAP_HAWKEYE_36XX 0xB891 /* OMAP36xx */ -+#define OMAP_HAWKEYE_335X 0xB944 /* AM335x */ - - /** These are implemented by the System specific code in omapX-generic.c */ - u32 get_cpu_type(void); --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0016-beaglebone-split-out-DDR2-init-for-BB-White.patch b/patches/barebox-2013.07.0/0016-beaglebone-split-out-DDR2-init-for-BB-White.patch deleted file mode 100644 index a74892c..0000000 --- a/patches/barebox-2013.07.0/0016-beaglebone-split-out-DDR2-init-for-BB-White.patch +++ /dev/null @@ -1,417 +0,0 @@ -From 425a24f42a726b6dc30d23c474dcacbb719820c5 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 14 Jul 2013 18:22:51 +0200 -Subject: [PATCH 16/17] beaglebone: split out DDR2 init for BB White - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/Makefile | 2 +- - arch/arm/boards/beaglebone/ddr.h | 1 + - arch/arm/boards/beaglebone/ddr2.c | 178 +++++++++++++++++++++++++++++++++ - arch/arm/boards/beaglebone/lowlevel.c | 175 +------------------------------- - 4 files changed, 184 insertions(+), 172 deletions(-) - create mode 100644 arch/arm/boards/beaglebone/ddr.h - create mode 100644 arch/arm/boards/beaglebone/ddr2.c - -diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile -index 092c31d..7ec0c8b 100644 ---- a/arch/arm/boards/beaglebone/Makefile -+++ b/arch/arm/boards/beaglebone/Makefile -@@ -1,2 +1,2 @@ --lwl-y += lowlevel.o -+lwl-y += lowlevel.o ddr2.o - obj-y += board.o -diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h -new file mode 100644 -index 0000000..d2f0c95 ---- /dev/null -+++ b/arch/arm/boards/beaglebone/ddr.h -@@ -0,0 +1 @@ -+void beaglebone_config_ddr2(void); -diff --git a/arch/arm/boards/beaglebone/ddr2.c b/arch/arm/boards/beaglebone/ddr2.c -new file mode 100644 -index 0000000..42a099d ---- /dev/null -+++ b/arch/arm/boards/beaglebone/ddr2.c -@@ -0,0 +1,178 @@ -+#include <init.h> -+#include <sizes.h> -+#include <io.h> -+#include <asm/armlinux.h> -+#include <asm/barebox-arm-head.h> -+#include <asm/barebox-arm.h> -+#include <mach/am33xx-silicon.h> -+#include <mach/am33xx-clock.h> -+ -+/* AM335X EMIF Register values */ -+#define EMIF_SDMGT 0x80000000 -+#define EMIF_SDRAM 0x00004650 -+#define EMIF_PHYCFG 0x2 -+#define DDR_PHY_RESET (0x1 << 10) -+#define DDR_FUNCTIONAL_MODE_EN 0x1 -+#define DDR_PHY_READY (0x1 << 2) -+#define VTP_CTRL_READY (0x1 << 5) -+#define VTP_CTRL_ENABLE (0x1 << 6) -+#define VTP_CTRL_LOCK_EN (0x1 << 4) -+#define VTP_CTRL_START_EN (0x1) -+#define DDR2_RATIO 0x80 /* for mDDR */ -+#define CMD_FORCE 0x00 /* common #def */ -+#define CMD_DELAY 0x00 -+ -+#define EMIF_READ_LATENCY 0x05 -+#define EMIF_TIM1 0x0666B3D6 -+#define EMIF_TIM2 0x143731DA -+#define EMIF_TIM3 0x00000347 -+#define EMIF_SDCFG 0x43805332 -+#define EMIF_SDREF 0x0000081a -+#define DDR2_DLL_LOCK_DIFF 0x0 -+#define DDR2_RD_DQS 0x12 -+#define DDR2_PHY_FIFO_WE 0x80 -+ -+#define DDR2_INVERT_CLKOUT 0x00 -+#define DDR2_WR_DQS 0x00 -+#define DDR2_PHY_WRLVL 0x00 -+#define DDR2_PHY_GATELVL 0x00 -+#define DDR2_PHY_WR_DATA 0x40 -+#define PHY_RANK0_DELAY 0x01 -+#define PHY_DLL_LOCK_DIFF 0x0 -+#define DDR_IOCTRL_VALUE 0x18B -+ -+static void beaglebone_data_macro_config_ddr2(int dataMacroNum) -+{ -+ u32 BaseAddrOffset = 0x00; -+ -+ if (dataMacroNum == 1) -+ BaseAddrOffset = 0xA4; -+ -+ __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) -+ |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), -+ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_RD_DQS>>2, -+ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); -+ __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) -+ |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), -+ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_WR_DQS>>2, -+ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); -+ __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) -+ |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), -+ (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_PHY_WRLVL>>2, -+ (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); -+ __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) -+ |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), -+ (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_PHY_GATELVL>>2, -+ (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); -+ __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) -+ |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), -+ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_PHY_FIFO_WE>>2, -+ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); -+ __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) -+ |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), -+ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_PHY_WR_DATA>>2, -+ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); -+ __raw_writel(PHY_DLL_LOCK_DIFF, -+ (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); -+} -+ -+static void beaglebone_cmd_macro_config_ddr2(void) -+{ -+ __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); -+ __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); -+ __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); -+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); -+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); -+ -+ __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); -+ __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); -+ __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); -+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); -+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); -+ -+ __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); -+ __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); -+ __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); -+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); -+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); -+} -+ -+static void beaglebone_config_vtp_ddr2(void) -+{ -+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, -+ AM33XX_VTP0_CTRL_REG); -+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), -+ AM33XX_VTP0_CTRL_REG); -+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, -+ AM33XX_VTP0_CTRL_REG); -+ -+ /* Poll for READY */ -+ while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); -+} -+ -+static void beaglebone_config_emif_ddr2(void) -+{ -+ u32 i; -+ -+ /*Program EMIF0 CFG Registers*/ -+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); -+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); -+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); -+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); -+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); -+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); -+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); -+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); -+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); -+ -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); -+ -+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); -+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ -+ __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); -+ __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); -+ -+ for (i = 0; i < 5000; i++) { -+ -+ } -+ -+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); -+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ -+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); -+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); -+ -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); -+} -+ -+void beaglebone_config_ddr2(void) -+{ -+ enable_ddr_clocks(); -+ -+ beaglebone_config_vtp_ddr2(); -+ -+ beaglebone_cmd_macro_config_ddr2(); -+ beaglebone_data_macro_config_ddr2(0); -+ beaglebone_data_macro_config_ddr2(1); -+ -+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); -+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); -+ -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); -+ -+ __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); -+ __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); -+ -+ beaglebone_config_emif_ddr2(); -+} -diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c -index 59d9ff1..282b471 100644 ---- a/arch/arm/boards/beaglebone/lowlevel.c -+++ b/arch/arm/boards/beaglebone/lowlevel.c -@@ -13,6 +13,8 @@ - #include <mach/am33xx-mux.h> - #include <mach/wdt.h> - -+#include "ddr.h" -+ - /* UART Defines */ - #define UART_SYSCFG_OFFSET (0x54) - #define UART_SYSSTS_OFFSET (0x58) -@@ -21,176 +23,6 @@ - #define UART_CLK_RUNNING_MASK 0x1 - #define UART_SMART_IDLE_EN (0x1 << 0x3) - --/* AM335X EMIF Register values */ --#define EMIF_SDMGT 0x80000000 --#define EMIF_SDRAM 0x00004650 --#define EMIF_PHYCFG 0x2 --#define DDR_PHY_RESET (0x1 << 10) --#define DDR_FUNCTIONAL_MODE_EN 0x1 --#define DDR_PHY_READY (0x1 << 2) --#define VTP_CTRL_READY (0x1 << 5) --#define VTP_CTRL_ENABLE (0x1 << 6) --#define VTP_CTRL_LOCK_EN (0x1 << 4) --#define VTP_CTRL_START_EN (0x1) --#define DDR2_RATIO 0x80 /* for mDDR */ --#define CMD_FORCE 0x00 /* common #def */ --#define CMD_DELAY 0x00 -- --#define EMIF_READ_LATENCY 0x05 --#define EMIF_TIM1 0x0666B3D6 --#define EMIF_TIM2 0x143731DA --#define EMIF_TIM3 0x00000347 --#define EMIF_SDCFG 0x43805332 --#define EMIF_SDREF 0x0000081a --#define DDR2_DLL_LOCK_DIFF 0x0 --#define DDR2_RD_DQS 0x12 --#define DDR2_PHY_FIFO_WE 0x80 -- --#define DDR2_INVERT_CLKOUT 0x00 --#define DDR2_WR_DQS 0x00 --#define DDR2_PHY_WRLVL 0x00 --#define DDR2_PHY_GATELVL 0x00 --#define DDR2_PHY_WR_DATA 0x40 --#define PHY_RANK0_DELAY 0x01 --#define PHY_DLL_LOCK_DIFF 0x0 --#define DDR_IOCTRL_VALUE 0x18B -- --static void beaglebone_data_macro_config(int dataMacroNum) --{ -- u32 BaseAddrOffset = 0x00; -- -- if (dataMacroNum == 1) -- BaseAddrOffset = 0xA4; -- -- __raw_writel(((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20) -- |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)), -- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); -- __raw_writel(DDR2_RD_DQS>>2, -- (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); -- __raw_writel(((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20) -- |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)), -- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); -- __raw_writel(DDR2_WR_DQS>>2, -- (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_1 + BaseAddrOffset)); -- __raw_writel(((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20) -- |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)), -- (AM33XX_DATA0_WRLVL_INIT_RATIO_0 + BaseAddrOffset)); -- __raw_writel(DDR2_PHY_WRLVL>>2, -- (AM33XX_DATA0_WRLVL_INIT_RATIO_1 + BaseAddrOffset)); -- __raw_writel(((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20) -- |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)), -- (AM33XX_DATA0_GATELVL_INIT_RATIO_0 + BaseAddrOffset)); -- __raw_writel(DDR2_PHY_GATELVL>>2, -- (AM33XX_DATA0_GATELVL_INIT_RATIO_1 + BaseAddrOffset)); -- __raw_writel(((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20) -- |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)), -- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); -- __raw_writel(DDR2_PHY_FIFO_WE>>2, -- (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_1 + BaseAddrOffset)); -- __raw_writel(((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20) -- |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)), -- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); -- __raw_writel(DDR2_PHY_WR_DATA>>2, -- (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_1 + BaseAddrOffset)); -- __raw_writel(PHY_DLL_LOCK_DIFF, -- (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); --} -- --static void beaglebone_cmd_macro_config(void) --{ -- __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); -- __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); -- __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); -- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); -- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); -- -- __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); -- __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); -- __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); -- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); -- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); -- -- __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); -- __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); -- __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); -- __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); -- __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); --} -- --static void beaglebone_config_vtp(void) --{ -- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, -- AM33XX_VTP0_CTRL_REG); -- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), -- AM33XX_VTP0_CTRL_REG); -- __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, -- AM33XX_VTP0_CTRL_REG); -- -- /* Poll for READY */ -- while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); --} -- --static void beaglebone_config_emif_ddr2(void) --{ -- u32 i; -- -- /*Program EMIF0 CFG Registers*/ -- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); -- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); -- __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); -- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); -- __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); -- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); -- __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); -- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); -- __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); -- -- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); -- -- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); -- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ -- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); -- __raw_writel(0x00004650, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); -- -- for (i = 0; i < 5000; i++) { -- -- } -- -- /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); -- __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ -- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); -- __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); -- -- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -- __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); --} -- --static void beaglebone_config_ddr(void) --{ -- enable_ddr_clocks(); -- -- beaglebone_config_vtp(); -- -- beaglebone_cmd_macro_config(); -- beaglebone_data_macro_config(0); -- beaglebone_data_macro_config(1); -- -- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); -- __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); -- -- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); -- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); -- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); -- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); -- __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); -- -- __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); -- __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); -- -- beaglebone_config_emif_ddr2(); --} -- - /* - * early system init of muxing and clocks. - */ -@@ -201,7 +33,8 @@ void beaglebone_sram_init(void) - /* Setup the PLLs and the clocks for the peripherals */ - pll_init(MPUPLL_M_500); - -- beaglebone_config_ddr(); -+ if (get_cpu_rev() == AM335X_ES1_0) -+ beaglebone_config_ddr2(); - - /* Enable pin mux */ - am33xx_enable_uart0_pin_mux(); --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch b/patches/barebox-2013.07.0/0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch deleted file mode 100644 index aa5edbf..0000000 --- a/patches/barebox-2013.07.0/0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch +++ /dev/null @@ -1,396 +0,0 @@ -From d8b67830c302eb2cf3d396f1828534850f136771 Mon Sep 17 00:00:00 2001 -From: Jan Luebbe <jlu@pengutronix.de> -Date: Sun, 14 Jul 2013 19:25:39 +0200 -Subject: [PATCH 17/17] beaglebone: add support for beaglebone black with DDR3 - RAM - -Also allow configuration of the DDR PLL from board code - -Signed-off-by: Jan Luebbe <jlu@pengutronix.de> ---- - arch/arm/boards/beaglebone/Makefile | 2 +- - arch/arm/boards/beaglebone/board.c | 47 ++++++- - arch/arm/boards/beaglebone/ddr.h | 1 + - arch/arm/boards/beaglebone/ddr3.c | 155 ++++++++++++++++++++++ - arch/arm/boards/beaglebone/lowlevel.c | 11 +- - arch/arm/mach-omap/am33xx_clock.c | 9 +- - arch/arm/mach-omap/include/mach/am33xx-clock.h | 5 +- - arch/arm/mach-omap/include/mach/am33xx-devices.h | 6 + - 8 files changed, 222 insertions(+), 14 deletions(-) - create mode 100644 arch/arm/boards/beaglebone/ddr3.c - -diff --git a/arch/arm/boards/beaglebone/Makefile b/arch/arm/boards/beaglebone/Makefile -index 7ec0c8b..eb2ffec 100644 ---- a/arch/arm/boards/beaglebone/Makefile -+++ b/arch/arm/boards/beaglebone/Makefile -@@ -1,2 +1,2 @@ --lwl-y += lowlevel.o ddr2.o -+lwl-y += lowlevel.o ddr2.o ddr3.o - obj-y += board.o -diff --git a/arch/arm/boards/beaglebone/board.c b/arch/arm/boards/beaglebone/board.c -index ccb7004..a01fe1b 100644 ---- a/arch/arm/boards/beaglebone/board.c -+++ b/arch/arm/boards/beaglebone/board.c -@@ -26,6 +26,8 @@ - #include <init.h> - #include <driver.h> - #include <envfs.h> -+#include <environment.h> -+#include <globalvar.h> - #include <sizes.h> - #include <io.h> - #include <ns16550.h> -@@ -68,7 +70,11 @@ console_initcall(beaglebone_console_init); - - static int beaglebone_mem_init(void) - { -- omap_add_ram0(SZ_256M); -+ if (get_cpu_rev() == AM335X_ES1_0) { /* white */ -+ omap_add_ram0(SZ_256M); -+ } else { /* black */ -+ omap_add_ram0(SZ_512M); -+ } - - return 0; - } -@@ -103,19 +109,56 @@ static struct i2c_board_info i2c0_devices[] = { - }, - }; - -+static const __maybe_unused struct module_pin_mux mmc1_pin_mux[] = { -+ {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE)}, /* MMC1_DAT0 */ -+ {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE)}, /* MMC1_DAT1 */ -+ {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE)}, /* MMC1_DAT2 */ -+ {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE)}, /* MMC1_DAT3 */ -+ {OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE)}, /* MMC1_DAT4 */ -+ {OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE)}, /* MMC1_DAT5 */ -+ {OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE)}, /* MMC1_DAT6 */ -+ {OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE)}, /* MMC1_DAT7 */ -+ {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ -+ {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ -+ {-1}, -+}; -+ - static int beaglebone_devices_init(void) - { -+ bool black = get_cpu_rev() != AM335X_ES1_0; -+ -+ am33xx_enable_mmc0_pin_mux(); - am33xx_add_mmc0(NULL); - -+ if (black) { -+ configure_module_pin_mux(mmc1_pin_mux); -+ am33xx_add_mmc1(NULL); -+ } -+ - am33xx_enable_i2c0_pin_mux(); - i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); - am33xx_add_i2c0(NULL); - - beaglebone_eth_init(); - -+ return 0; -+} -+device_initcall(beaglebone_devices_init); -+ -+static int beaglebone_env_init(void) -+{ -+ bool black = get_cpu_rev() != AM335X_ES1_0; -+ -+#if defined(CONFIG_GLOBALVAR) -+ globalvar_add_simple("board.variant"); -+ setenv("global.board.variant", black ? "boneblack" : "bone"); -+#endif -+ -+ printf("detected 'BeageBone %s'\n", black ? "Black" : "White"); -+ - armlinux_set_bootparams((void *)0x80000100); - armlinux_set_architecture(MACH_TYPE_BEAGLEBONE); - - return 0; - } --device_initcall(beaglebone_devices_init); -+late_initcall(beaglebone_env_init); -diff --git a/arch/arm/boards/beaglebone/ddr.h b/arch/arm/boards/beaglebone/ddr.h -index d2f0c95..46c2504 100644 ---- a/arch/arm/boards/beaglebone/ddr.h -+++ b/arch/arm/boards/beaglebone/ddr.h -@@ -1 +1,2 @@ - void beaglebone_config_ddr2(void); -+void beaglebone_config_ddr3(void); -diff --git a/arch/arm/boards/beaglebone/ddr3.c b/arch/arm/boards/beaglebone/ddr3.c -new file mode 100644 -index 0000000..643a94d ---- /dev/null -+++ b/arch/arm/boards/beaglebone/ddr3.c -@@ -0,0 +1,155 @@ -+#include <init.h> -+#include <sizes.h> -+#include <io.h> -+#include <asm/armlinux.h> -+#include <asm/barebox-arm-head.h> -+#include <asm/barebox-arm.h> -+#include <mach/am33xx-silicon.h> -+#include <mach/am33xx-clock.h> -+ -+/* AM335X EMIF Register values */ -+#define EMIF_SDMGT 0x80000000 -+#define EMIF_SDRAM 0x00004650 -+#define EMIF_PHYCFG 0x2 -+#define DDR_PHY_RESET (0x1 << 10) -+#define DDR_FUNCTIONAL_MODE_EN 0x1 -+#define DDR_PHY_READY (0x1 << 2) -+#define VTP_CTRL_READY (0x1 << 5) -+#define VTP_CTRL_ENABLE (0x1 << 6) -+#define VTP_CTRL_LOCK_EN (0x1 << 4) -+#define VTP_CTRL_START_EN (0x1) -+#define DDR2_RATIO 0x80 /* for mDDR */ -+#define CMD_FORCE 0x00 /* common #def */ -+#define CMD_DELAY 0x00 -+ -+#define EMIF_READ_LATENCY 0x100007 -+#define EMIF_TIM1 0x0AAAD4DB -+#define EMIF_TIM2 0x266B7FDA -+#define EMIF_TIM3 0x501F867F -+#define EMIF_SDCFG 0x61C05332 -+#define EMIF_SDREF 0xC30 -+#define ZQ_CFG 0x50074BE4 -+#define DDR2_DLL_LOCK_DIFF 0x1 -+#define DDR2_RD_DQS 0x38 -+#define DDR2_WR_DQS 0x44 -+#define DDR2_PHY_FIFO_WE 0x94 -+#define DDR2_PHY_WR_DATA 0x7D -+ -+#define DDR2_INVERT_CLKOUT 0x0 -+#define PHY_RANK0_DELAY 0x01 -+#define PHY_DLL_LOCK_DIFF 0x0 -+#define DDR_IOCTRL_VALUE 0x18B -+ -+static void beaglebone_data_macro_config_ddr3(int dataMacroNum) -+{ -+ u32 BaseAddrOffset = 0x00; -+ -+ if (dataMacroNum == 1) -+ BaseAddrOffset = 0xA4; -+ -+ __raw_writel(DDR2_RD_DQS, -+ (AM33XX_DATA0_RD_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_WR_DQS, -+ (AM33XX_DATA0_WR_DQS_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_PHY_FIFO_WE, -+ (AM33XX_DATA0_FIFO_WE_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(DDR2_PHY_WR_DATA, -+ (AM33XX_DATA0_WR_DATA_SLAVE_RATIO_0 + BaseAddrOffset)); -+ __raw_writel(PHY_DLL_LOCK_DIFF, -+ (AM33XX_DATA0_DLL_LOCK_DIFF_0 + BaseAddrOffset)); -+} -+ -+static void beaglebone_cmd_macro_config_ddr3(void) -+{ -+ __raw_writel(DDR2_RATIO, AM33XX_CMD0_CTRL_SLAVE_RATIO_0); -+ __raw_writel(CMD_FORCE, AM33XX_CMD0_CTRL_SLAVE_FORCE_0); -+ __raw_writel(CMD_DELAY, AM33XX_CMD0_CTRL_SLAVE_DELAY_0); -+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD0_DLL_LOCK_DIFF_0); -+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD0_INVERT_CLKOUT_0); -+ -+ __raw_writel(DDR2_RATIO, AM33XX_CMD1_CTRL_SLAVE_RATIO_0); -+ __raw_writel(CMD_FORCE, AM33XX_CMD1_CTRL_SLAVE_FORCE_0); -+ __raw_writel(CMD_DELAY, AM33XX_CMD1_CTRL_SLAVE_DELAY_0); -+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD1_DLL_LOCK_DIFF_0); -+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD1_INVERT_CLKOUT_0); -+ -+ __raw_writel(DDR2_RATIO, AM33XX_CMD2_CTRL_SLAVE_RATIO_0); -+ __raw_writel(CMD_FORCE, AM33XX_CMD2_CTRL_SLAVE_FORCE_0); -+ __raw_writel(CMD_DELAY, AM33XX_CMD2_CTRL_SLAVE_DELAY_0); -+ __raw_writel(DDR2_DLL_LOCK_DIFF, AM33XX_CMD2_DLL_LOCK_DIFF_0); -+ __raw_writel(DDR2_INVERT_CLKOUT, AM33XX_CMD2_INVERT_CLKOUT_0); -+} -+ -+static void beaglebone_config_vtp_ddr3(void) -+{ -+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_ENABLE, -+ AM33XX_VTP0_CTRL_REG); -+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) & (~VTP_CTRL_START_EN), -+ AM33XX_VTP0_CTRL_REG); -+ __raw_writel(__raw_readl(AM33XX_VTP0_CTRL_REG) | VTP_CTRL_START_EN, -+ AM33XX_VTP0_CTRL_REG); -+ -+ /* Poll for READY */ -+ while ((__raw_readl(AM33XX_VTP0_CTRL_REG) & VTP_CTRL_READY) != VTP_CTRL_READY); -+} -+ -+static void beaglebone_config_emif_ddr3(void) -+{ -+ u32 i; -+ -+ /*Program EMIF0 CFG Registers*/ -+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1)); -+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_1_SHADOW)); -+ __raw_writel(EMIF_READ_LATENCY, AM33XX_EMIF4_0_REG(DDR_PHY_CTRL_2)); -+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1)); -+ __raw_writel(EMIF_TIM1, AM33XX_EMIF4_0_REG(SDRAM_TIM_1_SHADOW)); -+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2)); -+ __raw_writel(EMIF_TIM2, AM33XX_EMIF4_0_REG(SDRAM_TIM_2_SHADOW)); -+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3)); -+ __raw_writel(EMIF_TIM3, AM33XX_EMIF4_0_REG(SDRAM_TIM_3_SHADOW)); -+ -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); -+ -+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); -+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ -+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); -+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); -+ -+ for (i = 0; i < 5000; i++) { -+ -+ } -+ -+ /* __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL); -+ __raw_writel(EMIF_SDMGT, EMIF0_0_SDRAM_MGMT_CTRL_SHD); */ -+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL)); -+ __raw_writel(EMIF_SDREF, AM33XX_EMIF4_0_REG(SDRAM_REF_CTRL_SHADOW)); -+ -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG)); -+ __raw_writel(EMIF_SDCFG, AM33XX_EMIF4_0_REG(SDRAM_CONFIG2)); -+} -+ -+void beaglebone_config_ddr3(void) -+{ -+ enable_ddr_clocks(); -+ -+ beaglebone_config_vtp_ddr3(); -+ -+ beaglebone_cmd_macro_config_ddr3(); -+ beaglebone_data_macro_config_ddr3(0); -+ beaglebone_data_macro_config_ddr3(1); -+ -+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); -+ __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); -+ -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); -+ __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); -+ -+ __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); -+ __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); -+ -+ beaglebone_config_emif_ddr3(); -+} -diff --git a/arch/arm/boards/beaglebone/lowlevel.c b/arch/arm/boards/beaglebone/lowlevel.c -index 282b471..c1e11a1 100644 ---- a/arch/arm/boards/beaglebone/lowlevel.c -+++ b/arch/arm/boards/beaglebone/lowlevel.c -@@ -31,10 +31,13 @@ void beaglebone_sram_init(void) - u32 regVal, uart_base; - - /* Setup the PLLs and the clocks for the peripherals */ -- pll_init(MPUPLL_M_500); -- -- if (get_cpu_rev() == AM335X_ES1_0) -+ if (get_cpu_rev() == AM335X_ES1_0) { /* white */ -+ pll_init(MPUPLL_M_500, DDRPLL_M_266); - beaglebone_config_ddr2(); -+ } else { /* black */ -+ pll_init(MPUPLL_M_500, DDRPLL_M_400); -+ beaglebone_config_ddr3(); -+ } - - /* Enable pin mux */ - am33xx_enable_uart0_pin_mux(); -@@ -100,6 +103,6 @@ void __bare_init __naked barebox_arm_reset_vector(uint32_t *data) - - beaglebone_board_init(); - -- barebox_arm_entry(0x80000000, SZ_256M, 0); -+ barebox_arm_entry(0x80000000, SZ_256M, 0); /* real RAM setup comes later */ - /* barebox_arm_entry(0x402F0400, 0x4030CE00-0x402F0400, 0); */ /* for SRAM */ - } -diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c -index 9928e9f..e0ba197 100644 ---- a/arch/arm/mach-omap/am33xx_clock.c -+++ b/arch/arm/mach-omap/am33xx_clock.c -@@ -248,7 +248,7 @@ static void per_pll_config(void) - while(__raw_readl(CM_IDLEST_DPLL_PER) != 0x1); - } - --static void ddr_pll_config(void) -+static void ddr_pll_config(int ddrpll_M) - { - u32 clkmode, clksel, div_m2; - -@@ -263,7 +263,7 @@ static void ddr_pll_config(void) - while ((__raw_readl(CM_IDLEST_DPLL_DDR) & 0x00000100) != 0x00000100); - - clksel = clksel & (~0x7ffff); -- clksel = clksel | ((DDRPLL_M << 0x8) | DDRPLL_N); -+ clksel = clksel | ((ddrpll_M << 0x8) | DDRPLL_N); - __raw_writel(clksel, CM_CLKSEL_DPLL_DDR); - - div_m2 = div_m2 & 0xFFFFFFE0; -@@ -288,18 +288,17 @@ void enable_ddr_clocks(void) - PRCM_L3_GCLK_ACTIVITY)); - /* Poll if module is functional */ - while ((__raw_readl(CM_PER_EMIF_CLKCTRL)) != PRCM_MOD_EN); -- - } - - /* - * Configure the PLL/PRCM for necessary peripherals - */ --void pll_init(int mpupll_M) -+void pll_init(int mpupll_M, int ddrpll_M) - { - mpu_pll_config(mpupll_M); - core_pll_config(); - per_pll_config(); -- ddr_pll_config(); -+ ddr_pll_config(ddrpll_M); - /* Enable the required interconnect clocks */ - interface_clocks_enable(); - /* Enable power domain transition */ -diff --git a/arch/arm/mach-omap/include/mach/am33xx-clock.h b/arch/arm/mach-omap/include/mach/am33xx-clock.h -index 968509e..3f86d14 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-clock.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-clock.h -@@ -53,7 +53,8 @@ - - /* DDR Freq is 266 MHZ for now*/ - /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */ --#define DDRPLL_M 266 -+#define DDRPLL_M_266 266 -+#define DDRPLL_M_400 400 - #define DDRPLL_N (OSC - 1) - #define DDRPLL_M2 1 - -@@ -187,7 +188,7 @@ - - #define CM_ALWON_GPMC_CLKCTRL CM_PER_GPMC_CLKCTRL - --extern void pll_init(int mpupll_M); -+extern void pll_init(int mpupll_M, int ddrpll_M); - extern void enable_ddr_clocks(void); - - #endif /* endif _AM33XX_CLOCKS_H_ */ -diff --git a/arch/arm/mach-omap/include/mach/am33xx-devices.h b/arch/arm/mach-omap/include/mach/am33xx-devices.h -index edf8982..1d13d3d 100644 ---- a/arch/arm/mach-omap/include/mach/am33xx-devices.h -+++ b/arch/arm/mach-omap/include/mach/am33xx-devices.h -@@ -31,6 +31,12 @@ static inline struct device_d *am33xx_add_mmc0(struct omap_hsmmc_platform_data * - AM33XX_MMCHS0_BASE, SZ_4K, IORESOURCE_MEM, pdata); - } - -+static inline struct device_d *am33xx_add_mmc1(struct omap_hsmmc_platform_data *pdata) -+{ -+ return add_generic_device("omap4-hsmmc", 1, NULL, -+ AM33XX_MMC1_BASE, SZ_4K, IORESOURCE_MEM, pdata); -+} -+ - static inline struct device_d *am33xx_add_cpsw(struct cpsw_platform_data *cpsw_data) - { - return add_generic_device("cpsw", 0, NULL, --- -1.7.10.4 - diff --git a/patches/barebox-2013.07.0/series b/patches/barebox-2013.07.0/series deleted file mode 100644 index 042cb61..0000000 --- a/patches/barebox-2013.07.0/series +++ /dev/null @@ -1,17 +0,0 @@ -0001-scripts-genenv-remove-empty-files-from-tempdir.patch -0002-scripts-Makefile-do-not-use-obj-variables-for-usersp.patch -0003-console-fix-console-without-CONFIG_PARAMETER.patch -0004-beaglebone-fix-booting.patch -0005-beaglebone-env-use-config-board-instead-of-config.patch -0006-WIP-beaglebone-add-simple-script-to-change-usb-curre.patch -0007-ARM-AM33xx-Add-gpio-support.patch -0008-ARM-AM33xx-Enable-clock-for-all-GPIO-banks.patch -0009-ARM-AM33xx-Make-mpu-pll-configurable-by-lowlevel-boa.patch -0010-arm-omap-store-boot-source-info-from-ROM-loader.patch -0011-i2c-omap-cleanup-cpu_is-functions.patch -0012-ARM-AM33xx-Add-i2c-support-for-AM33xx.patch -0013-beaglebone-configure-I2C-EEPROM.patch -0014-arm-cpuinfo-display-the-core-name-and-version.patch -0015-am33xx-implement-cpu-revision-decoding.patch -0016-beaglebone-split-out-DDR2-init-for-BB-White.patch -0017-beaglebone-add-support-for-beaglebone-black-with-DDR.patch diff --git a/platformconfig b/platformconfig index 19abca6..5368907 100644 --- a/platformconfig +++ b/platformconfig @@ -148,8 +148,8 @@ PTXCONF_CONSOLE_SPEED="115200" # PTXCONF_AT91BOOTSTRAP2 is not set PTXCONF_BAREBOX_ARCH_STRING="arm" PTXCONF_BAREBOX=y -PTXCONF_BAREBOX_VERSION="2013.07.0" -PTXCONF_BAREBOX_MD5="6e60845aa3ebfe4ccc1d834508d8c8c8" +PTXCONF_BAREBOX_VERSION="2013.11.0" +PTXCONF_BAREBOX_MD5="d6b08fc4d2bd65725f6ac2049aeaa427" PTXCONF_BAREBOX_CONFIG="barebox.config" PTXCONF_BAREBOX_EXTRA_ENV=y PTXCONF_BAREBOX_EXTRA_ENV_PATH="${PTXDIST_PLATFORMCONFIGDIR}/barebox-defaultenv" |