add eukrea_cpuimx51 board

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>

11 files changed, 640 insertions, 0 deletions

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 14fd4f10..d075efd8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -70,6 +70,7 @@ board-$(CONFIG_MACH_EDB9315A)			:= edb93xx
 board-$(CONFIG_MACH_EUKREA_CPUIMX25)		:= eukrea_cpuimx25
 board-$(CONFIG_MACH_EUKREA_CPUIMX27)		:= eukrea_cpuimx27
 board-$(CONFIG_MACH_EUKREA_CPUIMX35)		:= eukrea_cpuimx35
+board-$(CONFIG_MACH_EUKREA_CPUIMX51SD)		:= eukrea_cpuimx51
 board-$(CONFIG_MACH_FREESCALE_MX25_3STACK)	:= freescale-mx25-3-stack
 board-$(CONFIG_MACH_FREESCALE_MX35_3STACK)	:= freescale-mx35-3-stack
 board-$(CONFIG_MACH_IMX21ADS)			:= imx21ads
diff --git a/arch/arm/boards/eukrea_cpuimx51/Makefile b/arch/arm/boards/eukrea_cpuimx51/Makefile
new file mode 100644
index 00000000..0f506a38
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/Makefile
@@ -0,0 +1,3 @@
+obj-y += lowlevel_init.o
+obj-y += eukrea_cpuimx51.o
+obj-y += flash_header.o
diff --git a/arch/arm/boards/eukrea_cpuimx51/config.h b/arch/arm/boards/eukrea_cpuimx51/config.h
new file mode 100644
index 00000000..d62e1469
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/config.h
@@ -0,0 +1,24 @@
+/**
+ * @file
+ * @brief Global defintions for the ARM i.MX51 based cpuimx51 board
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#endif	/* __CONFIG_H */
diff --git a/arch/arm/boards/eukrea_cpuimx51/env/bin/init_board b/arch/arm/boards/eukrea_cpuimx51/env/bin/init_board
new file mode 100644
index 00000000..173ecf9b
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/env/bin/init_board
@@ -0,0 +1,20 @@
+#!/bin/sh
+
+if [ -f /env/logo.bmp ]; then
+	bmp /env/logo.bmp
+	fb0.enable=1
+	gpio_set_value 1 1
+elif [ -f /env/logo.bmp.lzo ]; then
+	unlzo /env/logo.bmp.lzo /logo.bmp
+	bmp /logo.bmp
+	fb0.enable=1
+	gpio_set_value 1 1
+fi
+
+if [ -z $eth0.ethaddr ]; then
+	while [ -z $eth0.ethaddr ]; do
+		readline "no MAC address set for eth0. please enter the one found on your board: " eth0.ethaddr
+	done
+	echo -a /env/config "eth0.ethaddr=$eth0.ethaddr"
+	saveenv
+fi
diff --git a/arch/arm/boards/eukrea_cpuimx51/env/config b/arch/arm/boards/eukrea_cpuimx51/env/config
new file mode 100644
index 00000000..51fcdde3
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/env/config
@@ -0,0 +1,58 @@
+#!/bin/sh
+
+# otg port mode : can be 'host' or 'device'
+otg_mode="device"
+# video mode : can be 'CMO-QVGA' or any modefb mode
+# ex : 640x480M-16@60 800x600M-24@60 1024x768M-16@60
+video="CMO-QVGA"
+
+machine=eukrea-cpuimx51
+
+# use 'dhcp' to do dhcp in barebox and in kernel
+# use 'none' if you want to skip kernel ip autoconfiguration
+ip=none
+
+# or set your networking parameters here
+#eth0.ipaddr=a.b.c.d
+#eth0.netmask=a.b.c.d
+#eth0.gateway=a.b.c.d
+#eth0.serverip=a.b.c.d
+
+# can be either 'net' or 'nand'
+kernel_loc=nand
+# can be either 'net', 'nand' or 'initrd'
+rootfs_loc=nand
+
+# rootfs
+rootfs_type=ubifs
+rootfsimage=$machine/rootfs.$rootfs_type
+
+# kernel
+kernelimage_type=uimage
+kernelimage=$machine/uImage-${machine}.bin
+kernelimage=uImage
+
+# barebox and it's env
+bareboximage=$machine/barebox-${machine}.bin
+bareboxenvimage=$machine/bareboxenv-${machine}.bin
+
+nfsroot="$eth0.serverip:/srv/nfs/$machine"
+
+autoboot_timeout=1
+
+if [ x$video = xCMO-QVGA ]; then
+        screen_type="tft"
+else
+        screen_type="dvi"
+fi
+
+bootargs="console=ttymxc0,115200 otg_mode=$otg_mode video=$video screen_type=$screen_type"
+
+nand_parts="256k(barebox)ro,128k(bareboxenv),3M(kernel),-(root)"
+rootfs_mtdblock_nand=3
+nand_device="mxc_nand"
+ubiroot="$machine-rootfs"
+device_type="nand"
+
+# set a fancy prompt (if support is compiled in)
+PS1="\e[1;32mbarebox@\e[1;31m\h:\w\e[0m "
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
new file mode 100644
index 00000000..0847bb1d
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * (c) 2011 Eukrea Electromatique, Eric Bénard <eric@eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <net.h>
+#include <init.h>
+#include <environment.h>
+#include <mach/imx-regs.h>
+#include <fec.h>
+#include <mach/gpio.h>
+#include <asm/armlinux.h>
+#include <generated/mach-types.h>
+#include <partition.h>
+#include <fs.h>
+#include <fcntl.h>
+#include <nand.h>
+#include <spi/spi.h>
+#include <mfd/mc13892.h>
+#include <asm/io.h>
+#include <asm/mmu.h>
+#include <mach/imx-nand.h>
+#include <mach/spi.h>
+#include <mach/generic.h>
+#include <mach/iomux-mx51.h>
+#include <mach/devices-imx51.h>
+
+static struct memory_platform_data ram_pdata = {
+	.name = "ram0",
+	.flags = DEVFS_RDWR,
+};
+
+static struct device_d sdram_dev = {
+	.id       = -1,
+	.name     = "mem",
+	.map_base = 0x90000000,
+	.size     = 256 * 1024 * 1024,
+	.platform_data = &ram_pdata,
+};
+
+static struct fec_platform_data fec_info = {
+	.xcv_type = MII100,
+};
+
+struct imx_nand_platform_data nand_info = {
+	.width		= 1,
+	.hw_ecc		= 1,
+	.flash_bbt	= 1,
+};
+
+static struct pad_desc eukrea_cpuimx51_pads[] = {
+	/* FEC */
+	MX51_PAD_DISP2_DAT1__FEC_RX_ER,
+	MX51_PAD_DISP2_DAT15__FEC_TDATA0,
+	MX51_PAD_DISP2_DAT6__FEC_TDATA1,
+	MX51_PAD_DISP2_DAT7__FEC_TDATA2,
+	MX51_PAD_DISP2_DAT8__FEC_TDATA3,
+	MX51_PAD_DISP2_DAT9__FEC_TX_EN,
+	MX51_PAD_DISP2_DAT10__FEC_COL,
+	MX51_PAD_DISP2_DAT11__FEC_RX_CLK,
+	MX51_PAD_DISP2_DAT12__FEC_RX_DV,
+	MX51_PAD_DISP2_DAT13__FEC_TX_CLK,
+	MX51_PAD_DI2_PIN4__FEC_CRS,
+	MX51_PAD_DI2_PIN2__FEC_MDC,
+	MX51_PAD_DI2_PIN3__FEC_MDIO,
+	MX51_PAD_DISP2_DAT14__FEC_RDATA0,
+	MX51_PAD_DI2_DISP_CLK__FEC_RDATA1,
+	MX51_PAD_DI_GP4__FEC_RDATA2,
+	MX51_PAD_DISP2_DAT0__FEC_RDATA3,
+	MX51_PAD_DI_GP3__FEC_TX_ER,
+	MX51_PAD_EIM_DTACK__GPIO2_31, /* LAN8700 reset pin */
+	/* NAND */
+	MX51_PAD_NANDF_D7__NANDF_D7,
+	MX51_PAD_NANDF_D6__NANDF_D6,
+	MX51_PAD_NANDF_D5__NANDF_D5,
+	MX51_PAD_NANDF_D4__NANDF_D4,
+	MX51_PAD_NANDF_D3__NANDF_D3,
+	MX51_PAD_NANDF_D2__NANDF_D2,
+	MX51_PAD_NANDF_D1__NANDF_D1,
+	MX51_PAD_NANDF_D0__NANDF_D0,
+	MX51_PAD_NANDF_RB0__NANDF_RB0,
+	MX51_PAD_NANDF_RB1__NANDF_RB1,
+	MX51_PAD_NANDF_CS0__NANDF_CS0,
+	MX51_PAD_NANDF_CS1__NANDF_CS1,
+	/* LCD BL */
+	MX51_PAD_DI1_D1_CS__GPIO3_4,
+};
+
+#define GPIO_LAN8700_RESET	(1 * 32 + 31)
+#define GPIO_LCD_BL		(2 * 32 + 4)
+
+#ifdef CONFIG_MMU
+static void eukrea_cpuimx51_mmu_init(void)
+{
+	mmu_init();
+
+	arm_create_section(0x90000000, 0x90000000, 256, PMD_SECT_DEF_CACHED);
+	arm_create_section(0xa0000000, 0x90000000, 256, PMD_SECT_DEF_UNCACHED);
+
+	setup_dma_coherent(0x10000000);
+
+#if TEXT_BASE & (0x100000 - 1)
+#warning cannot create vector section. Adjust TEXT_BASE to a 1M boundary
+#else
+	arm_create_section(0x0,        TEXT_BASE,   1, PMD_SECT_DEF_UNCACHED);
+#endif
+
+	mmu_enable();
+}
+#else
+static void eukrea_cpuimx51_mmu_init(void)
+{
+}
+#endif
+
+static int eukrea_cpuimx51_devices_init(void)
+{
+	eukrea_cpuimx51_mmu_init();
+
+	register_device(&sdram_dev);
+	imx51_add_fec(&fec_info);
+#ifdef CONFIG_MCI_IMX_ESDHC
+	imx51_add_mmc0(NULL);
+#endif
+	imx51_add_nand(&nand_info);
+
+	devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
+	dev_add_bb_dev("self_raw", "self0");
+	devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
+	dev_add_bb_dev("env_raw", "env0");
+
+	gpio_direction_output(GPIO_LAN8700_RESET, 0);
+	gpio_set_value(GPIO_LAN8700_RESET, 1);
+	gpio_direction_output(GPIO_LCD_BL, 0);
+
+	armlinux_add_dram(&sdram_dev);
+	armlinux_set_bootparams((void *)0x90000100);
+	armlinux_set_architecture(MACH_TYPE_EUKREA_CPUIMX51SD);
+
+	return 0;
+}
+
+device_initcall(eukrea_cpuimx51_devices_init);
+
+static int eukrea_cpuimx51_console_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads, ARRAY_SIZE(eukrea_cpuimx51_pads));
+
+	writel(0, 0x73fa8228);
+	writel(0, 0x73fa822c);
+	writel(0, 0x73fa8230);
+	writel(0, 0x73fa8234);
+
+	imx51_add_uart0();
+	return 0;
+}
+
+console_initcall(eukrea_cpuimx51_console_init);
diff --git a/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox
new file mode 100644
index 00000000..0f35e174
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/eukrea_cpuimx51.dox
@@ -0,0 +1,4 @@
+/** @page eukrea_cpuimx51 Eukrea's CPUIMX51
+
+
+*/
diff --git a/arch/arm/boards/eukrea_cpuimx51/flash_header.c b/arch/arm/boards/eukrea_cpuimx51/flash_header.c
new file mode 100644
index 00000000..f953b09b
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/flash_header.c
@@ -0,0 +1,84 @@
+#include <common.h>
+#include <mach/imx-flash-header.h>
+
+extern unsigned long _stext;
+
+void __naked __flash_header_start go(void)
+{
+	__asm__ __volatile__("b exception_vectors\n");
+}
+
+struct imx_dcd_entry __dcd_entry_section dcd_entry[] = {
+	{ .ptr_type = 4, .addr = 0x73fa88a0, .val = 0x00000200, },
+	{ .ptr_type = 4, .addr = 0x73fa850c, .val = 0x000020c5, },
+	{ .ptr_type = 4, .addr = 0x73fa8510, .val = 0x000020c5, },
+	{ .ptr_type = 4, .addr = 0x73fa883c, .val = 0x00000002, },
+	{ .ptr_type = 4, .addr = 0x73fa8848, .val = 0x00000002, },
+	{ .ptr_type = 4, .addr = 0x73fa84b8, .val = 0x000000e7, },
+	{ .ptr_type = 4, .addr = 0x73fa84bc, .val = 0x00000045, },
+	{ .ptr_type = 4, .addr = 0x73fa84c0, .val = 0x00000045, },
+	{ .ptr_type = 4, .addr = 0x73fa84c4, .val = 0x00000045, },
+	{ .ptr_type = 4, .addr = 0x73fa84c8, .val = 0x00000045, },
+	{ .ptr_type = 4, .addr = 0x73fa8820, .val = 0x00000000, },
+	{ .ptr_type = 4, .addr = 0x73fa84a4, .val = 0x00000003, },
+	{ .ptr_type = 4, .addr = 0x73fa84a8, .val = 0x00000003, },
+	{ .ptr_type = 4, .addr = 0x73fa84ac, .val = 0x000000e3, },
+	{ .ptr_type = 4, .addr = 0x73fa84b0, .val = 0x000000e3, },
+	{ .ptr_type = 4, .addr = 0x73fa84b4, .val = 0x000000e3, },
+	{ .ptr_type = 4, .addr = 0x73fa84cc, .val = 0x000000e3, },
+	{ .ptr_type = 4, .addr = 0x73fa84d0, .val = 0x000000e2, },
+	{ .ptr_type = 4, .addr = 0x73fa882c, .val = 0x00000004, },
+	{ .ptr_type = 4, .addr = 0x73fa88a4, .val = 0x00000004, },
+	{ .ptr_type = 4, .addr = 0x73fa88ac, .val = 0x00000004, },
+	{ .ptr_type = 4, .addr = 0x73fa88b8, .val = 0x00000004, },
+	{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0x82a20000, },
+	{ .ptr_type = 4, .addr = 0x83fd9008, .val = 0x82a20000, },
+	{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad0d0, },
+	{ .ptr_type = 4, .addr = 0x83fd9004, .val = 0x3f3584ab, },
+	{ .ptr_type = 4, .addr = 0x83fd900c, .val = 0x3f3584ab, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801a, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801b, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00448019, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x07328018, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x04008008, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008010, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x06328018, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x03808019, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00408019, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008000, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801e, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801f, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0000801d, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0732801c, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0400800c, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008014, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0632801c, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0380801d, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x0040801d, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00008004, },
+	{ .ptr_type = 4, .addr = 0x83fd9000, .val = 0xb2a20000, },
+	{ .ptr_type = 4, .addr = 0x83fd9008, .val = 0xb2a20000, },
+	{ .ptr_type = 4, .addr = 0x83fd9010, .val = 0x000ad6d0, },
+	{ .ptr_type = 4, .addr = 0x83fd9034, .val = 0x90000000, },
+	{ .ptr_type = 4, .addr = 0x83fd9014, .val = 0x00000000, },
+};
+
+#define APP_DEST	0x90000000
+
+struct imx_flash_header __flash_header_section flash_header = {
+	.app_code_jump_vector	= APP_DEST + 0x1000,
+	.app_code_barker	= APP_CODE_BARKER,
+	.app_code_csf		= 0,
+	.dcd_ptr_ptr		= APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd),
+	.super_root_key		= 0,
+	.dcd			= APP_DEST + 0x400 + offsetof(struct imx_flash_header, dcd_barker),
+	.app_dest		= APP_DEST,
+	.dcd_barker		= DCD_BARKER,
+	.dcd_block_len		= sizeof (dcd_entry),
+};
+
+unsigned long __image_len_section barebox_len = 0x40000;
diff --git a/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
new file mode 100644
index 00000000..793104c7
--- /dev/null
+++ b/arch/arm/boards/eukrea_cpuimx51/lowlevel_init.S
@@ -0,0 +1,216 @@
+/*
+ * This code is based on the ecos babbage startup code
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <mach/imx-regs.h>
+#include <mach/clock-imx51.h>
+
+#define ROM_SI_REV_OFFSET                   0x48
+
+.macro setup_pll pll, freq
+	ldr r2, =\pll
+	ldr r1, =0x00001232
+	str r1, [r2, #MX51_PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
+	mov r1, #0x2
+	str r1, [r2, #MX51_PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
+
+	str r3, [r2, #MX51_PLL_DP_OP]
+	str r3, [r2, #MX51_PLL_DP_HFS_OP]
+
+	str r4, [r2, #MX51_PLL_DP_MFD]
+	str r4, [r2, #MX51_PLL_DP_HFS_MFD]
+
+	str r5, [r2, #MX51_PLL_DP_MFN]
+	str r5, [r2, #MX51_PLL_DP_HFS_MFN]
+
+	ldr r1, =0x00001232
+	str r1, [r2, #MX51_PLL_DP_CTL]
+1:	ldr r1, [r2, #MX51_PLL_DP_CTL]
+	ands r1, r1, #0x1
+	beq 1b
+.endm
+
+#define writel(val, reg) \
+	ldr		r0,	=reg;	\
+	ldr		r1,	=val;	\
+	str		r1,   [r0];
+
+#define IMX51_TO_2
+
+.globl board_init_lowlevel
+board_init_lowlevel:
+	mov     r10, lr
+
+	/* explicitly disable L2 cache */
+	mrc 15, 0, r0, c1, c0, 1
+	bic r0, r0, #0x2
+	mcr 15, 0, r0, c1, c0, 1
+
+	/* reconfigure L2 cache aux control reg */
+	mov r0, #0xC0               /* tag RAM */
+	add r0, r0, #0x4    /* data RAM */
+	orr r0, r0, #(1 << 24)    /* disable write allocate delay */
+	orr r0, r0, #(1 << 23)    /* disable write allocate combine */
+	orr r0, r0, #(1 << 22)    /* disable write allocate */
+
+	ldr r1, =MX51_IROM_BASE_ADDR
+	ldr r3, [r1, #ROM_SI_REV_OFFSET]
+	cmp r3, #0x10
+	orrls r0, r0, #(1 << 25)    /* disable write combine for TO 2 and lower revs */
+
+	mcr 15, 1, r0, c9, c0, 2
+
+	ldr r0, =MX51_CCM_BASE_ADDR
+
+	/* Gate of clocks to the peripherals first */
+	ldr r1, =0x3FFFFFFF
+	str r1, [r0, #MX51_CCM_CCGR0]
+	ldr r1, =0x0
+	str r1, [r0, #MX51_CCM_CCGR1]
+	str r1, [r0, #MX51_CCM_CCGR2]
+	str r1, [r0, #MX51_CCM_CCGR3]
+
+	ldr r1, =0x00030000
+	str r1, [r0, #MX51_CCM_CCGR4]
+	ldr r1, =0x00FFF030
+	str r1, [r0, #MX51_CCM_CCGR5]
+	ldr r1, =0x00000300
+	str r1, [r0, #MX51_CCM_CCGR6]
+
+	/* Disable IPU and HSC dividers */
+	mov r1, #0x60000
+	str r1, [r0, #MX51_CCM_CCDR]
+
+#ifdef IMX51_TO_2
+	/* Make sure to switch the DDR away from PLL 1 */
+	ldr r1, =0x19239145
+	str r1, [r0, #MX51_CCM_CBCDR]
+	/* make sure divider effective */
+1:	ldr r1, [r0, #MX51_CCM_CDHIPR]
+	cmp r1, #0x0
+	bne 1b
+#endif
+
+	/* Switch ARM to step clock */
+	mov r1, #0x4
+	str r1, [r0, #MX51_CCM_CCSR]
+
+	mov r3, #MX51_PLL_DP_OP_800
+	mov r4, #MX51_PLL_DP_MFD_800
+	mov r5, #MX51_PLL_DP_MFN_800
+	setup_pll MX51_PLL1_BASE_ADDR
+
+	mov r3, #MX51_PLL_DP_OP_665
+	mov r4, #MX51_PLL_DP_MFD_665
+	mov r5, #MX51_PLL_DP_MFN_665
+	setup_pll MX51_PLL3_BASE_ADDR
+
+	/* Switch peripheral to PLL 3 */
+	ldr r1, =0x000010C0
+	str r1, [r0, #MX51_CCM_CBCMR]
+	ldr r1, =0x13239145
+	str r1, [r0, #MX51_CCM_CBCDR]
+
+	mov r3, #MX51_PLL_DP_OP_665
+	mov r4, #MX51_PLL_DP_MFD_665
+	mov r5, #MX51_PLL_DP_MFN_665
+	setup_pll MX51_PLL2_BASE_ADDR
+
+	/* Switch peripheral to PLL2 */
+	ldr r1, =0x19239145
+	str r1, [r0, #MX51_CCM_CBCDR]
+	ldr r1, =0x000020C0
+	str r1, [r0, #MX51_CCM_CBCMR]
+
+	mov r3, #MX51_PLL_DP_OP_216
+	mov r4, #MX51_PLL_DP_MFD_216
+	mov r5, #MX51_PLL_DP_MFN_216
+	setup_pll MX51_PLL3_BASE_ADDR
+
+	/* Set the platform clock dividers */
+	ldr r2, =MX51_ARM_BASE_ADDR
+	ldr r1, =0x00000124
+	str r1, [r2, #0x14]
+
+	/* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+	ldr r1, =MX51_IROM_BASE_ADDR
+	ldr r3, [r1, #ROM_SI_REV_OFFSET]
+	cmp r3, #0x10
+	movls r1, #0x1
+	movhi r1, #0
+	str r1, [r0, #MX51_CCM_CACRR]
+
+	/* Switch ARM back to PLL 1 */
+	mov r1, #0
+	str r1, [r0,  #MX51_CCM_CCSR]
+
+        /* setup the rest */
+        /* Use lp_apm (24MHz) source for perclk */
+#ifdef IMX51_TO_2
+        ldr r1, =0x000020C2
+        str r1, [r0, #MX51_CCM_CBCMR]
+        // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
+        ldr r1, =0x59239100
+        str r1, [r0, #MX51_CCM_CBCDR]
+#else
+        ldr r1, =0x0000E3C2
+        str r1, [r0, #MX51_CCM_CBCMR]
+        // emi=ahb, all perclk dividers are 1 since using 24MHz
+        // DDR divider=6 to have 665/6=110MHz
+        ldr r1, =0x013B9100
+        str r1, [r0, #MX51_CCM_CBCDR]
+#endif
+
+        /* Restore the default values in the Gate registers */
+        ldr r1, =0xFFFFFFFF
+        str r1, [r0, #MX51_CCM_CCGR0]
+        str r1, [r0, #MX51_CCM_CCGR1]
+        str r1, [r0, #MX51_CCM_CCGR2]
+        str r1, [r0, #MX51_CCM_CCGR3]
+        str r1, [r0, #MX51_CCM_CCGR4]
+        str r1, [r0, #MX51_CCM_CCGR5]
+        str r1, [r0, #MX51_CCM_CCGR6]
+
+        /* Use PLL 2 for UART's, get 66.5MHz from it */
+        ldr r1, =0xA5A2A020
+        str r1, [r0, #MX51_CCM_CSCMR1]
+        ldr r1, =0x00C30321
+        str r1, [r0, #MX51_CCM_CSCDR1]
+
+        /* make sure divider effective */
+    1:  ldr r1, [r0, #MX51_CCM_CDHIPR]
+        cmp r1, #0x0
+        bne 1b
+
+	mov r1, #0x0
+	str r1, [r0, #MX51_CCM_CCDR]
+
+	writel(0x1, 0x73fa8074)
+	ldr	r0, =0x73f88000
+	ldr	r1, [r0]
+	orr	r1, #0x40
+	str	r1, [r0]
+
+	ldr	r0, =0x73f88004
+	ldr	r1, [r0]
+	orr	r1, #0x40
+	str	r1, [r0]
+
+	mov	pc, r10
+
diff --git a/arch/arm/configs/eukrea_cpuimx51_defconfig b/arch/arm/configs/eukrea_cpuimx51_defconfig
new file mode 100644
index 00000000..a9fca844
--- /dev/null
+++ b/arch/arm/configs/eukrea_cpuimx51_defconfig
@@ -0,0 +1,45 @@
+CONFIG_ARCH_IMX=y
+CONFIG_ARCH_IMX_INTERNAL_BOOT=y
+CONFIG_ARCH_IMX51=y
+CONFIG_MACH_EUKREA_CPUIMX51SD=y
+CONFIG_AEABI=y
+CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
+CONFIG_MALLOC_SIZE=0x2000000
+CONFIG_LONGHELP=y
+CONFIG_GLOB=y
+CONFIG_HUSH_FANCY_PROMPT=y
+CONFIG_CMDLINE_EDITING=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_PARTITION=y
+CONFIG_DEFAULT_ENVIRONMENT_GENERIC=y
+CONFIG_DEFAULT_ENVIRONMENT_PATH="defaultenv arch/arm/boards/eukrea_cpuimx51/env"
+CONFIG_CMD_EDIT=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SAVEENV=y
+CONFIG_CMD_LOADENV=y
+CONFIG_CMD_EXPORT=y
+CONFIG_CMD_PRINTENV=y
+CONFIG_CMD_READLINE=y
+CONFIG_CMD_ECHO_E=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_MTEST=y
+CONFIG_CMD_FLASH=y
+CONFIG_CMD_BOOTM_ZLIB=y
+CONFIG_CMD_BOOTM_BZLIB=y
+CONFIG_CMD_BOOTM_SHOW_TYPE=y
+CONFIG_CMD_RESET=y
+CONFIG_CMD_GO=y
+CONFIG_CMD_TIMEOUT=y
+CONFIG_CMD_PARTITION=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_UNLZO=y
+CONFIG_NET=y
+CONFIG_NET_DHCP=y
+CONFIG_NET_PING=y
+CONFIG_NET_TFTP=y
+CONFIG_DRIVER_NET_FEC_IMX=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_NAND_IMX=y
+CONFIG_UBI=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 54545058..f497d35f 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -5,6 +5,7 @@ config ARCH_TEXT_BASE
 	default 0x83f00000 if MACH_EUKREA_CPUIMX25
 	default 0xa0000000 if MACH_EUKREA_CPUIMX27
 	default 0x87f00000 if MACH_EUKREA_CPUIMX35
+	default 0x97f00000 if MACH_EUKREA_CPUIMX51SD
 	default 0x08f00000 if MACH_MX1ADS
 	default 0xc0000000 if MACH_IMX21ADS
 	default 0xa0000000 if MACH_IMX27ADS
@@ -25,6 +26,7 @@ config BOARDINFO
 	default "Eukrea CPUIMX25" if MACH_EUKREA_CPUIMX25
 	default "Eukrea CPUIMX27" if MACH_EUKREA_CPUIMX27
 	default "Eukrea CPUIMX35" if MACH_EUKREA_CPUIMX35
+	default "Eukrea CPUIMX51" if MACH_EUKREA_CPUIMX51SD
 	default "Freescale i.MX21 ADS" if MACH_IMX21ADS
 	default "Freescale i.MX27 ADS" if MACH_IMX27ADS
 	default "Freescale MX35 3Stack" if MACH_FREESCALE_MX35_3STACK
@@ -383,6 +385,14 @@ config MACH_FREESCALE_MX51_PDK
 	select HAVE_MMU
 	select MACH_HAS_LOWLEVEL_INIT
 
+config MACH_EUKREA_CPUIMX51SD
+	bool "EUKREA CPUIMX51"
+	select HAVE_MMU
+	select MACH_HAS_LOWLEVEL_INIT
+	help
+	  Say Y here if you are using Eukrea's CPUIMX51 equipped
+	  with a Freescale i.MX51 Processor
+
 endchoice
 
 endif