v7a: tf-a: update to v2.4

Trusted Firmware-A v2.4 was released last month and adds amongst others,
enhancements to make use of the trusted boot chain possible with
upstream components.

The patch stack has now been posted upstream in hope we can eventually
drop it:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7339
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7340

For now, it was rebased with following modifications:
  - Sync with upstream device tree and new TF-A requirements
  - CLK_ETH_PLL4P is enabled for possible PTP use

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

3 files changed, 494 insertions, 0 deletions

diff --git a/configs/platform-v7a/patches/tf-a-v2.4/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch b/configs/platform-v7a/patches/tf-a-v2.4/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
new file mode 100644
index 0000000..cc8dd07
--- /dev/null
+++ b/configs/platform-v7a/patches/tf-a-v2.4/0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
@@ -0,0 +1,419 @@
+From: Ahmad Fatoum <a.fatoum@pengutronix.de>
+Date: Wed, 29 Jan 2020 16:04:18 +0100
+Subject: [PATCH] fdts: stm32mp1: add support for Linux Automation MC-1 board
+
+The Linux Automation MC-1 is a SBC built around the Octavo Systems
+OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and
+PMIC. The board has eMMC and a SD slot for storage.
+
+The SDRAM calibration values are taken as is from the DKx boards, which
+seem to be suitable for operation at German room temperature.
+
+This is deemed ok for now, but for use in the field, the SiP will likely
+need to have its timings determined in a climate chamber.
+
+Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0
+Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
+---
+ fdts/stm32mp157c-lxa-mc1.dts | 106 +++++++++++++++++
+ fdts/stm32mp15xx-osd32.dtsi  | 278 +++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 384 insertions(+)
+ create mode 100644 fdts/stm32mp157c-lxa-mc1.dts
+ create mode 100644 fdts/stm32mp15xx-osd32.dtsi
+
+diff --git a/fdts/stm32mp157c-lxa-mc1.dts b/fdts/stm32mp157c-lxa-mc1.dts
+new file mode 100644
+index 000000000000..47b96852496f
+--- /dev/null
++++ b/fdts/stm32mp157c-lxa-mc1.dts
+@@ -0,0 +1,106 @@
++/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
++/*
++ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
++ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
++ */
++
++/dts-v1/;
++
++#include "stm32mp157.dtsi"
++#include "stm32mp15xc.dtsi"
++#include "stm32mp15xx-osd32.dtsi"
++#include "stm32mp15xxac-pinctrl.dtsi"
++
++/ {
++	model = "Linux Automation MC-1 board";
++	compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
++
++	aliases {
++		mmc0 = &sdmmc1;
++		mmc1 = &sdmmc2;
++		serial0 = &uart4;
++	};
++
++	chosen {
++		stdout-path = &uart4;
++	};
++
++	led-act {
++		compatible = "gpio-leds";
++
++		led-green {
++			label = "mc1:green:act";
++			gpios = <&gpioa 13 1>;
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_3v3: regulator_3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "3V3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&v3v3>;
++	};
++};
++
++&sdmmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc1_b4_pins_a>;
++	bus-width = <4>;
++	cd-gpios = <&gpioh 3 1>;
++	disable-wp;
++	no-1-8-v;
++	st,neg-edge;
++	vmmc-supply = <&reg_3v3>;
++	status = "okay";
++};
++
++&sdmmc1_b4_pins_a {
++	/*
++	 * board lacks external pull-ups on SDMMC lines. Class 10 SD refuses to
++	 * work, thus enable internal pull-ups.
++	 */
++	pins1 {
++		/delete-property/ bias-disable;
++		bias-pull-up;
++	};
++	pins2 {
++		/delete-property/ bias-disable;
++		bias-pull-up;
++	};
++};
++
++&sdmmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc2_b4_pins_a &mc1_sdmmc2_d47_pins_b>;
++	bus-width = <8>;
++	no-1-8-v;
++	no-sd;
++	no-sdio;
++	non-removable;
++	st,neg-edge;
++	vmmc-supply = <&reg_3v3>;
++	status = "okay";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4_pins_a>;
++	status = "okay";
++};
++
++&pinctrl {
++	mc1_sdmmc2_d47_pins_b: mc1-sdmmc2-d47-1 {
++		pins {
++			pinmux = <STM32_PINMUX('A', 8, AF9)>,  /* SDMMC2_D4 */
++				 <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */
++				 <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */
++				 <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */
++			slew-rate = <1>;
++			drive-push-pull;
++			bias-disable;
++		};
++	};
++};
+diff --git a/fdts/stm32mp15xx-osd32.dtsi b/fdts/stm32mp15xx-osd32.dtsi
+new file mode 100644
+index 000000000000..9db838ea6b56
+--- /dev/null
++++ b/fdts/stm32mp15xx-osd32.dtsi
+@@ -0,0 +1,278 @@
++/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
++/*
++ * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
++ * Copyright (C) 2020 Ahmad Fatoum, Pengutronix
++ */
++
++#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
++#include "stm32mp15-pinctrl.dtsi"
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_pins_a>;
++	clock-frequency = <400000>;
++	i2c-scl-rising-time-ns = <185>;
++	i2c-scl-falling-time-ns = <20>;
++	status = "okay";
++
++	pmic: stpmic@33 {
++		compatible = "st,stpmic1";
++		reg = <0x33>;
++		interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
++		interrupt-controller;
++		#interrupt-cells = <2>;
++
++		regulators {
++			compatible = "st,stpmic1-regulators";
++
++			ldo1-supply = <&v3v3>;
++			ldo6-supply = <&v3v3>;
++			pwr_sw1-supply = <&bst_out>;
++
++			vddcore: buck1 {
++				regulator-name = "vddcore";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-always-on;
++				regulator-initial-mode = <0>;
++				regulator-over-current-protection;
++			};
++
++			vdd_ddr: buck2 {
++				regulator-name = "vdd_ddr";
++				regulator-min-microvolt = <1350000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-always-on;
++				regulator-initial-mode = <0>;
++				regulator-over-current-protection;
++			};
++
++			vdd: buck3 {
++				regulator-name = "vdd";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				st,mask-reset;
++				regulator-initial-mode = <0>;
++				regulator-over-current-protection;
++			};
++
++			v3v3: buck4 {
++				regulator-name = "v3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-over-current-protection;
++				regulator-initial-mode = <0>;
++			};
++
++			v1v8_audio: ldo1 {
++				regulator-name = "v1v8_audio";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++			};
++
++			v3v3_hdmi: ldo2 {
++				regulator-name = "v3v3_hdmi";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++			};
++
++			vtt_ddr: ldo3 {
++				regulator-name = "vtt_ddr";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <750000>;
++				regulator-always-on;
++				regulator-over-current-protection;
++			};
++
++			vdd_usb: ldo4 {
++				regulator-name = "vdd_usb";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++			};
++
++			vdda: ldo5 {
++				regulator-name = "vdda";
++				regulator-min-microvolt = <2900000>;
++				regulator-max-microvolt = <2900000>;
++				regulator-boot-on;
++			};
++
++			v1v2_hdmi: ldo6 {
++				regulator-name = "v1v2_hdmi";
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-always-on;
++			};
++
++			vref_ddr: vref_ddr {
++				regulator-name = "vref_ddr";
++				regulator-always-on;
++				regulator-over-current-protection;
++			};
++
++			bst_out: boost {
++				regulator-name = "bst_out";
++			};
++
++			vbus_otg: pwr_sw1 {
++				regulator-name = "vbus_otg";
++				regulator-active-discharge;
++			};
++
++			vbus_sw: pwr_sw2 {
++				regulator-name = "vbus_sw";
++				regulator-active-discharge;
++			};
++		};
++
++		pmic_watchdog: watchdog {
++			compatible = "st,stpmic1-wdt";
++			status = "disabled";
++		};
++	};
++};
++
++&rng1 {
++	status = "okay";
++};
++
++/* ATF Specific */
++#include <dt-bindings/clock/stm32mp1-clksrc.h>
++
++/ {
++	aliases {
++		gpio0 = &gpioa;
++		gpio1 = &gpiob;
++		gpio2 = &gpioc;
++		gpio3 = &gpiod;
++		gpio4 = &gpioe;
++		gpio5 = &gpiof;
++		gpio6 = &gpiog;
++		gpio7 = &gpioh;
++		gpio8 = &gpioi;
++		gpio25 = &gpioz;
++		i2c3 = &i2c4;
++	};
++};
++
++&bsec {
++	board_id: board_id@ec {
++		reg = <0xec 0x4>;
++		st,non-secure-otp;
++	};
++};
++
++&clk_hse {
++	st,digbypass;
++};
++
++&cpu0{
++	cpu-supply = <&vddcore>;
++};
++
++&cpu1{
++	cpu-supply = <&vddcore>;
++};
++
++/* CLOCK init */
++&rcc {
++	secure-status = "disabled";
++	st,clksrc = <
++		CLK_MPU_PLL1P
++		CLK_AXI_PLL2P
++		CLK_MCU_PLL3P
++		CLK_PLL12_HSE
++		CLK_PLL3_HSE
++		CLK_PLL4_HSE
++		CLK_RTC_LSE
++		CLK_MCO1_DISABLED
++		CLK_MCO2_DISABLED
++	>;
++
++	st,clkdiv = <
++		1 /*MPU*/
++		0 /*AXI*/
++		0 /*MCU*/
++		1 /*APB1*/
++		1 /*APB2*/
++		1 /*APB3*/
++		1 /*APB4*/
++		2 /*APB5*/
++		23 /*RTC*/
++		0 /*MCO1*/
++		0 /*MCO2*/
++	>;
++
++	st,pkcs = <
++		CLK_CKPER_HSE
++		CLK_FMC_ACLK
++		CLK_QSPI_ACLK
++		CLK_ETH_PLL4P
++		CLK_SDMMC12_PLL4P
++		CLK_DSI_DSIPLL
++		CLK_STGEN_HSE
++		CLK_USBPHY_HSE
++		CLK_SPI2S1_PLL3Q
++		CLK_SPI2S23_PLL3Q
++		CLK_SPI45_HSI
++		CLK_SPI6_HSI
++		CLK_I2C46_HSI
++		CLK_SDMMC3_PLL4P
++		CLK_USBO_USBPHY
++		CLK_ADC_CKPER
++		CLK_CEC_LSE
++		CLK_I2C12_HSI
++		CLK_I2C35_HSI
++		CLK_UART1_HSI
++		CLK_UART24_HSI
++		CLK_UART35_HSI
++		CLK_UART6_HSI
++		CLK_UART78_HSI
++		CLK_SPDIF_PLL4P
++		CLK_FDCAN_PLL4R
++		CLK_SAI1_PLL3Q
++		CLK_SAI2_PLL3Q
++		CLK_SAI3_PLL3Q
++		CLK_SAI4_PLL3Q
++		CLK_RNG1_LSI
++		CLK_RNG2_LSI
++		CLK_LPTIM1_PCLK1
++		CLK_LPTIM23_PCLK3
++		CLK_LPTIM45_LSE
++	>;
++
++	/* VCO = 1300.0 MHz => P = 650 (CPU) */
++	pll1: st,pll@0 {
++		compatible = "st,stm32mp1-pll";
++		reg = <0>;
++		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
++		frac = < 0x800 >;
++	};
++
++	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
++	pll2: st,pll@1 {
++		compatible = "st,stm32mp1-pll";
++		reg = <1>;
++		cfg = <2 65 1 0 0 PQR(1,1,1)>;
++		frac = <0x1400>;
++	};
++
++	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
++	pll3: st,pll@2 {
++		compatible = "st,stm32mp1-pll";
++		reg = <2>;
++		cfg = <1 33 1 16 36 PQR(1,1,1)>;
++		frac = <0x1a04>;
++	};
++
++	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
++	pll4: st,pll@3 {
++		compatible = "st,stm32mp1-pll";
++		reg = <3>;
++		cfg = <3 98 5 7 7 PQR(1,1,1)>;
++	};
++};
diff --git a/configs/platform-v7a/patches/tf-a-v2.4/0101-fdts-stm32mp1-enable-hash1-unconditionally.patch b/configs/platform-v7a/patches/tf-a-v2.4/0101-fdts-stm32mp1-enable-hash1-unconditionally.patch
new file mode 100644
index 0000000..c05c02c
--- /dev/null
+++ b/configs/platform-v7a/patches/tf-a-v2.4/0101-fdts-stm32mp1-enable-hash1-unconditionally.patch
@@ -0,0 +1,63 @@
+From: Ahmad Fatoum <a.fatoum@pengutronix.de>
+Date: Thu, 3 Dec 2020 20:24:53 +0100
+Subject: [PATCH] fdts: stm32mp1: enable hash1 unconditionally
+
+&hash1 is an internal IP that can be enabled always as it has no
+dependencies. Indeed we must enable it, because TF-A panics otherwise
+during stm32mp_init_auth(). Instead of duplicating the enabling
+line in every board device tree, stick it into the SoC dtsi.
+
+This likely fixes boot on the Avenger board that lacks the status =
+"okay" line for the &hash1 device tree node.
+
+Change-Id: I5901029f29af0cf213510878b5daaf5240f96f17
+Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
+---
+ fdts/stm32mp151.dtsi      | 2 +-
+ fdts/stm32mp157c-ed1.dts  | 4 ----
+ fdts/stm32mp15xx-dkx.dtsi | 4 ----
+ 3 files changed, 1 insertion(+), 9 deletions(-)
+
+diff --git a/fdts/stm32mp151.dtsi b/fdts/stm32mp151.dtsi
+index 8f175a6492a1..d908b710bbb9 100644
+--- a/fdts/stm32mp151.dtsi
++++ b/fdts/stm32mp151.dtsi
+@@ -253,7 +253,7 @@
+ 			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&rcc HASH1>;
+ 			resets = <&rcc HASH1_R>;
+-			status = "disabled";
++			status = "okay";
+ 		};
+ 
+ 		rng1: rng@54003000 {
+diff --git a/fdts/stm32mp157c-ed1.dts b/fdts/stm32mp157c-ed1.dts
+index a6b98b7d9337..615e2cc07578 100644
+--- a/fdts/stm32mp157c-ed1.dts
++++ b/fdts/stm32mp157c-ed1.dts
+@@ -55,10 +55,6 @@
+ 	status="okay";
+ };
+ 
+-&hash1 {
+-	status = "okay";
+-};
+-
+ &i2c4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c4_pins_a>;
+diff --git a/fdts/stm32mp15xx-dkx.dtsi b/fdts/stm32mp15xx-dkx.dtsi
+index 52b914b84e45..e59a65fb5555 100644
+--- a/fdts/stm32mp15xx-dkx.dtsi
++++ b/fdts/stm32mp15xx-dkx.dtsi
+@@ -41,10 +41,6 @@
+ 	cpu-supply = <&vddcore>;
+ };
+ 
+-&hash1 {
+-	status = "okay";
+-};
+-
+ &i2c4 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&i2c4_pins_a>;
diff --git a/configs/platform-v7a/patches/tf-a-v2.4/series b/configs/platform-v7a/patches/tf-a-v2.4/series
new file mode 100644
index 0000000..39ffbf3
--- /dev/null
+++ b/configs/platform-v7a/patches/tf-a-v2.4/series
@@ -0,0 +1,12 @@
+# umpf-base: v2.4
+# umpf-name: 2.4/customers/pengutronix/distrokit-v7a
+# umpf-version: 2.4/customers/pengutronix/distrokit-v7a/20201203-3
+# umpf-topic: v2.4/customers/pengutronix/mc1
+# umpf-hashinfo: 21a3904995b9fbfe16f6b4d4e9db1c03d102a485
+# umpf-topic-range: e2c509a39c6cc4dda8734e6509cdbe6e3603cdfc..ffb9bfe900a2d98486ed63f8041d63cfa39620db
+0001-fdts-stm32mp1-add-support-for-Linux-Automation-MC-1-.patch
+# umpf-topic: v2.4/topic/stm32mp1-hash1-enable
+# umpf-hashinfo: c23c95a1eca7d557650836929252eb3c5cb3ca86
+# umpf-topic-range: ffb9bfe900a2d98486ed63f8041d63cfa39620db..10935b6d4379f0e8f8634cca1ac1cb69a66436e0
+0101-fdts-stm32mp1-enable-hash1-unconditionally.patch
+# umpf-end