diff options
Diffstat (limited to 'patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch')
| -rw-r--r-- | patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch b/patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch new file mode 100644 index 0000000..60abc48 --- /dev/null +++ b/patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch @@ -0,0 +1,57 @@ +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Tue, 12 Mar 2024 18:36:46 +0100 +Subject: [PATCH] fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32 + +While comments introduced with the original commit claim that +pmuv3_disable_el3()/pmuv3_init_el3() are compatible with PMUv2 and +PMUv1, this is not true in practice: The function accesses the Secure +Debug Control Register (SDCR), which only available to ARMv8 CPUs. + +ARMv8 CPUs executing in AArch32 mode would thus be able to disable +their PMUv3, while ARMv7 CPUs would hang trying to access the SDCR. + +Fix this by only doing PMUv3 handling when we know a PMUv3 to be +available. This resolves boot hanging on all STM32MP15 platforms +that use SP_min as BL32 instead of OP-TEE. + +Change-Id: I40f7611cf46b89a30243cc55bf55a8d9c9de93c8 +Fixes: c73686a11cea ("feat(pmu): introduce pmuv3 lib/extensions folder") +Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> +--- + lib/el3_runtime/aarch32/context_mgmt.c | 7 ++----- + lib/extensions/pmuv3/aarch32/pmuv3.c | 4 ---- + 2 files changed, 2 insertions(+), 9 deletions(-) + +diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c +index b60b8e0f05d0..72af43d3dcb0 100644 +--- a/lib/el3_runtime/aarch32/context_mgmt.c ++++ b/lib/el3_runtime/aarch32/context_mgmt.c +@@ -149,11 +149,8 @@ static void enable_extensions_nonsecure(bool el2_unused) + trf_init_el3(); + } + +- /* +- * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure +- * state execution. This does not affect lower NS ELs. +- */ +- pmuv3_init_el3(); ++ if (read_feat_pmuv3_id_field() >= 3) ++ pmuv3_init_el3(); + #endif /* IMAGE_BL32 */ + } + +diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c +index effb7e02dc29..456a48efb0fb 100644 +--- a/lib/extensions/pmuv3/aarch32/pmuv3.c ++++ b/lib/extensions/pmuv3/aarch32/pmuv3.c +@@ -25,10 +25,6 @@ static u_register_t mtpmu_disable_el3(u_register_t sdcr) + return sdcr; + } + +-/* +- * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and +- * to not clash with platforms which reuse the PMU name +- */ + void pmuv3_init_el3(void) + { + u_register_t sdcr = read_sdcr(); |