diff options
Diffstat (limited to 'patches/tf-a-v2.10')
8 files changed, 655 insertions, 0 deletions
diff --git a/patches/tf-a-v2.10/0001-fix-imx-disable-DRAM-retention-by-default-on-i.MX8MQ.patch b/patches/tf-a-v2.10/0001-fix-imx-disable-DRAM-retention-by-default-on-i.MX8MQ.patch new file mode 100644 index 0000000..cab995b --- /dev/null +++ b/patches/tf-a-v2.10/0001-fix-imx-disable-DRAM-retention-by-default-on-i.MX8MQ.patch @@ -0,0 +1,182 @@ +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Wed, 13 Mar 2024 08:08:13 +0100 +Subject: [PATCH] fix(imx): disable DRAM retention by default on i.MX8MQ + +Building the default upstream configuration for the imx8mq-evk is no longer +possible: The linker will complain that the TF-A image would no longer +fit On-Chip SRAM. + +In order to make the i.MX8MQ Image buildable again, let's make the DRAM +retention feature optional: It was added in v2.9 and it's possible to +boot the systems without it. Users that make space elsewhere and wish to +enable it can use the newly introduced IMX_DRAM_RETENTION parameter to +configure it. The parameter is added to all i.MX8M variants, but only +for i.MX8MQ, we disable it by default, as that's the one that currently +has binary size problems. + +Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7 +Fixes: dd108c3c1fe3 ("feat(imx8mq): add the dram retention support for imx8mq") +Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> +--- + plat/imx/common/include/imx_sip_svc.h | 8 ++++++++ + plat/imx/imx8m/imx8mm/platform.mk | 9 ++++++++- + plat/imx/imx8m/imx8mn/platform.mk | 9 ++++++++- + plat/imx/imx8m/imx8mp/platform.mk | 9 ++++++++- + plat/imx/imx8m/imx8mq/platform.mk | 9 ++++++++- + plat/imx/imx8m/include/dram.h | 8 +++++++- + 6 files changed, 47 insertions(+), 5 deletions(-) + +diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h +index 0e91c7174a52..5015eb6a1f11 100644 +--- a/plat/imx/common/include/imx_sip_svc.h ++++ b/plat/imx/common/include/imx_sip_svc.h +@@ -57,8 +57,16 @@ int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3); + int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3); ++#if IMX_DRAM_RETENTION + int dram_dvfs_handler(uint32_t smc_fid, void *handle, + u_register_t x1, u_register_t x2, u_register_t x3); ++#else ++static inline int dram_dvfs_handler(uint32_t smc_fid, void *handle, ++ u_register_t x1, u_register_t x2, u_register_t x3) ++{ ++ SMC_RET1(handle, SMC_UNK); ++} ++#endif + #endif + #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) + int dram_dvfs_handler(uint32_t smc_fid, void *handle, +diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk +index 97f4f248824d..849ae5e4ca36 100644 +--- a/plat/imx/imx8m/imx8mm/platform.mk ++++ b/plat/imx/imx8m/imx8mm/platform.mk +@@ -52,7 +52,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${XLAT_TABLES_LIB_SRCS} \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} + + ifeq (${NEED_BL2},yes) +@@ -153,6 +152,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 1 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0xbe000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk +index e0826e29a88c..94d31a2681aa 100644 +--- a/plat/imx/imx8m/imx8mn/platform.mk ++++ b/plat/imx/imx8m/imx8mn/platform.mk +@@ -46,7 +46,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/arm/tzc/tzc380.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +@@ -59,6 +58,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 1 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0xbe000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk +index ce6907195152..1f699c4f26f0 100644 +--- a/plat/imx/imx8m/imx8mp/platform.mk ++++ b/plat/imx/imx8m/imx8mp/platform.mk +@@ -47,7 +47,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/arm/tzc/tzc380.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +@@ -150,6 +149,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 1 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0x56000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk +index b1c189fa09f5..b48449725791 100644 +--- a/plat/imx/imx8m/imx8mq/platform.mk ++++ b/plat/imx/imx8m/imx8mq/platform.mk +@@ -42,7 +42,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${XLAT_TABLES_LIB_SRCS} \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} + + ENABLE_PIE := 1 +@@ -55,6 +54,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 0 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0xfe000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/include/dram.h b/plat/imx/imx8m/include/dram.h +index 719c39063778..1cf0666e9cad 100644 +--- a/plat/imx/imx8m/include/dram.h ++++ b/plat/imx/imx8m/include/dram.h +@@ -70,13 +70,19 @@ struct dram_info { + + extern struct dram_info dram_info; + +-void dram_info_init(unsigned long dram_timing_base); + void dram_umctl2_init(struct dram_timing_info *timing); + void dram_phy_init(struct dram_timing_info *timing); + + /* dram retention */ ++#if IMX_DRAM_RETENTION ++void dram_info_init(unsigned long dram_timing_base); + void dram_enter_retention(void); + void dram_exit_retention(void); ++#else ++static inline void dram_info_init(unsigned long dram_timing_base) {} ++static inline void dram_enter_retention(void) {} ++static inline void dram_exit_retention(void) {} ++#endif + + void dram_clock_switch(unsigned int target_drate, bool bypass_mode); + diff --git a/patches/tf-a-v2.10/0001-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch b/patches/tf-a-v2.10/0001-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch new file mode 100644 index 0000000..745e171 --- /dev/null +++ b/patches/tf-a-v2.10/0001-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch @@ -0,0 +1,61 @@ +From 44f35b67ee4f89b05408ecfe7b4b2c1ae5366b72 Mon Sep 17 00:00:00 2001 +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Tue, 12 Mar 2024 18:36:46 +0100 +Subject: [PATCH 1/3] fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32 + +While comments introduced with the original commit claim that +pmuv3_disable_el3()/pmuv3_init_el3() are compatible with PMUv2 and +PMUv1, this is not true in practice: The function accesses the Secure +Debug Control Register (SDCR), which only available to ARMv8 CPUs. + +ARMv8 CPUs executing in AArch32 mode would thus be able to disable +their PMUv3, while ARMv7 CPUs would hang trying to access the SDCR. + +Fix this by only doing PMUv3 handling when we know a PMUv3 to be +available. This resolves boot hanging on all STM32MP15 platforms +that use SP_min as BL32 instead of OP-TEE. + +Change-Id: I40f7611cf46b89a30243cc55bf55a8d9c9de93c8 +Fixes: c73686a11cea ("feat(pmu): introduce pmuv3 lib/extensions folder") +Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> +--- + lib/el3_runtime/aarch32/context_mgmt.c | 7 ++----- + lib/extensions/pmuv3/aarch32/pmuv3.c | 4 ---- + 2 files changed, 2 insertions(+), 9 deletions(-) + +diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c +index b60b8e0f05d0..72af43d3dcb0 100644 +--- a/lib/el3_runtime/aarch32/context_mgmt.c ++++ b/lib/el3_runtime/aarch32/context_mgmt.c +@@ -149,11 +149,8 @@ static void enable_extensions_nonsecure(bool el2_unused) + trf_init_el3(); + } + +- /* +- * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure +- * state execution. This does not affect lower NS ELs. +- */ +- pmuv3_init_el3(); ++ if (read_feat_pmuv3_id_field() >= 3) ++ pmuv3_init_el3(); + #endif /* IMAGE_BL32 */ + } + +diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c +index effb7e02dc29..456a48efb0fb 100644 +--- a/lib/extensions/pmuv3/aarch32/pmuv3.c ++++ b/lib/extensions/pmuv3/aarch32/pmuv3.c +@@ -25,10 +25,6 @@ static u_register_t mtpmu_disable_el3(u_register_t sdcr) + return sdcr; + } + +-/* +- * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and +- * to not clash with platforms which reuse the PMU name +- */ + void pmuv3_init_el3(void) + { + u_register_t sdcr = read_sdcr(); +-- +2.39.2 + diff --git a/patches/tf-a-v2.10/0002-feat-imx8mq-detect-console-base-address-during-runti.patch b/patches/tf-a-v2.10/0002-feat-imx8mq-detect-console-base-address-during-runti.patch new file mode 100644 index 0000000..c488337 --- /dev/null +++ b/patches/tf-a-v2.10/0002-feat-imx8mq-detect-console-base-address-during-runti.patch @@ -0,0 +1,69 @@ +From aeb68be64c5c47142de3c95a8961749f7b33030a Mon Sep 17 00:00:00 2001 +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Wed, 13 Mar 2024 02:08:54 +0100 +Subject: [PATCH 2/3] feat(imx8mq): detect console base address during runtime + +Change-Id: I9ba70f7068e762da979bd103390fa006c3a5d480 +--- + plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 8 +++++++- + plat/imx/imx8m/imx8mq/platform.mk | 4 ++++ + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +index 7065a658614f..70c2def7d18b 100644 +--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c ++++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +@@ -26,6 +26,7 @@ + #include <imx_aipstz.h> + #include <imx_uart.h> + #include <imx8m_caam.h> ++#include <imx8m_ccm.h> + #include <plat_imx8.h> + + #define TRUSTY_PARAMS_LEN_BYTES (4096*2) +@@ -145,6 +146,7 @@ static void bl31_tz380_setup(void) + void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) + { ++ unsigned int console_base = IMX_BOOT_UART_BASE; + static console_t console; + int i; + /* enable CSU NS access permission */ +@@ -154,7 +156,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + + imx_aipstz_init(aipstz); + +- console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, ++ if (console_base == 0U) { ++ console_base = imx8m_uart_get_base(); ++ } ++ ++ console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); + /* This console is only used for boot stage */ + console_set_scope(&console, CONSOLE_FLAG_BOOT); +diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk +index b1c189fa09f5..648159eb3d10 100644 +--- a/plat/imx/imx8m/imx8mq/platform.mk ++++ b/plat/imx/imx8m/imx8mq/platform.mk +@@ -31,6 +31,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + plat/imx/imx8m/gpc_common.c \ + plat/imx/imx8m/imx_aipstz.c \ + plat/imx/imx8m/imx8m_caam.c \ ++ plat/imx/imx8m/imx8m_ccm.c \ + plat/imx/imx8m/imx8m_psci_common.c \ + plat/imx/imx8m/imx8mq/gpc.c \ + plat/imx/common/imx8_topology.c \ +@@ -62,6 +63,9 @@ BL32_SIZE ?= 0x2000000 + $(eval $(call add_define,BL32_SIZE)) + + IMX_BOOT_UART_BASE ?= 0x30860000 ++ifeq (${IMX_BOOT_UART_BASE},auto) ++ override IMX_BOOT_UART_BASE := 0 ++endif + $(eval $(call add_define,IMX_BOOT_UART_BASE)) + + ifeq (${SPD},trusty) +-- +2.39.2 + diff --git a/patches/tf-a-v2.10/0003-imx-disable-DRAM-retention-by-default.patch b/patches/tf-a-v2.10/0003-imx-disable-DRAM-retention-by-default.patch new file mode 100644 index 0000000..7d2b361 --- /dev/null +++ b/patches/tf-a-v2.10/0003-imx-disable-DRAM-retention-by-default.patch @@ -0,0 +1,174 @@ +From 5d2f3f48a66a1f3f90d35679920832569100ed35 Mon Sep 17 00:00:00 2001 +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Wed, 13 Mar 2024 08:08:13 +0100 +Subject: [PATCH 3/3] imx: disable DRAM retention by default + +Building the default upstream configuration is no longer possible + +Change-Id: I714f8ea96f18154db02390ba500f4a2dc5329ee7 +--- + plat/imx/common/include/imx_sip_svc.h | 8 ++++++++ + plat/imx/imx8m/imx8mm/platform.mk | 9 ++++++++- + plat/imx/imx8m/imx8mn/platform.mk | 9 ++++++++- + plat/imx/imx8m/imx8mp/platform.mk | 9 ++++++++- + plat/imx/imx8m/imx8mq/platform.mk | 9 ++++++++- + plat/imx/imx8m/include/dram.h | 8 +++++++- + 6 files changed, 47 insertions(+), 5 deletions(-) + +diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h +index 0e91c7174a52..5015eb6a1f11 100644 +--- a/plat/imx/common/include/imx_sip_svc.h ++++ b/plat/imx/common/include/imx_sip_svc.h +@@ -57,8 +57,16 @@ int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3); + int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, + u_register_t x2, u_register_t x3); ++#if IMX_DRAM_RETENTION + int dram_dvfs_handler(uint32_t smc_fid, void *handle, + u_register_t x1, u_register_t x2, u_register_t x3); ++#else ++static inline int dram_dvfs_handler(uint32_t smc_fid, void *handle, ++ u_register_t x1, u_register_t x2, u_register_t x3) ++{ ++ SMC_RET1(handle, SMC_UNK); ++} ++#endif + #endif + #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) + int dram_dvfs_handler(uint32_t smc_fid, void *handle, +diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk +index 97f4f248824d..849ae5e4ca36 100644 +--- a/plat/imx/imx8m/imx8mm/platform.mk ++++ b/plat/imx/imx8m/imx8mm/platform.mk +@@ -52,7 +52,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${XLAT_TABLES_LIB_SRCS} \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} + + ifeq (${NEED_BL2},yes) +@@ -153,6 +152,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 1 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0xbe000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk +index e0826e29a88c..94d31a2681aa 100644 +--- a/plat/imx/imx8m/imx8mn/platform.mk ++++ b/plat/imx/imx8m/imx8mn/platform.mk +@@ -46,7 +46,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/arm/tzc/tzc380.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +@@ -59,6 +58,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 1 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0xbe000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk +index ce6907195152..1f699c4f26f0 100644 +--- a/plat/imx/imx8m/imx8mp/platform.mk ++++ b/plat/imx/imx8m/imx8mp/platform.mk +@@ -47,7 +47,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/arm/tzc/tzc380.c \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} \ + ${XLAT_TABLES_LIB_SRCS} + +@@ -150,6 +149,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 1 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0x56000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk +index 648159eb3d10..f61620bd4224 100644 +--- a/plat/imx/imx8m/imx8mq/platform.mk ++++ b/plat/imx/imx8m/imx8mq/platform.mk +@@ -43,7 +43,6 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + drivers/delay_timer/delay_timer.c \ + drivers/delay_timer/generic_delay_timer.c \ + ${XLAT_TABLES_LIB_SRCS} \ +- ${IMX_DRAM_SOURCES} \ + ${IMX_GIC_SOURCES} + + ENABLE_PIE := 1 +@@ -56,6 +55,14 @@ ERRATA_A53_835769 := 1 + ERRATA_A53_843419 := 1 + ERRATA_A53_855873 := 1 + ++IMX_DRAM_RETENTION ?= 0 ++$(eval $(call assert_boolean,IMX_DRAM_RETENTION)) ++$(eval $(call add_define,IMX_DRAM_RETENTION)) ++ ++ifeq (${IMX_DRAM_RETENTION},1) ++BL31_SOURCES += ${IMX_DRAM_SOURCES} ++endif ++ + BL32_BASE ?= 0xfe000000 + $(eval $(call add_define,BL32_BASE)) + +diff --git a/plat/imx/imx8m/include/dram.h b/plat/imx/imx8m/include/dram.h +index 719c39063778..1cf0666e9cad 100644 +--- a/plat/imx/imx8m/include/dram.h ++++ b/plat/imx/imx8m/include/dram.h +@@ -70,13 +70,19 @@ struct dram_info { + + extern struct dram_info dram_info; + +-void dram_info_init(unsigned long dram_timing_base); + void dram_umctl2_init(struct dram_timing_info *timing); + void dram_phy_init(struct dram_timing_info *timing); + + /* dram retention */ ++#if IMX_DRAM_RETENTION ++void dram_info_init(unsigned long dram_timing_base); + void dram_enter_retention(void); + void dram_exit_retention(void); ++#else ++static inline void dram_info_init(unsigned long dram_timing_base) {} ++static inline void dram_enter_retention(void) {} ++static inline void dram_exit_retention(void) {} ++#endif + + void dram_clock_switch(unsigned int target_drate, bool bypass_mode); + +-- +2.39.2 + diff --git a/patches/tf-a-v2.10/0101-feat-imx8mq-detect-console-base-address-during-runti.patch b/patches/tf-a-v2.10/0101-feat-imx8mq-detect-console-base-address-during-runti.patch new file mode 100644 index 0000000..d375a45 --- /dev/null +++ b/patches/tf-a-v2.10/0101-feat-imx8mq-detect-console-base-address-during-runti.patch @@ -0,0 +1,72 @@ +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Wed, 13 Mar 2024 02:08:54 +0100 +Subject: [PATCH] feat(imx8mq): detect console base address during runtime + +On the i.MX8M SoCs, TF-A doesn't itself initialize the UART, but depends +on BL2 to set it up beforehand. To allow using the same TF-A binary on +boards with different UART assignment, TF-A On i.MX8M M/N/P supports +dynamically determining the UART in use. The code is also applicable to +the i.MX8MQ, so enable it there too. + +Change-Id: I9ba70f7068e762da979bd103390fa006c3a5d480 +Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> +--- + plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c | 8 +++++++- + plat/imx/imx8m/imx8mq/platform.mk | 4 ++++ + 2 files changed, 11 insertions(+), 1 deletion(-) + +diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +index 7065a658614f..70c2def7d18b 100644 +--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c ++++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c +@@ -26,6 +26,7 @@ + #include <imx_aipstz.h> + #include <imx_uart.h> + #include <imx8m_caam.h> ++#include <imx8m_ccm.h> + #include <plat_imx8.h> + + #define TRUSTY_PARAMS_LEN_BYTES (4096*2) +@@ -145,6 +146,7 @@ static void bl31_tz380_setup(void) + void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) + { ++ unsigned int console_base = IMX_BOOT_UART_BASE; + static console_t console; + int i; + /* enable CSU NS access permission */ +@@ -154,7 +156,11 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + + imx_aipstz_init(aipstz); + +- console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, ++ if (console_base == 0U) { ++ console_base = imx8m_uart_get_base(); ++ } ++ ++ console_imx_uart_register(console_base, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE, &console); + /* This console is only used for boot stage */ + console_set_scope(&console, CONSOLE_FLAG_BOOT); +diff --git a/plat/imx/imx8m/imx8mq/platform.mk b/plat/imx/imx8m/imx8mq/platform.mk +index b48449725791..f61620bd4224 100644 +--- a/plat/imx/imx8m/imx8mq/platform.mk ++++ b/plat/imx/imx8m/imx8mq/platform.mk +@@ -31,6 +31,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ + plat/imx/imx8m/gpc_common.c \ + plat/imx/imx8m/imx_aipstz.c \ + plat/imx/imx8m/imx8m_caam.c \ ++ plat/imx/imx8m/imx8m_ccm.c \ + plat/imx/imx8m/imx8m_psci_common.c \ + plat/imx/imx8m/imx8mq/gpc.c \ + plat/imx/common/imx8_topology.c \ +@@ -69,6 +70,9 @@ BL32_SIZE ?= 0x2000000 + $(eval $(call add_define,BL32_SIZE)) + + IMX_BOOT_UART_BASE ?= 0x30860000 ++ifeq (${IMX_BOOT_UART_BASE},auto) ++ override IMX_BOOT_UART_BASE := 0 ++endif + $(eval $(call add_define,IMX_BOOT_UART_BASE)) + + ifeq (${SPD},trusty) diff --git a/patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch b/patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch new file mode 100644 index 0000000..60abc48 --- /dev/null +++ b/patches/tf-a-v2.10/0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch @@ -0,0 +1,57 @@ +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Tue, 12 Mar 2024 18:36:46 +0100 +Subject: [PATCH] fix(pmu): fix breakage on ARMv7 CPUs with SP_min as BL32 + +While comments introduced with the original commit claim that +pmuv3_disable_el3()/pmuv3_init_el3() are compatible with PMUv2 and +PMUv1, this is not true in practice: The function accesses the Secure +Debug Control Register (SDCR), which only available to ARMv8 CPUs. + +ARMv8 CPUs executing in AArch32 mode would thus be able to disable +their PMUv3, while ARMv7 CPUs would hang trying to access the SDCR. + +Fix this by only doing PMUv3 handling when we know a PMUv3 to be +available. This resolves boot hanging on all STM32MP15 platforms +that use SP_min as BL32 instead of OP-TEE. + +Change-Id: I40f7611cf46b89a30243cc55bf55a8d9c9de93c8 +Fixes: c73686a11cea ("feat(pmu): introduce pmuv3 lib/extensions folder") +Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de> +--- + lib/el3_runtime/aarch32/context_mgmt.c | 7 ++----- + lib/extensions/pmuv3/aarch32/pmuv3.c | 4 ---- + 2 files changed, 2 insertions(+), 9 deletions(-) + +diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c +index b60b8e0f05d0..72af43d3dcb0 100644 +--- a/lib/el3_runtime/aarch32/context_mgmt.c ++++ b/lib/el3_runtime/aarch32/context_mgmt.c +@@ -149,11 +149,8 @@ static void enable_extensions_nonsecure(bool el2_unused) + trf_init_el3(); + } + +- /* +- * Also applies to PMU < v3. The PMU is only disabled for EL3 and Secure +- * state execution. This does not affect lower NS ELs. +- */ +- pmuv3_init_el3(); ++ if (read_feat_pmuv3_id_field() >= 3) ++ pmuv3_init_el3(); + #endif /* IMAGE_BL32 */ + } + +diff --git a/lib/extensions/pmuv3/aarch32/pmuv3.c b/lib/extensions/pmuv3/aarch32/pmuv3.c +index effb7e02dc29..456a48efb0fb 100644 +--- a/lib/extensions/pmuv3/aarch32/pmuv3.c ++++ b/lib/extensions/pmuv3/aarch32/pmuv3.c +@@ -25,10 +25,6 @@ static u_register_t mtpmu_disable_el3(u_register_t sdcr) + return sdcr; + } + +-/* +- * Applies to all PMU versions. Name is PMUv3 for compatibility with aarch64 and +- * to not clash with platforms which reuse the PMU name +- */ + void pmuv3_init_el3(void) + { + u_register_t sdcr = read_sdcr(); diff --git a/patches/tf-a-v2.10/0301-Release-2.10-customers-pengutronix-distrokit-2024031.patch b/patches/tf-a-v2.10/0301-Release-2.10-customers-pengutronix-distrokit-2024031.patch new file mode 100644 index 0000000..58cbc06 --- /dev/null +++ b/patches/tf-a-v2.10/0301-Release-2.10-customers-pengutronix-distrokit-2024031.patch @@ -0,0 +1,21 @@ +From: Ahmad Fatoum <a.fatoum@pengutronix.de> +Date: Fri, 15 Mar 2024 21:18:29 +0100 +Subject: [PATCH] Release 2.10/customers/pengutronix/distrokit/20240315-1 + +--- + Makefile | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile b/Makefile +index 97c3c1548a78..56556db0be78 100644 +--- a/Makefile ++++ b/Makefile +@@ -222,7 +222,7 @@ endif #(Debug) + ifeq (${BUILD_STRING},) + BUILD_STRING := $(shell git describe --always --dirty --tags 2> /dev/null) + endif +-VERSION_STRING := v${VERSION}(${BUILD_TYPE}):${BUILD_STRING} ++VERSION_STRING := v${VERSION}(${BUILD_TYPE}):${BUILD_STRING}-20240315-1 + + ifeq (${AARCH32_INSTRUCTION_SET},A32) + TF_CFLAGS_aarch32 += -marm diff --git a/patches/tf-a-v2.10/series b/patches/tf-a-v2.10/series new file mode 100644 index 0000000..4dd620f --- /dev/null +++ b/patches/tf-a-v2.10/series @@ -0,0 +1,19 @@ +# umpf-base: v2.10 +# umpf-name: 2.10/customers/pengutronix/distrokit +# umpf-version: 2.10/customers/pengutronix/distrokit/20240315-1 +# umpf-topic: v2.10/topic/imx8mq-size +# umpf-hashinfo: a972970be20be852b0d48576dfb1c233612efbdd +# umpf-topic-range: b6c0948400594e3cc4dbb5a4ef04b815d2675808..6c0660bf6047f288628c282e44b9b1b06bd1d33a +0001-fix-imx-disable-DRAM-retention-by-default-on-i.MX8MQ.patch +# umpf-topic: v2.10/topic/imx8mq-console +# umpf-hashinfo: 252b1100fb3c424e0fe1043e60414c3d7e0fa675 +# umpf-topic-range: 6c0660bf6047f288628c282e44b9b1b06bd1d33a..ec9b46be3c0c561ed61f113dc3c15085dbce5bf7 +0101-feat-imx8mq-detect-console-base-address-during-runti.patch +# umpf-topic: v2.10/topic/stm32mp1 +# umpf-hashinfo: 44f35b67ee4f89b05408ecfe7b4b2c1ae5366b72 +# umpf-topic-range: ec9b46be3c0c561ed61f113dc3c15085dbce5bf7..10dfac53fdfff2f98d8140863f583df472483f1d +0201-fix-pmu-fix-breakage-on-ARMv7-CPUs-with-SP_min-as-BL.patch +# umpf-release: 2.10/customers/pengutronix/distrokit/20240315-1 +# umpf-topic-range: 10dfac53fdfff2f98d8140863f583df472483f1d..288664026c3117bda3f8f2275e76bb97be116b89 +0301-Release-2.10-customers-pengutronix-distrokit-2024031.patch +# umpf-end |