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authorSascha Hauer <s.hauer@pengutronix.de>2019-11-11 14:16:34 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2019-11-11 14:16:36 +0100
commit0c7c5c210746f7c9ce63761907a88d7f32b5d104 (patch)
tree8b733f80037230266dc861bf9872c54fefd5ab72
parent38b62d07a6109f7e00714316afbe2aead8c3dfa3 (diff)
downloadbarebox-0c7c5c210746f7c9ce63761907a88d7f32b5d104.tar.gz
ARM: am335x: Enable MMC2 clock
Since Kernel commit 5b63fb90adb9 ("ARM: dts: Fix incomplete dts data for am3 and am4 mmc") (barebox commit 419db1f984 ("dts: update to v5.3-rc7")) the AM33xx MMC2 controller is unconditionally enabled in the dts. This has the effect that the driver probes for this device and then can't access the registers as the clock is disabled. Enable the clock to let the driver probe successfully. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/mach-omap/am33xx_clock.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-omap/am33xx_clock.c b/arch/arm/mach-omap/am33xx_clock.c
index e63e936..0a49038 100644
--- a/arch/arm/mach-omap/am33xx_clock.c
+++ b/arch/arm/mach-omap/am33xx_clock.c
@@ -142,11 +142,13 @@ void am33xx_enable_per_clocks(void)
__raw_writel(PRCM_MOD_EN, CM_PER_CPSW_CLKSTCTRL);
while ((__raw_readl(CM_PER_CPGMAC0_CLKCTRL) & 0x30000) != 0x0);
- /* MMC 0 & 1 */
+ /* MMC 0, 1 & 2 */
__raw_writel(PRCM_MOD_EN, CM_PER_MMC0_CLKCTRL);
while (__raw_readl(CM_PER_MMC0_CLKCTRL) != PRCM_MOD_EN);
__raw_writel(PRCM_MOD_EN, CM_PER_MMC1_CLKCTRL);
while (__raw_readl(CM_PER_MMC1_CLKCTRL) != PRCM_MOD_EN);
+ __raw_writel(PRCM_MOD_EN, CM_PER_MMC2_CLKCTRL);
+ while (__raw_readl(CM_PER_MMC2_CLKCTRL) != PRCM_MOD_EN);
/* Enable the control module though RBL would have done it*/
__raw_writel(PRCM_MOD_EN, CM_WKUP_CONTROL_CLKCTRL);