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authorSascha Hauer <s.hauer@pengutronix.de>2015-12-08 07:33:36 +0100
committerSascha Hauer <s.hauer@pengutronix.de>2015-12-10 08:48:39 +0100
commita05d5c206c91b17eb13ab9631d93e0a9b6fb92f8 (patch)
tree69bb9a750c3f22308887a30b37e946b2738e33d4
parent48c682bcb09e2073d7eb07b4ce2ffbbf20d02d59 (diff)
downloadbarebox-a05d5c206c91b17eb13ab9631d93e0a9b6fb92f8.tar.gz
dts: update to v4.3-rc1
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/dts/am33xx-strip.dtsi1
-rw-r--r--dts/Bindings/arc/archs-pct.txt17
-rw-r--r--dts/Bindings/arm/atmel-at91.txt17
-rw-r--r--dts/Bindings/arm/bcm/ns2.txt9
-rw-r--r--dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt14
-rw-r--r--dts/Bindings/arm/coresight.txt1
-rw-r--r--dts/Bindings/arm/hisilicon/hisilicon.txt18
-rw-r--r--dts/Bindings/arm/l2cc.txt6
-rw-r--r--dts/Bindings/arm/marvell,kirkwood.txt2
-rw-r--r--dts/Bindings/arm/mediatek.txt13
-rw-r--r--dts/Bindings/arm/mediatek/mediatek,sysirq.txt4
-rw-r--r--dts/Bindings/arm/omap/omap.txt3
-rw-r--r--dts/Bindings/arm/pmu.txt12
-rw-r--r--dts/Bindings/arm/rockchip.txt35
-rw-r--r--dts/Bindings/arm/sp810.txt46
-rw-r--r--dts/Bindings/clock/gpio-mux-clock.txt19
-rw-r--r--dts/Bindings/clock/hi6220-clock.txt19
-rw-r--r--dts/Bindings/clock/imx6ul-clock.txt13
-rw-r--r--dts/Bindings/clock/mt8173-cpu-dvfs.txt83
-rw-r--r--dts/Bindings/clock/nvidia,tegra124-dfll.txt79
-rw-r--r--dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt29
-rw-r--r--dts/Bindings/clock/renesas,r8a7779-cpg-clocks.txt30
-rw-r--r--dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt26
-rw-r--r--dts/Bindings/clock/renesas,rz-cpg-clocks.txt29
-rw-r--r--dts/Bindings/clock/rockchip,rk3368-cru.txt61
-rw-r--r--dts/Bindings/clock/st/st,clkgen-pll.txt4
-rw-r--r--dts/Bindings/clock/ux500.txt64
-rw-r--r--dts/Bindings/cpufreq/tegra124-cpufreq.txt44
-rw-r--r--dts/Bindings/crypto/fsl-sec4.txt108
-rw-r--r--dts/Bindings/crypto/sun4i-ss.txt23
-rw-r--r--dts/Bindings/devfreq/event/exynos-ppmu.txt43
-rw-r--r--dts/Bindings/dma/adi,axi-dmac.txt61
-rw-r--r--dts/Bindings/dma/arm-pl08x.txt54
-rw-r--r--dts/Bindings/dma/lpc1850-dmamux.txt54
-rw-r--r--dts/Bindings/dma/mv-xor.txt10
-rw-r--r--dts/Bindings/dma/sun4i-dma.txt46
-rw-r--r--dts/Bindings/dma/zxdma.txt38
-rw-r--r--dts/Bindings/drm/msm/dsi.txt41
-rw-r--r--dts/Bindings/drm/msm/hdmi.txt3
-rw-r--r--dts/Bindings/extcon/extcon-palmas.txt5
-rw-r--r--dts/Bindings/gpio/brcm,brcmstb-gpio.txt35
-rw-r--r--dts/Bindings/gpio/gpio-etraxfs.txt3
-rw-r--r--dts/Bindings/gpio/gpio-mpc8xxx.txt22
-rw-r--r--dts/Bindings/gpio/renesas,gpio-rcar.txt1
-rw-r--r--dts/Bindings/gpio/zx296702-gpio.txt24
-rw-r--r--dts/Bindings/gpu/nvidia,tegra20-host1x.txt8
-rw-r--r--dts/Bindings/gpu/st,stih4xx.txt72
-rw-r--r--dts/Bindings/hwmon/ina209.txt (renamed from dts/Bindings/i2c/ina209.txt)0
-rw-r--r--dts/Bindings/hwmon/ina2xx.txt (renamed from dts/Bindings/i2c/ina2xx.txt)0
-rw-r--r--dts/Bindings/hwmon/lm70.txt21
-rw-r--r--dts/Bindings/hwmon/ltc2978.txt12
-rw-r--r--dts/Bindings/hwmon/max6697.txt (renamed from dts/Bindings/i2c/max6697.txt)0
-rw-r--r--dts/Bindings/i2c/i2c-cadence.txt6
-rw-r--r--dts/Bindings/i2c/i2c-emev2.txt22
-rw-r--r--dts/Bindings/i2c/i2c-lpc2k.txt33
-rw-r--r--dts/Bindings/i2c/i2c-mux-reg.txt74
-rw-r--r--dts/Bindings/i2c/i2c.txt45
-rw-r--r--dts/Bindings/i2c/trivial-devices.txt2
-rw-r--r--dts/Bindings/iio/adc/mcp320x.txt1
-rw-r--r--dts/Bindings/iio/adc/vf610-adc.txt5
-rw-r--r--dts/Bindings/iio/magnetometer/mmc35240.txt13
-rw-r--r--dts/Bindings/iio/st-sensors.txt2
-rw-r--r--dts/Bindings/input/ads7846.txt2
-rw-r--r--dts/Bindings/input/cap11xx.txt19
-rw-r--r--dts/Bindings/input/cypress,cyapa.txt44
-rw-r--r--dts/Bindings/input/elants_i2c.txt3
-rw-r--r--dts/Bindings/input/gpio-keys-polled.txt2
-rw-r--r--dts/Bindings/input/gpio-keys.txt2
-rw-r--r--dts/Bindings/input/gpio-matrix-keypad.txt2
-rw-r--r--dts/Bindings/input/qcom,pm8xxx-keypad.txt2
-rw-r--r--dts/Bindings/input/samsung-keypad.txt4
-rw-r--r--dts/Bindings/input/snvs-pwrkey.txt1
-rw-r--r--dts/Bindings/input/touchscreen/colibri-vf50-ts.txt36
-rw-r--r--dts/Bindings/input/touchscreen/imx6ul_tsc.txt36
-rw-r--r--dts/Bindings/input/touchscreen/pixcir_i2c_ts.txt3
-rw-r--r--dts/Bindings/input/touchscreen/zforce_ts.txt8
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt25
-rw-r--r--dts/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt37
-rw-r--r--dts/Bindings/interrupt-controller/msi.txt135
-rw-r--r--dts/Bindings/iommu/arm,smmu.txt6
-rw-r--r--dts/Bindings/iommu/ti,omap-iommu.txt6
-rw-r--r--dts/Bindings/ipmi.txt25
-rw-r--r--dts/Bindings/leds/common.txt27
-rw-r--r--dts/Bindings/leds/leds-ns2.txt9
-rw-r--r--dts/Bindings/leds/leds-powernv.txt26
-rw-r--r--dts/Bindings/media/i2c/adv7604.txt21
-rw-r--r--dts/Bindings/media/i2c/tc358743.txt48
-rw-r--r--dts/Bindings/media/renesas,jpu.txt24
-rw-r--r--dts/Bindings/media/stih407-c8sectpfe.txt89
-rw-r--r--dts/Bindings/memory-controllers/arm,pl172.txt125
-rw-r--r--dts/Bindings/memory-controllers/fsl/ifc.txt3
-rw-r--r--dts/Bindings/memory-controllers/synopsys.txt4
-rw-r--r--dts/Bindings/mfd/atmel-hlcdc.txt4
-rw-r--r--dts/Bindings/mfd/axp20x.txt4
-rw-r--r--dts/Bindings/mfd/da9062.txt88
-rw-r--r--dts/Bindings/mfd/max77686.txt65
-rw-r--r--dts/Bindings/mfd/max77802.txt26
-rw-r--r--dts/Bindings/mfd/rk808.txt8
-rw-r--r--dts/Bindings/mfd/tc3589x.txt4
-rw-r--r--dts/Bindings/mmc/arasan,sdhci.txt2
-rw-r--r--dts/Bindings/mmc/fsl-imx-esdhc.txt6
-rw-r--r--dts/Bindings/mmc/sdhci-atmel.txt21
-rw-r--r--dts/Bindings/mmc/ti-omap-hsmmc.txt2
-rw-r--r--dts/Bindings/mtd/fsl-quadspi.txt3
-rw-r--r--dts/Bindings/mtd/nxp-spifi.txt58
-rw-r--r--dts/Bindings/mtd/pxa3xx-nand.txt3
-rw-r--r--dts/Bindings/net/cpsw.txt6
-rw-r--r--dts/Bindings/net/dsa/dsa.txt38
-rw-r--r--dts/Bindings/net/ethernet.txt4
-rw-r--r--dts/Bindings/net/fixed-link.txt14
-rw-r--r--dts/Bindings/net/keystone-netcp.txt6
-rw-r--r--dts/Bindings/net/nfc/s3fwrn5.txt27
-rw-r--r--dts/Bindings/net/nfc/st-nci-i2c.txt (renamed from dts/Bindings/net/nfc/st-nci.txt)0
-rw-r--r--dts/Bindings/net/nfc/st-nci-spi.txt31
-rw-r--r--dts/Bindings/net/snps,dwc-qos-ethernet.txt75
-rw-r--r--dts/Bindings/nvmem/allwinner,sunxi-sid.txt (renamed from dts/Bindings/misc/allwinner,sunxi-sid.txt)4
-rw-r--r--dts/Bindings/nvmem/nvmem.txt80
-rw-r--r--dts/Bindings/nvmem/qfprom.txt35
-rw-r--r--dts/Bindings/opp/opp.txt (renamed from dts/Bindings/power/opp.txt)40
-rw-r--r--dts/Bindings/panel/auo,b080uan01.txt7
-rw-r--r--dts/Bindings/panel/lg,lg4573.txt19
-rw-r--r--dts/Bindings/panel/nec,nl4827hc19-05b.txt7
-rw-r--r--dts/Bindings/panel/okaya,rs800480t-7x0gp.txt7
-rw-r--r--dts/Bindings/pci/ti-pci.txt3
-rw-r--r--dts/Bindings/phy/phy-lpc18xx-usb-otg.txt26
-rw-r--r--dts/Bindings/phy/sun4i-usb-phy.txt22
-rw-r--r--dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt37
-rw-r--r--dts/Bindings/pinctrl/cnxt,cx92755-pinctrl.txt86
-rw-r--r--dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt36
-rw-r--r--dts/Bindings/pinctrl/qcom,pmic-mpp.txt36
-rw-r--r--dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt24
-rw-r--r--dts/Bindings/pinctrl/ste,nomadik.txt7
-rw-r--r--dts/Bindings/power/power_domain.txt2
-rw-r--r--dts/Bindings/power/qcom,coincell-charger.txt48
-rw-r--r--dts/Bindings/power/rockchip-io-domain.txt14
-rw-r--r--dts/Bindings/powerpc/fsl/mpc5121-psc.txt24
-rw-r--r--dts/Bindings/powerpc/fsl/scfg.txt18
-rw-r--r--dts/Bindings/pwm/lpc1850-sct-pwm.txt20
-rw-r--r--dts/Bindings/regulator/da9210.txt4
-rw-r--r--dts/Bindings/regulator/da9211.txt32
-rw-r--r--dts/Bindings/regulator/max77686.txt71
-rw-r--r--dts/Bindings/regulator/max8973-regulator.txt6
-rw-r--r--dts/Bindings/regulator/mt6311-regulator.txt35
-rw-r--r--dts/Bindings/regulator/pwm-regulator.txt65
-rw-r--r--dts/Bindings/regulator/qcom,spmi-regulator.txt60
-rw-r--r--dts/Bindings/regulator/regulator.txt1
-rw-r--r--dts/Bindings/reset/ath79-reset.txt20
-rw-r--r--dts/Bindings/reset/nxp,lpc1850-rgu.txt84
-rw-r--r--dts/Bindings/reset/socfpga-reset.txt2
-rw-r--r--dts/Bindings/reset/st,sti-picophyreset.txt2
-rw-r--r--dts/Bindings/reset/st,sti-powerdown.txt4
-rw-r--r--dts/Bindings/reset/st,sti-softreset.txt4
-rw-r--r--dts/Bindings/reset/zynq-reset.txt68
-rw-r--r--dts/Bindings/rtc/atmel,at91rm9200-rtc.txt2
-rw-r--r--dts/Bindings/rtc/nxp,lpc1788-rtc.txt21
-rw-r--r--dts/Bindings/rtc/rtc-mxc.txt26
-rw-r--r--dts/Bindings/rtc/rtc-omap.txt5
-rw-r--r--dts/Bindings/rtc/rtc-st-lpc.txt15
-rw-r--r--dts/Bindings/rtc/ti,bq32k.txt (renamed from dts/Bindings/i2c/ti,bq32k.txt)0
-rw-r--r--dts/Bindings/rtc/xlnx-rtc.txt25
-rw-r--r--dts/Bindings/serial/atmel-usart.txt3
-rw-r--r--dts/Bindings/serial/axis,etraxfs-uart.txt6
-rw-r--r--dts/Bindings/serial/mtk-uart.txt6
-rw-r--r--dts/Bindings/serial/omap_serial.txt3
-rw-r--r--dts/Bindings/soc/mediatek/scpsys.txt41
-rw-r--r--dts/Bindings/soc/qcom,smd-rpm.txt117
-rw-r--r--dts/Bindings/soc/qcom/qcom,smd.txt85
-rw-r--r--dts/Bindings/sound/cs4349.txt19
-rw-r--r--dts/Bindings/sound/ics43432.txt17
-rw-r--r--dts/Bindings/sound/max98357a.txt6
-rw-r--r--dts/Bindings/sound/nvidia,tegra30-hda.txt8
-rw-r--r--dts/Bindings/sound/renesas,rsnd.txt22
-rw-r--r--dts/Bindings/sound/renesas,rsrc-card.txt7
-rw-r--r--dts/Bindings/sound/rockchip-max98090.txt19
-rw-r--r--dts/Bindings/sound/rockchip-rt5645.txt17
-rw-r--r--dts/Bindings/sound/st,sti-asoc-card.txt155
-rw-r--r--dts/Bindings/spi/snps,dw-apb-ssi.txt2
-rw-r--r--dts/Bindings/spi/spi-davinci.txt2
-rw-r--r--dts/Bindings/spi/spi-img-spfi.txt1
-rw-r--r--dts/Bindings/spi/spi-mt65xx.txt51
-rw-r--r--dts/Bindings/spi/spi-xlp.txt39
-rw-r--r--dts/Bindings/staging/iio/adc/mxs-lradc.txt2
-rw-r--r--dts/Bindings/timer/img,pistachio-gptimer.txt28
-rw-r--r--dts/Bindings/timer/mediatek,mtk-timer.txt6
-rw-r--r--dts/Bindings/timer/st,stih407-lpc28
-rw-r--r--dts/Bindings/usb/allwinner,sun4i-a10-musb.txt29
-rw-r--r--dts/Bindings/usb/ci-hdrc-usb2.txt20
-rw-r--r--dts/Bindings/usb/generic.txt15
-rw-r--r--dts/Bindings/usb/msm-hsusb.txt4
-rw-r--r--dts/Bindings/usb/qcom,usb-8x16-phy.txt76
-rw-r--r--dts/Bindings/vendor-prefixes.txt11
-rw-r--r--dts/Bindings/video/backlight/pm8941-wled.txt (renamed from dts/Bindings/leds/leds-pm8941-wled.txt)5
-rw-r--r--dts/Bindings/video/fsl,dcu.txt22
-rw-r--r--dts/Bindings/watchdog/atmel-sama5d4-wdt.txt35
-rw-r--r--dts/Bindings/watchdog/atmel-wdt.txt2
-rw-r--r--dts/Bindings/watchdog/lpc18xx-wdt.txt19
-rw-r--r--dts/Bindings/watchdog/st_lpc_wdt.txt12
-rw-r--r--dts/include/dt-bindings/clock/exynos3250.h1
-rw-r--r--dts/include/dt-bindings/clock/exynos5250.h1
-rw-r--r--dts/include/dt-bindings/clock/imx6qdl-clock.h5
-rw-r--r--dts/include/dt-bindings/clock/imx6ul-clock.h240
-rw-r--r--dts/include/dt-bindings/clock/r8a7790-clock.h3
-rw-r--r--dts/include/dt-bindings/clock/r8a7791-clock.h2
-rw-r--r--dts/include/dt-bindings/clock/r8a7793-clock.h164
-rw-r--r--dts/include/dt-bindings/clock/rk3066a-cru.h5
-rw-r--r--dts/include/dt-bindings/clock/rk3188-cru-common.h5
-rw-r--r--dts/include/dt-bindings/clock/rk3188-cru.h5
-rw-r--r--dts/include/dt-bindings/clock/rk3288-cru.h5
-rw-r--r--dts/include/dt-bindings/clock/rk3368-cru.h384
-rw-r--r--dts/include/dt-bindings/clock/zx296702-clock.h17
-rw-r--r--dts/include/dt-bindings/dma/axi-dmac.h48
-rw-r--r--dts/include/dt-bindings/dma/jz4780-dma.h49
-rw-r--r--dts/include/dt-bindings/i2c/i2c.h18
-rw-r--r--dts/include/dt-bindings/leds/leds-ns2.h8
-rw-r--r--dts/include/dt-bindings/media/c8sectpfe.h12
-rw-r--r--dts/include/dt-bindings/memory/tegra210-mc.h36
-rw-r--r--dts/include/dt-bindings/mfd/st-lpc.h1
-rw-r--r--dts/include/dt-bindings/pinctrl/am43xx.h1
-rw-r--r--dts/include/dt-bindings/pinctrl/dra.h20
-rw-r--r--dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h51
-rw-r--r--dts/include/dt-bindings/power/mt8173-power.h15
-rw-r--r--dts/include/dt-bindings/reset/altr,rst-mgr-a10.h110
-rw-r--r--dts/include/dt-bindings/reset/stih407-resets.h (renamed from dts/include/dt-bindings/reset-controller/stih407-resets.h)0
-rw-r--r--dts/include/dt-bindings/reset/stih415-resets.h (renamed from dts/include/dt-bindings/reset-controller/stih415-resets.h)0
-rw-r--r--dts/include/dt-bindings/reset/stih416-resets.h (renamed from dts/include/dt-bindings/reset-controller/stih416-resets.h)0
-rw-r--r--dts/include/dt-bindings/reset/tegra124-car.h12
-rw-r--r--dts/src/arc/axc003.dtsi13
-rw-r--r--dts/src/arm/am335x-boneblack.dts20
-rw-r--r--dts/src/arm/am335x-evm.dts69
-rw-r--r--dts/src/arm/am335x-evmsk.dts62
-rw-r--r--dts/src/arm/am335x-phycore-som.dtsi368
-rw-r--r--dts/src/arm/am335x-wega-rdk.dts22
-rw-r--r--dts/src/arm/am335x-wega.dtsi151
-rw-r--r--dts/src/arm/am33xx.dtsi39
-rw-r--r--dts/src/arm/am4372.dtsi70
-rw-r--r--dts/src/arm/am437x-gp-evm.dts198
-rw-r--r--dts/src/arm/am437x-idk-evm.dts9
-rw-r--r--dts/src/arm/am437x-sk-evm.dts54
-rw-r--r--dts/src/arm/am43x-epos-evm.dts130
-rw-r--r--dts/src/arm/am43xx-clocks.dtsi9
-rw-r--r--dts/src/arm/am57xx-beagle-x15.dts5
-rw-r--r--dts/src/arm/armada-375.dtsi4
-rw-r--r--dts/src/arm/armada-388-gp.dts12
-rw-r--r--dts/src/arm/armada-38x.dtsi8
-rw-r--r--dts/src/arm/armada-39x.dtsi8
-rw-r--r--dts/src/arm/at91-sama5d2_xplained.dts134
-rw-r--r--dts/src/arm/at91-sama5d4_xplained.dts9
-rw-r--r--dts/src/arm/at91-sama5d4ek.dts9
-rw-r--r--dts/src/arm/at91rm9200.dtsi10
-rw-r--r--dts/src/arm/at91sam9260.dtsi11
-rw-r--r--dts/src/arm/at91sam9261.dtsi7
-rw-r--r--dts/src/arm/at91sam9263.dtsi7
-rw-r--r--dts/src/arm/at91sam9g15.dtsi1
-rw-r--r--dts/src/arm/at91sam9g15ek.dts25
-rw-r--r--dts/src/arm/at91sam9g35.dtsi1
-rw-r--r--dts/src/arm/at91sam9g35ek.dts21
-rw-r--r--dts/src/arm/at91sam9g45.dtsi60
-rw-r--r--dts/src/arm/at91sam9m10g45ek.dts47
-rw-r--r--dts/src/arm/at91sam9n12.dtsi83
-rw-r--r--dts/src/arm/at91sam9n12ek.dts61
-rw-r--r--dts/src/arm/at91sam9rl.dtsi8
-rw-r--r--dts/src/arm/at91sam9x35.dtsi1
-rw-r--r--dts/src/arm/at91sam9x35ek.dts20
-rw-r--r--dts/src/arm/at91sam9x5.dtsi12
-rw-r--r--dts/src/arm/at91sam9x5_lcd.dtsi139
-rw-r--r--dts/src/arm/at91sam9x5dm.dtsi101
-rw-r--r--dts/src/arm/atlas7-evb.dts18
-rw-r--r--dts/src/arm/atlas7.dtsi97
-rw-r--r--dts/src/arm/axp152.dtsi49
-rw-r--r--dts/src/arm/bcm-cygnus-clock.dtsi89
-rw-r--r--dts/src/arm/bcm2835-rpi.dtsi7
-rw-r--r--dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts4
-rw-r--r--dts/src/arm/bcm4708-luxul-xwc-1000.dts4
-rw-r--r--dts/src/arm/bcm4708-netgear-r6250.dts14
-rw-r--r--dts/src/arm/bcm4708-smartrg-sr400ac.dts4
-rw-r--r--dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts4
-rw-r--r--dts/src/arm/bcm5301x.dtsi10
-rw-r--r--dts/src/arm/bcm7445.dtsi50
-rw-r--r--dts/src/arm/cros-ec-sbs.dtsi52
-rw-r--r--dts/src/arm/cx92755.dtsi7
-rw-r--r--dts/src/arm/cx92755_equinox.dts3
-rw-r--r--dts/src/arm/dm8148-evm.dts28
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-rw-r--r--dts/src/arm/exynos4412-odroidu3.dts8
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-rw-r--r--dts/src/arm/exynos5422-cpu-thermal.dtsi59
-rw-r--r--dts/src/arm/exynos5422-cpus.dtsi81
-rw-r--r--dts/src/arm/exynos5422-odroidxu3-common.dtsi47
-rw-r--r--dts/src/arm/imx27.dtsi9
-rw-r--r--dts/src/arm/imx53-qsb-common.dtsi5
-rw-r--r--dts/src/arm/imx53-qsrb.dts14
-rw-r--r--dts/src/arm/imx6qdl-gw51xx.dtsi1
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-rw-r--r--dts/src/arm/imx6qdl-gw552x.dtsi1
-rw-r--r--dts/src/arm/imx6qdl-nitrogen6x.dtsi39
-rw-r--r--dts/src/arm/imx6qdl-sabreauto.dtsi137
-rw-r--r--dts/src/arm/imx6qdl-sabrelite.dtsi39
-rw-r--r--dts/src/arm/imx6qdl-sabresd.dtsi7
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-rw-r--r--dts/src/arm/imx6ul-14x14-evk.dts343
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-rw-r--r--dts/src/arm/kirkwood-ns2mini.dts5
-rw-r--r--dts/src/arm/lpc18xx.dtsi267
-rw-r--r--dts/src/arm/lpc4337-ciaa.dts187
-rw-r--r--dts/src/arm/lpc4350-hitex-eval.dts244
-rw-r--r--dts/src/arm/lpc4357-ea4357-devkit.dts467
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-rw-r--r--dts/src/arm/mt6580.dtsi116
-rw-r--r--dts/src/arm/mt8135-evbp1.dts193
-rw-r--r--dts/src/arm/mt8135.dtsi58
-rw-r--r--dts/src/arm/omap3-devkit8000-common.dtsi369
-rw-r--r--dts/src/arm/omap3-devkit8000-lcd-common.dtsi73
-rw-r--r--dts/src/arm/omap3-devkit8000-lcd43.dts37
-rw-r--r--dts/src/arm/omap3-devkit8000-lcd70.dts37
-rw-r--r--dts/src/arm/omap3-devkit8000.dts191
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-rw-r--r--dts/src/arm/omap3-overo-base.dtsi55
-rw-r--r--dts/src/arm/omap3-overo-common-lcd35.dtsi3
-rw-r--r--dts/src/arm/omap3-overo-palo35-common.dtsi53
-rw-r--r--dts/src/arm/omap3-overo-palo35.dts37
-rw-r--r--dts/src/arm/omap3-overo-storm-palo35.dts37
-rw-r--r--dts/src/arm/omap3-overo-storm-tobiduo.dts21
-rw-r--r--dts/src/arm/omap3-overo-tobiduo-common.dtsi65
-rw-r--r--dts/src/arm/omap3-overo-tobiduo.dts21
-rw-r--r--dts/src/arm/omap3-overo.dtsi4
-rw-r--r--dts/src/arm/omap3-pandora-1ghz.dts2
-rw-r--r--dts/src/arm/omap3-pandora-600mhz.dts2
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-rw-r--r--dts/src/arm/omap5-uevm.dts7
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-rw-r--r--dts/src/arm/pxa2xx.dtsi4
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-rw-r--r--dts/src/arm/qcom-apq8064-ifc6410.dts44
-rw-r--r--dts/src/arm/qcom-apq8064.dtsi91
-rw-r--r--dts/src/arm/qcom-apq8074-dragonboard.dts8
-rw-r--r--dts/src/arm/qcom-apq8084-ifc6540.dts8
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-rw-r--r--dts/src/arm/qcom-ipq8064-ap148.dts8
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-rw-r--r--dts/src/arm/qcom-msm8660-surf.dts8
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-rw-r--r--dts/src/arm/qcom-msm8960-cdp.dts310
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-rw-r--r--dts/src/arm/qcom-msm8974-sony-xperia-honami.dts18
-rw-r--r--dts/src/arm/qcom-msm8974.dtsi34
-rw-r--r--dts/src/arm/qcom-pm8941.dtsi6
-rw-r--r--dts/src/arm/r7s72100.dtsi19
-rw-r--r--dts/src/arm/r8a73a4.dtsi9
-rw-r--r--dts/src/arm/r8a7740-armadillo800eva.dts13
-rw-r--r--dts/src/arm/r8a7740.dtsi1
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-rw-r--r--dts/src/arm/r8a7779.dtsi28
-rw-r--r--dts/src/arm/r8a7790-lager.dts4
-rw-r--r--dts/src/arm/r8a7790.dtsi138
-rw-r--r--dts/src/arm/r8a7791-koelsch.dts2
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-rw-r--r--dts/src/arm/r8a7794-silk.dts102
-rw-r--r--dts/src/arm/r8a7794.dtsi48
-rw-r--r--dts/src/arm/rk3066a-bqcurie2.dts1
-rw-r--r--dts/src/arm/rk3066a-marsboard.dts13
-rw-r--r--dts/src/arm/rk3066a-rayeager.dts5
-rw-r--r--dts/src/arm/rk3066a.dtsi22
-rw-r--r--dts/src/arm/rk3188-radxarock.dts5
-rw-r--r--dts/src/arm/rk3188.dtsi22
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-rw-r--r--dts/src/arm/rk3288-firefly.dtsi3
-rw-r--r--dts/src/arm/rk3288-popmetal.dts1
-rw-r--r--dts/src/arm/rk3288-r89.dts413
-rw-r--r--dts/src/arm/rk3288-veyron-chromebook.dtsi232
-rw-r--r--dts/src/arm/rk3288-veyron-jerry.dts197
-rw-r--r--dts/src/arm/rk3288-veyron-minnie.dts230
-rw-r--r--dts/src/arm/rk3288-veyron-pinky.dts128
-rw-r--r--dts/src/arm/rk3288-veyron-sdmmc.dtsi122
-rw-r--r--dts/src/arm/rk3288-veyron-speedy.dts155
-rw-r--r--dts/src/arm/rk3288-veyron.dtsi563
-rw-r--r--dts/src/arm/rk3288.dtsi31
-rw-r--r--dts/src/arm/rk3xxx.dtsi10
-rw-r--r--dts/src/arm/sama5d2.dtsi926
-rw-r--r--dts/src/arm/sama5d3.dtsi10
-rw-r--r--dts/src/arm/sama5d3_tcb1.dtsi4
-rw-r--r--dts/src/arm/sama5d4.dtsi25
-rw-r--r--dts/src/arm/sh73a0.dtsi3
-rw-r--r--dts/src/arm/socfpga.dtsi46
-rw-r--r--dts/src/arm/socfpga_arria10.dtsi11
-rw-r--r--dts/src/arm/socfpga_arria10_socdk.dtsi3
-rw-r--r--dts/src/arm/socfpga_arria5_socdk.dts3
-rw-r--r--dts/src/arm/socfpga_cyclone5_de0_sockit.dts111
-rw-r--r--dts/src/arm/socfpga_cyclone5_socdk.dts3
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-rw-r--r--dts/src/arm/stih407-family.dtsi47
-rw-r--r--dts/src/arm/stih407-pinctrl.dtsi200
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-rw-r--r--dts/src/arm/stih410-clock.dtsi4
-rw-r--r--dts/src/arm/stih410.dtsi12
-rw-r--r--dts/src/arm/stih415.dtsi2
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-rw-r--r--dts/src/arm/stih418-clock.dtsi4
-rw-r--r--dts/src/arm/stih418.dtsi4
-rw-r--r--dts/src/arm/stm32429i-eval.dts75
-rw-r--r--dts/src/arm/stm32f429-disco.dts8
-rw-r--r--dts/src/arm/stm32f429.dtsi79
-rw-r--r--dts/src/arm/sun4i-a10-ba10-tvbox.dts15
-rw-r--r--dts/src/arm/sun4i-a10-chuwi-v7-cw0825.dts34
-rw-r--r--dts/src/arm/sun4i-a10-cubieboard.dts19
-rw-r--r--dts/src/arm/sun4i-a10-itead-iteaduino-plus.dts202
-rw-r--r--dts/src/arm/sun4i-a10-mini-xplus.dts15
-rw-r--r--dts/src/arm/sun4i-a10-olinuxino-lime.dts32
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-rw-r--r--dts/src/arm/sun5i-a10s-olinuxino-micro.dts37
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-rw-r--r--dts/src/arm/sun5i-a13-hsg-h702.dts58
-rw-r--r--dts/src/arm/sun5i-a13-olinuxino.dts37
-rw-r--r--dts/src/arm/sun5i-a13-utoo-p66.dts29
-rw-r--r--dts/src/arm/sun5i-a13.dtsi18
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-rw-r--r--dts/src/arm/sun6i-a31.dtsi58
-rw-r--r--dts/src/arm/sun6i-a31s-cs908.dts5
-rw-r--r--dts/src/arm/sun7i-a20-cubietruck.dts56
-rw-r--r--dts/src/arm/sun7i-a20-i12-tvbox.dts2
-rw-r--r--dts/src/arm/sun7i-a20-olinuxino-lime.dts32
-rw-r--r--dts/src/arm/sun7i-a20-olinuxino-micro.dts32
-rw-r--r--dts/src/arm/sun7i-a20.dtsi47
-rw-r--r--dts/src/arm/sun8i-a23-a33.dtsi40
-rw-r--r--dts/src/arm/sun8i-a23-ippo-q8h-v5.dts9
-rw-r--r--dts/src/arm/sun8i-a23.dtsi33
-rw-r--r--dts/src/arm/sun8i-a33-ga10h-v1.1.dts17
-rw-r--r--dts/src/arm/sun8i-a33-ippo-q8h-v1.2.dts133
-rw-r--r--dts/src/arm/sun8i-a33-sinlinx-sina33.dts13
-rw-r--r--dts/src/arm/sun8i-a33.dtsi33
-rw-r--r--dts/src/arm/sun9i-a80.dtsi32
-rw-r--r--dts/src/arm/sunxi-common-regulators.dtsi2
-rw-r--r--dts/src/arm/tegra114.dtsi5
-rw-r--r--dts/src/arm/tegra124-jetson-tk1.dts25
-rw-r--r--dts/src/arm/tegra124-venice2.dts10
-rw-r--r--dts/src/arm/tegra124.dtsi50
-rw-r--r--dts/src/arm/tegra20.dtsi5
-rw-r--r--dts/src/arm/tegra30.dtsi5
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-rw-r--r--dts/src/arm/uniphier-ph1-ld4.dtsi143
-rw-r--r--dts/src/arm/uniphier-ph1-ld6b-ref.dts105
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-rw-r--r--dts/src/arm/uniphier-ph1-pro4-ref.dts40
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-rw-r--r--dts/src/arm/uniphier-ph1-sld3-ref.dts46
-rw-r--r--dts/src/arm/uniphier-ph1-sld3.dtsi122
-rw-r--r--dts/src/arm/uniphier-ph1-sld8-ref.dts42
-rw-r--r--dts/src/arm/uniphier-ph1-sld8.dtsi143
-rw-r--r--dts/src/arm/uniphier-pinctrl.dtsi105
-rw-r--r--dts/src/arm/uniphier-proxstream2.dtsi273
-rw-r--r--dts/src/arm/uniphier-ref-daughter.dtsi50
-rw-r--r--dts/src/arm/vexpress-v2m-rs1.dtsi2
-rw-r--r--dts/src/arm/vexpress-v2m.dtsi2
-rw-r--r--dts/src/arm/vf-colibri-eval-v3.dtsi2
-rw-r--r--dts/src/arm/vfxxx.dtsi85
-rw-r--r--dts/src/arm/zynq-7000.dtsi10
-rw-r--r--dts/src/arm/zynq-zc702.dts28
-rw-r--r--dts/src/arm64/apm/apm-storm.dtsi23
-rw-r--r--dts/src/arm64/arm/juno-motherboard.dtsi2
-rw-r--r--dts/src/arm64/arm/rtsm_ve-motherboard.dtsi2
-rw-r--r--dts/src/arm64/broadcom/ns2-svk.dts59
-rw-r--r--dts/src/arm64/broadcom/ns2.dtsi118
-rw-r--r--dts/src/arm64/marvell/berlin4ct-dmp.dts66
-rw-r--r--dts/src/arm64/marvell/berlin4ct.dtsi164
-rw-r--r--dts/src/arm64/mediatek/mt6795-evb.dts41
-rw-r--r--dts/src/arm64/mediatek/mt6795.dtsi175
-rw-r--r--dts/src/arm64/mediatek/mt8173-evb.dts353
-rw-r--r--dts/src/arm64/mediatek/mt8173.dtsi327
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc-pmic-pins.dtsi34
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc-soc-pins.dtsi14
-rw-r--r--dts/src/arm64/qcom/apq8016-sbc.dtsi51
-rw-r--r--dts/src/arm64/qcom/msm8916-pins.dtsi430
-rw-r--r--dts/src/arm64/qcom/msm8916.dtsi227
-rw-r--r--dts/src/arm64/rockchip/rk3368-r88.dts354
-rw-r--r--dts/src/arm64/rockchip/rk3368.dtsi900
-rw-r--r--dts/src/arm64/sprd/sc9836.dtsi99
-rw-r--r--dts/src/arm64/xilinx/zynqmp-ep108.dts89
-rw-r--r--dts/src/arm64/xilinx/zynqmp.dtsi233
-rw-r--r--dts/src/mips/netlogic/xlp_evp.dts12
-rw-r--r--dts/src/mips/netlogic/xlp_fvp.dts12
-rw-r--r--dts/src/mips/netlogic/xlp_gvp.dts11
-rw-r--r--dts/src/mips/netlogic/xlp_rvp.dts11
-rw-r--r--dts/src/mips/netlogic/xlp_svp.dts12
-rw-r--r--dts/src/mips/qca/ar9132.dtsi8
-rwxr-xr-xdts/src/nios2/10m50_devboard.dts248
-rw-r--r--dts/src/powerpc/fsl/p1022si-post.dtsi2
-rw-r--r--dts/src/powerpc/fsl/p1022si-pre.dtsi2
-rw-r--r--dts/src/powerpc/fsl/t1040si-post.dtsi5
-rw-r--r--dts/src/powerpc/t1023rdb.dts13
-rw-r--r--dts/src/powerpc/t1024rdb.dts6
-rw-r--r--dts/src/powerpc/t1040d4rdb.dts46
-rw-r--r--dts/src/powerpc/t1042d4rdb.dts53
-rw-r--r--dts/src/powerpc/t104xd4rdb.dtsi205
551 files changed, 30395 insertions, 3533 deletions
diff --git a/arch/arm/dts/am33xx-strip.dtsi b/arch/arm/dts/am33xx-strip.dtsi
index 04cf315..2943fd1 100644
--- a/arch/arm/dts/am33xx-strip.dtsi
+++ b/arch/arm/dts/am33xx-strip.dtsi
@@ -45,3 +45,4 @@
/delete-node/ &rng;
/delete-node/ &rtc;
/delete-node/ &wkup_m3;
+/delete-node/ &wkup_m3_ipc;
diff --git a/dts/Bindings/arc/archs-pct.txt b/dts/Bindings/arc/archs-pct.txt
new file mode 100644
index 0000000..1ae98b8
--- /dev/null
+++ b/dts/Bindings/arc/archs-pct.txt
@@ -0,0 +1,17 @@
+* ARC HS Performance Counters
+
+The ARC HS can be configured with a pipeline performance monitor for counting
+CPU and cache events like cache misses and hits. Like conventional PCT there
+are 100+ hardware conditions dynamically mapped to upto 32 counters.
+It also supports overflow interrupts.
+
+Required properties:
+
+- compatible : should contain
+ "snps,archs-pct"
+
+Example:
+
+pmu {
+ compatible = "snps,archs-pct";
+};
diff --git a/dts/Bindings/arm/atmel-at91.txt b/dts/Bindings/arm/atmel-at91.txt
index 424ac8c..7fd64ec 100644
--- a/dts/Bindings/arm/atmel-at91.txt
+++ b/dts/Bindings/arm/atmel-at91.txt
@@ -27,6 +27,8 @@ compatible: must be one of:
o "atmel,at91sam9xe"
* "atmel,sama5" for SoCs using a Cortex-A5, shall be extended with the specific
SoC family:
+ o "atmel,sama5d2" shall be extended with the specific SoC compatible:
+ - "atmel,sama5d27"
o "atmel,sama5d3" shall be extended with the specific SoC compatible:
- "atmel,sama5d31"
- "atmel,sama5d33"
@@ -50,6 +52,7 @@ System Timer (ST) required properties:
- reg: Should contain registers location and length
- interrupts: Should contain interrupt for the ST which is the IRQ line
shared across all System Controller members.
+- clocks: phandle to input clock.
Its subnodes can be:
- watchdog: compatible should be "atmel,at91rm9200-wdt"
@@ -61,7 +64,7 @@ TC/TCLIB Timer required properties:
Note that you can specify several interrupt cells if the TC
block has one interrupt per channel.
- clock-names: tuple listing input clock names.
- Required elements: "t0_clk"
+ Required elements: "t0_clk", "slow_clk"
Optional elements: "t1_clk", "t2_clk"
- clocks: phandles to input clocks.
@@ -87,14 +90,16 @@ One interrupt per TC channel in a TC block:
RSTC Reset Controller required properties:
- compatible: Should be "atmel,<chip>-rstc".
- <chip> can be "at91sam9260" or "at91sam9g45"
+ <chip> can be "at91sam9260" or "at91sam9g45" or "sama5d3"
- reg: Should contain registers location and length
+- clocks: phandle to input clock.
Example:
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
RAMC SDRAM/DDR Controller required properties:
@@ -117,6 +122,7 @@ required properties:
- compatible: Should be "atmel,<chip>-shdwc".
<chip> can be "at91sam9260", "at91sam9rl" or "at91sam9x5".
- reg: Should contain registers location and length
+- clocks: phandle to input clock.
optional properties:
- atmel,wakeup-mode: String, operation mode of the wakeup mode.
@@ -135,9 +141,10 @@ optional at91sam9x5 properties:
Example:
- rstc@fffffd00 {
- compatible = "atmel,at91sam9260-rstc";
- reg = <0xfffffd00 0x10>;
+ shdwc@fffffd10 {
+ compatible = "atmel,at91sam9260-shdwc";
+ reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
Special Function Registers (SFR)
diff --git a/dts/Bindings/arm/bcm/ns2.txt b/dts/Bindings/arm/bcm/ns2.txt
new file mode 100644
index 0000000..35f056f
--- /dev/null
+++ b/dts/Bindings/arm/bcm/ns2.txt
@@ -0,0 +1,9 @@
+Broadcom North Star 2 (NS2) device tree bindings
+------------------------------------------------
+
+Boards with NS2 shall have the following properties:
+
+Required root node property:
+
+NS2 SVK board
+compatible = "brcm,ns2-svk", "brcm,ns2";
diff --git a/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
new file mode 100644
index 0000000..6824b31
--- /dev/null
+++ b/dts/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.txt
@@ -0,0 +1,14 @@
+Raspberry Pi VideoCore firmware driver
+
+Required properties:
+
+- compatible: Should be "raspberrypi,bcm2835-firmware"
+- mboxes: Phandle to the firmware device's Mailbox.
+ (See: ../mailbox/mailbox.txt for more information)
+
+Example:
+
+firmware {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+};
diff --git a/dts/Bindings/arm/coresight.txt b/dts/Bindings/arm/coresight.txt
index 65a6db2..62938eb 100644
--- a/dts/Bindings/arm/coresight.txt
+++ b/dts/Bindings/arm/coresight.txt
@@ -17,6 +17,7 @@ its hardware characteristcs.
- "arm,coresight-tmc", "arm,primecell";
- "arm,coresight-funnel", "arm,primecell";
- "arm,coresight-etm3x", "arm,primecell";
+ - "arm,coresight-etm4x", "arm,primecell";
- "qcom,coresight-replicator1x", "arm,primecell";
* reg: physical base address and length of the register
diff --git a/dts/Bindings/arm/hisilicon/hisilicon.txt b/dts/Bindings/arm/hisilicon/hisilicon.txt
index c431c67..c733e28 100644
--- a/dts/Bindings/arm/hisilicon/hisilicon.txt
+++ b/dts/Bindings/arm/hisilicon/hisilicon.txt
@@ -127,6 +127,24 @@ Example:
#clock-cells = <1>;
};
+
+Hisilicon Hi6220 SRAM controller
+
+Required properties:
+- compatible : "hisilicon,hi6220-sramctrl", "syscon"
+- reg : Register address and size
+
+Hisilicon's SoCs use sram for multiple purpose; on Hi6220 there have several
+SRAM banks for power management, modem, security, etc. Further, use "syscon"
+managing the common sram which can be shared by multiple modules.
+
+Example:
+ /*for Hi6220*/
+ sram: sram@fff80000 {
+ compatible = "hisilicon,hi6220-sramctrl", "syscon";
+ reg = <0x0 0xfff80000 0x0 0x12000>;
+ };
+
-----------------------------------------------------------------------
Hisilicon HiP01 system controller
diff --git a/dts/Bindings/arm/l2cc.txt b/dts/Bindings/arm/l2cc.txt
index 2251dcc..06c88a4 100644
--- a/dts/Bindings/arm/l2cc.txt
+++ b/dts/Bindings/arm/l2cc.txt
@@ -67,6 +67,12 @@ Optional properties:
disable if zero.
- arm,prefetch-offset : Override prefetch offset value. Valid values are
0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the pl310 cache controller with
+ respect to the shareable attribute is to transform "normal memory
+ non-cacheable transactions" into "cacheable no allocate" (for reads) or
+ "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
(forcibly enable), property absent (retain settings set by firmware)
- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
diff --git a/dts/Bindings/arm/marvell,kirkwood.txt b/dts/Bindings/arm/marvell,kirkwood.txt
index 4f40ff3..5171ad8 100644
--- a/dts/Bindings/arm/marvell,kirkwood.txt
+++ b/dts/Bindings/arm/marvell,kirkwood.txt
@@ -20,6 +20,8 @@ And in addition, the compatible shall be extended with the specific
board. Currently known boards are:
"buffalo,lschlv2"
+"buffalo,lswvl"
+"buffalo,lswxl"
"buffalo,lsxhl"
"buffalo,lsxl"
"dlink,dns-320"
diff --git a/dts/Bindings/arm/mediatek.txt b/dts/Bindings/arm/mediatek.txt
index dd7550a..618a919 100644
--- a/dts/Bindings/arm/mediatek.txt
+++ b/dts/Bindings/arm/mediatek.txt
@@ -1,12 +1,15 @@
-MediaTek mt65xx & mt81xx Platforms Device Tree Bindings
+MediaTek mt65xx, mt67xx & mt81xx Platforms Device Tree Bindings
-Boards with a MediaTek mt65xx/mt81xx SoC shall have the following property:
+Boards with a MediaTek mt65xx/mt67xx/mt81xx SoC shall have the
+following property:
Required root node property:
compatible: Must contain one of
+ "mediatek,mt6580"
"mediatek,mt6589"
"mediatek,mt6592"
+ "mediatek,mt6795"
"mediatek,mt8127"
"mediatek,mt8135"
"mediatek,mt8173"
@@ -14,12 +17,18 @@ compatible: Must contain one of
Supported boards:
+- Evaluation board for MT6580:
+ Required root node properties:
+ - compatible = "mediatek,mt6580-evbp1", "mediatek,mt6580";
- bq Aquaris5 smart phone:
Required root node properties:
- compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589";
- Evaluation board for MT6592:
Required root node properties:
- compatible = "mediatek,mt6592-evb", "mediatek,mt6592";
+- Evaluation board for MT6795(Helio X10):
+ Required root node properties:
+ - compatible = "mediatek,mt6795-evb", "mediatek,mt6795";
- MTK mt8127 tablet moose EVB:
Required root node properties:
- compatible = "mediatek,mt8127-moose", "mediatek,mt8127";
diff --git a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt b/dts/Bindings/arm/mediatek/mediatek,sysirq.txt
index 4f5a535..afef6a8 100644
--- a/dts/Bindings/arm/mediatek/mediatek,sysirq.txt
+++ b/dts/Bindings/arm/mediatek/mediatek,sysirq.txt
@@ -1,4 +1,4 @@
-Mediatek 65xx/81xx sysirq
++Mediatek 65xx/67xx/81xx sysirq
Mediatek SOCs sysirq support controllable irq inverter for each GIC SPI
interrupt.
@@ -8,9 +8,11 @@ Required properties:
"mediatek,mt8173-sysirq"
"mediatek,mt8135-sysirq"
"mediatek,mt8127-sysirq"
+ "mediatek,mt6795-sysirq"
"mediatek,mt6592-sysirq"
"mediatek,mt6589-sysirq"
"mediatek,mt6582-sysirq"
+ "mediatek,mt6580-sysirq"
"mediatek,mt6577-sysirq"
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in
diff --git a/dts/Bindings/arm/omap/omap.txt b/dts/Bindings/arm/omap/omap.txt
index 4f6a82c..9f4e513 100644
--- a/dts/Bindings/arm/omap/omap.txt
+++ b/dts/Bindings/arm/omap/omap.txt
@@ -135,6 +135,9 @@ Boards:
- AM335X OrionLXm : Substation Automation Platform
compatible = "novatech,am335x-lxm", "ti,am33xx"
+- AM335X phyBOARD-WEGA: Single Board Computer dev kit
+ compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"
+
- OMAP5 EVM : Evaluation Module
compatible = "ti,omap5-evm", "ti,omap5"
diff --git a/dts/Bindings/arm/pmu.txt b/dts/Bindings/arm/pmu.txt
index 3b5f5d1..435251f 100644
--- a/dts/Bindings/arm/pmu.txt
+++ b/dts/Bindings/arm/pmu.txt
@@ -26,13 +26,19 @@ Required properties:
Optional properties:
-- interrupt-affinity : Valid only when using SPIs, specifies a list of phandles
- to CPU nodes corresponding directly to the affinity of
+- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
+ nodes corresponding directly to the affinity of
the SPIs listed in the interrupts property.
- This property should be present when there is more than
+ When using a PPI, specifies a list of phandles to CPU
+ nodes corresponding to the set of CPUs which have
+ a PMU of this type signalling the PPI listed in the
+ interrupts property.
+
+ This property should be present when there is more than
a single SPI.
+
- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
events.
diff --git a/dts/Bindings/arm/rockchip.txt b/dts/Bindings/arm/rockchip.txt
index 60d4a1e..af58cd7 100644
--- a/dts/Bindings/arm/rockchip.txt
+++ b/dts/Bindings/arm/rockchip.txt
@@ -26,3 +26,38 @@ Rockchip platforms device tree bindings
- ChipSPARK PopMetal-RK3288 board:
Required root node properties:
- compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288";
+
+- Netxeon R89 board:
+ Required root node properties:
+ - compatible = "netxeon,r89", "rockchip,rk3288";
+
+- Google Jerry (Hisense Chromebook C11 and more):
+ Required root node properties:
+ - compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
+ "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
+ "google,veyron-jerry-rev3", "google,veyron-jerry",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Minnie (Asus Chromebook Flip C100P):
+ Required root node properties:
+ - compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
+ "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
+ "google,veyron-minnie-rev0", "google,veyron-minnie",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Pinky (dev-board):
+ Required root node properties:
+ - compatible = "google,veyron-pinky-rev2", "google,veyron-pinky",
+ "google,veyron", "rockchip,rk3288";
+
+- Google Speedy (Asus C201 Chromebook):
+ Required root node properties:
+ - compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8",
+ "google,veyron-speedy-rev7", "google,veyron-speedy-rev6",
+ "google,veyron-speedy-rev5", "google,veyron-speedy-rev4",
+ "google,veyron-speedy-rev3", "google,veyron-speedy-rev2",
+ "google,veyron-speedy", "google,veyron", "rockchip,rk3288";
+
+- Rockchip R88 board:
+ Required root node properties:
+ - compatible = "rockchip,r88", "rockchip,rk3368";
diff --git a/dts/Bindings/arm/sp810.txt b/dts/Bindings/arm/sp810.txt
new file mode 100644
index 0000000..6808fb5
--- /dev/null
+++ b/dts/Bindings/arm/sp810.txt
@@ -0,0 +1,46 @@
+SP810 System Controller
+-----------------------
+
+Required properties:
+
+- compatible: standard compatible string for a Primecell peripheral,
+ see Documentation/devicetree/bindings/arm/primecell.txt
+ for more details
+ should be: "arm,sp810", "arm,primecell"
+
+- reg: standard registers property, physical address and size
+ of the control registers
+
+- clock-names: from the common clock bindings, for more details see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt;
+ should be: "refclk", "timclk", "apb_pclk"
+
+- clocks: from the common clock bindings, phandle and clock
+ specifier pairs for the entries of clock-names property
+
+- #clock-cells: from the common clock bindings;
+ should be: <1>
+
+- clock-output-names: from the common clock bindings;
+ should be: "timerclken0", "timerclken1", "timerclken2", "timerclken3"
+
+- assigned-clocks: from the common clock binding;
+ should be: clock specifier for each output clock of this
+ provider node
+
+- assigned-clock-parents: from the common clock binding;
+ should be: phandle of input clock listed in clocks
+ property with the highest frequency
+
+Example:
+ v2m_sysctl: sysctl@020000 {
+ compatible = "arm,sp810", "arm,primecell";
+ reg = <0x020000 0x1000>;
+ clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
+ clock-names = "refclk", "timclk", "apb_pclk";
+ #clock-cells = <1>;
+ clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
+ assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
+ assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
+
+ };
diff --git a/dts/Bindings/clock/gpio-mux-clock.txt b/dts/Bindings/clock/gpio-mux-clock.txt
new file mode 100644
index 0000000..2be1e03
--- /dev/null
+++ b/dts/Bindings/clock/gpio-mux-clock.txt
@@ -0,0 +1,19 @@
+Binding for simple gpio clock multiplexer.
+
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+Required properties:
+- compatible : shall be "gpio-mux-clock".
+- clocks: list of two references to parent clocks.
+- #clock-cells : from common clock binding; shall be set to 0.
+- select-gpios : GPIO reference for selecting the parent clock.
+
+Example:
+ clock {
+ compatible = "gpio-mux-clock";
+ clocks = <&parentclk1>, <&parentclk2>;
+ #clock-cells = <0>;
+ select-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/dts/Bindings/clock/hi6220-clock.txt b/dts/Bindings/clock/hi6220-clock.txt
index 259e30a..e4d5fea 100644
--- a/dts/Bindings/clock/hi6220-clock.txt
+++ b/dts/Bindings/clock/hi6220-clock.txt
@@ -15,19 +15,36 @@ Required Properties:
- "hisilicon,hi6220-sysctrl"
- "hisilicon,hi6220-mediactrl"
- "hisilicon,hi6220-pmctrl"
+ - "hisilicon,hi6220-stub-clk"
- reg: physical base address of the controller and length of memory mapped
region.
- #clock-cells: should be 1.
-For example:
+Optional Properties:
+
+- hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
+ the driver need use the sram to pass parameters for frequency change.
+
+- mboxes: use the label reference for the mailbox as the first parameter, the
+ second parameter is the channel number.
+
+Example 1:
sys_ctrl: sys_ctrl@f7030000 {
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
};
+Example 2:
+ stub_clock: stub_clock {
+ compatible = "hisilicon,hi6220-stub-clk";
+ hisilicon,hi6220-clk-sram = <&sram>;
+ #clock-cells = <1>;
+ mboxes = <&mailbox 1>;
+ };
+
Each clock is assigned an identifier and client nodes use this identifier
to specify the clock which they consume.
diff --git a/dts/Bindings/clock/imx6ul-clock.txt b/dts/Bindings/clock/imx6ul-clock.txt
new file mode 100644
index 0000000..571d503
--- /dev/null
+++ b/dts/Bindings/clock/imx6ul-clock.txt
@@ -0,0 +1,13 @@
+* Clock bindings for Freescale i.MX6 UltraLite
+
+Required properties:
+- compatible: Should be "fsl,imx6ul-ccm"
+- reg: Address and length of the register set
+- #clock-cells: Should be <1>
+- clocks: list of clock specifiers, must contain an entry for each required
+ entry in clock-names
+- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
+
+The clock consumer should specify the desired clock by having the clock
+ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6ul-clock.h
+for the full list of i.MX6 UltraLite clock IDs.
diff --git a/dts/Bindings/clock/mt8173-cpu-dvfs.txt b/dts/Bindings/clock/mt8173-cpu-dvfs.txt
new file mode 100644
index 0000000..52b457c
--- /dev/null
+++ b/dts/Bindings/clock/mt8173-cpu-dvfs.txt
@@ -0,0 +1,83 @@
+Device Tree Clock bindins for CPU DVFS of Mediatek MT8173 SoC
+
+Required properties:
+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
+- clock-names: Should contain the following:
+ "cpu" - The multiplexer for clock input of CPU cluster.
+ "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
+ source (usually MAINPLL) when the original CPU PLL is under
+ transition and not stable yet.
+ Please refer to Documentation/devicetree/bindings/clk/clock-bindings.txt for
+ generic clock consumer properties.
+- proc-supply: Regulator for Vproc of CPU cluster.
+
+Optional properties:
+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
+ needs to do "voltage tracking" to step by step scale up/down Vproc and
+ Vsram to fit SoC specific needs. When absent, the voltage scaling
+ flow is handled by hardware, hence no software "voltage tracking" is
+ needed.
+
+Example:
+--------
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA53SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x101>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ clocks = <&infracfg CLK_INFRA_CA57SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ };
+
+ &cpu0 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu1 {
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ &cpu2 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
+
+ &cpu3 {
+ proc-supply = <&da9211_vcpu_reg>;
+ sram-supply = <&mt6397_vsramca7_reg>;
+ };
diff --git a/dts/Bindings/clock/nvidia,tegra124-dfll.txt b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
new file mode 100644
index 0000000..ee7e5fd
--- /dev/null
+++ b/dts/Bindings/clock/nvidia,tegra124-dfll.txt
@@ -0,0 +1,79 @@
+NVIDIA Tegra124 DFLL FCPU clocksource
+
+This binding uses the common clock binding:
+Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+The DFLL IP block on Tegra is a root clocksource designed for clocking
+the fast CPU cluster. It consists of a free-running voltage controlled
+oscillator connected to the CPU voltage rail (VDD_CPU), and a closed loop
+control module that will automatically adjust the VDD_CPU voltage by
+communicating with an off-chip PMIC either via an I2C bus or via PWM signals.
+Currently only the I2C mode is supported by these bindings.
+
+Required properties:
+- compatible : should be "nvidia,tegra124-dfll"
+- reg : Defines the following set of registers, in the order listed:
+ - registers for the DFLL control logic.
+ - registers for the I2C output logic.
+ - registers for the integrated I2C master controller.
+ - look-up table RAM for voltage register values.
+- interrupts: Should contain the DFLL block interrupt.
+- clocks: Must contain an entry for each entry in clock-names.
+ See clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - soc: Clock source for the DFLL control logic.
+ - ref: The closed loop reference clock
+ - i2c: Clock source for the integrated I2C master.
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - dvco: Reset control for the DFLL DVCO.
+- #clock-cells: Must be 0.
+- clock-output-names: Name of the clock output.
+- vdd-cpu-supply: Regulator for the CPU voltage rail that the DFLL
+ hardware will start controlling. The regulator will be queried for
+ the I2C register, control values and supported voltages.
+
+Required properties for the control loop parameters:
+- nvidia,sample-rate: Sample rate of the DFLL control loop.
+- nvidia,droop-ctrl: See the register CL_DVFS_DROOP_CTRL in the TRM.
+- nvidia,force-mode: See the field DFLL_PARAMS_FORCE_MODE in the TRM.
+- nvidia,cf: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM.
+- nvidia,ci: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM.
+- nvidia,cg: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM.
+
+Optional properties for the control loop parameters:
+- nvidia,cg-scale: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM.
+
+Required properties for I2C mode:
+- nvidia,i2c-fs-rate: I2C transfer rate, if using full speed mode.
+
+Example:
+
+clock@0,70110000 {
+ compatible = "nvidia,tegra124-dfll";
+ reg = <0 0x70110000 0 0x100>, /* DFLL control */
+ <0 0x70110000 0 0x100>, /* I2C output control */
+ <0 0x70110100 0 0x100>, /* Integrated I2C controller */
+ <0 0x70110200 0 0x100>; /* Look-up table RAM */
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
+ <&tegra_car TEGRA124_CLK_DFLL_REF>,
+ <&tegra_car TEGRA124_CLK_I2C5>;
+ clock-names = "soc", "ref", "i2c";
+ resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
+ reset-names = "dvco";
+ #clock-cells = <0>;
+ clock-output-names = "dfllCPU_out";
+ vdd-cpu-supply = <&vdd_cpu>;
+ status = "okay";
+
+ nvidia,sample-rate = <12500>;
+ nvidia,droop-ctrl = <0x00000f00>;
+ nvidia,force-mode = <1>;
+ nvidia,cf = <10>;
+ nvidia,ci = <0>;
+ nvidia,cg = <2>;
+
+ nvidia,i2c-fs-rate = <400000>;
+};
diff --git a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
index 2f3747f..e4cdaf1 100644
--- a/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7778 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7778. It includes two PLLs and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -10,10 +12,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are
"plla", "pllb", "b", "out", "p", "s", and "s1".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7778-cpg-clocks";
@@ -22,4 +32,17 @@ Example
clocks = <&extal_clk>;
clock-output-names = "plla", "pllb", "b",
"out", "p", "s", "s1";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sdhi0: sd@ffe4c000 {
+ compatible = "renesas,sdhi-r8a7778";
+ reg = <0xffe4c000 0x100>;
+ interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/dts/Bindings/clock/renesas,r8a7779-cpg-clocks.txt b/dts/Bindings/clock/renesas,r8a7779-cpg-clocks.txt
index ed3c8cb..8c81547 100644
--- a/dts/Bindings/clock/renesas,r8a7779-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,r8a7779-cpg-clocks.txt
@@ -1,7 +1,9 @@
* Renesas R8A7779 Clock Pulse Generator (CPG)
The CPG generates core clocks for the R8A7779. It includes one PLL and
-several fixed ratio dividers
+several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -12,16 +14,36 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "plla",
"z", "zs", "s", "s1", "p", "b", "out".
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@ffc80000 {
compatible = "renesas,r8a7779-cpg-clocks";
- reg = <0 0xffc80000 0 0x30>;
+ reg = <0xffc80000 0x30>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "plla", "z", "zs", "s", "s1", "p",
"b", "out";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ sata: sata@fc600000 {
+ compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
+ reg = <0xfc600000 0x2000>;
+ interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7779_CLK_SATA>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
index 56f111b..2a9a8ed 100644
--- a/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,rcar-gen2-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -20,10 +22,18 @@ Required Properties:
- clock-output-names: The names of the clocks. Supported clocks are "main",
"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
"adsp"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7790-cpg-clocks",
@@ -34,4 +44,16 @@ Example
clock-output-names = "main", "pll0, "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "sd1", "z",
"rcan", "adsp";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ thermal@e61f0000 {
+ compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
+ reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
+ power-domains = <&cpg_clocks>;
};
diff --git a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
index b0f7ddb..bb51a33 100644
--- a/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
+++ b/dts/Bindings/clock/renesas,rz-cpg-clocks.txt
@@ -2,6 +2,8 @@
The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
CPU and GPU clocks, and several fixed ratio dividers.
+The CPG also provides a Clock Domain for SoC devices, in combination with the
+CPG Module Stop (MSTP) Clocks.
Required Properties:
@@ -14,10 +16,18 @@ Required Properties:
- #clock-cells: Must be 1
- clock-output-names: The names of the clocks. Supported clocks are "pll",
"i", and "g"
+ - #power-domain-cells: Must be 0
+SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
+through an MSTP clock should refer to the CPG device node in their
+"power-domains" property, as documented by the generic PM domain bindings in
+Documentation/devicetree/bindings/power/power_domain.txt.
-Example
--------
+
+Examples
+--------
+
+ - CPG device node:
cpg_clocks: cpg_clocks@fcfe0000 {
#clock-cells = <1>;
@@ -26,4 +36,19 @@ Example
reg = <0xfcfe0000 0x18>;
clocks = <&extal_clk>, <&usb_x1_clk>;
clock-output-names = "pll", "i", "g";
+ #power-domain-cells = <0>;
+ };
+
+
+ - CPG/MSTP Clock Domain member device node:
+
+ mtu2: timer@fcff0000 {
+ compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
+ reg = <0xfcff0000 0x400>;
+ interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tgi0a";
+ clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
+ clock-names = "fck";
+ power-domains = <&cpg_clocks>;
+ status = "disabled";
};
diff --git a/dts/Bindings/clock/rockchip,rk3368-cru.txt b/dts/Bindings/clock/rockchip,rk3368-cru.txt
new file mode 100644
index 0000000..7c8bbcf
--- /dev/null
+++ b/dts/Bindings/clock/rockchip,rk3368-cru.txt
@@ -0,0 +1,61 @@
+* Rockchip RK3368 Clock and Reset Unit
+
+The RK3368 clock controller generates and supplies clock to various
+controllers within the SoC and also implements a reset controller for SoC
+peripherals.
+
+Required Properties:
+
+- compatible: should be "rockchip,rk3368-cru"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Optional Properties:
+
+- rockchip,grf: phandle to the syscon managing the "general register files"
+ If missing, pll rates are not changeable, due to the missing pll lock status.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume. All available clocks are defined as
+preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
+used in device tree sources. Similar macros exist for the reset sources in
+these files.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It is expected
+that they are defined using standard clock bindings with following
+clock-output-names:
+ - "xin24m" - crystal input - required,
+ - "xin32k" - rtc clock - optional,
+ - "ext_i2s" - external I2S clock - optional,
+ - "ext_gmac" - external GMAC clock - optional
+ - "ext_hsadc" - external HSADC clock - optional,
+ - "ext_isp" - external ISP clock - optional,
+ - "ext_jtag" - external JTAG clock - optional
+ - "ext_vip" - external VIP clock - optional,
+ - "usbotg_out" - output clock of the pll in the otg phy
+
+Example: Clock controller node:
+
+ cru: clock-controller@ff760000 {
+ compatible = "rockchip,rk3368-cru";
+ reg = <0x0 0xff760000 0x0 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+Example: UART controller node that consumes the clock generated by the clock
+ controller:
+
+ uart0: serial@10124000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10124000 0x400>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ clocks = <&cru SCLK_UART0>;
+ };
diff --git a/dts/Bindings/clock/st/st,clkgen-pll.txt b/dts/Bindings/clock/st/st,clkgen-pll.txt
index efb51cf..d8b168e 100644
--- a/dts/Bindings/clock/st/st,clkgen-pll.txt
+++ b/dts/Bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_0", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"
diff --git a/dts/Bindings/clock/ux500.txt b/dts/Bindings/clock/ux500.txt
new file mode 100644
index 0000000..e52bd4b
--- /dev/null
+++ b/dts/Bindings/clock/ux500.txt
@@ -0,0 +1,64 @@
+Clock bindings for ST-Ericsson Ux500 clocks
+
+Required properties :
+- compatible : shall contain only one of the following:
+ "stericsson,u8500-clks"
+ "stericsson,u8540-clks"
+ "stericsson,u9540-clks"
+- reg : shall contain base register location and length for
+ CLKRST1, 2, 3, 5, and 6 in an array. Note the absence of
+ CLKRST4, which does not exist.
+
+Required subnodes:
+- prcmu-clock: a subnode with one clock cell for PRCMU (power,
+ reset, control unit) clocks. The cell indicates which PRCMU
+ clock in the prcmu-clock node the consumer wants to use.
+- prcc-periph-clock: a subnode with two clock cells for
+ PRCC (programmable reset- and clock controller) peripheral clocks.
+ The first cell indicates which PRCC block the consumer
+ wants to use, possible values are 1, 2, 3, 5, 6. The second
+ cell indicates which clock inside the PRCC block it wants,
+ possible values are 0 thru 31.
+- prcc-kernel-clock: a subnode with two clock cells for
+ PRCC (programmable reset- and clock controller) kernel clocks
+ The first cell indicates which PRCC block the consumer
+ wants to use, possible values are 1, 2, 3, 5, 6. The second
+ cell indicates which clock inside the PRCC block it wants,
+ possible values are 0 thru 31.
+- rtc32k-clock: a subnode with zero clock cells for the 32kHz
+ RTC clock.
+- smp-twd-clock: a subnode for the ARM SMP Timer Watchdog cluster
+ with zero clock cells.
+
+Example:
+
+clocks {
+ compatible = "stericsson,u8500-clks";
+ /*
+ * Registers for the CLKRST block on peripheral
+ * groups 1, 2, 3, 5, 6,
+ */
+ reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>,
+ <0x8000f000 0x1000>, <0xa03ff000 0x1000>,
+ <0xa03cf000 0x1000>;
+
+ prcmu_clk: prcmu-clock {
+ #clock-cells = <1>;
+ };
+
+ prcc_pclk: prcc-periph-clock {
+ #clock-cells = <2>;
+ };
+
+ prcc_kclk: prcc-kernel-clock {
+ #clock-cells = <2>;
+ };
+
+ rtc_clk: rtc32k-clock {
+ #clock-cells = <0>;
+ };
+
+ smp_twd_clk: smp-twd-clock {
+ #clock-cells = <0>;
+ };
+};
diff --git a/dts/Bindings/cpufreq/tegra124-cpufreq.txt b/dts/Bindings/cpufreq/tegra124-cpufreq.txt
new file mode 100644
index 0000000..b1669fb
--- /dev/null
+++ b/dts/Bindings/cpufreq/tegra124-cpufreq.txt
@@ -0,0 +1,44 @@
+Tegra124 CPU frequency scaling driver bindings
+----------------------------------------------
+
+Both required and optional properties listed below must be defined
+under node /cpus/cpu@0.
+
+Required properties:
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - cpu_g: Clock mux for the fast CPU cluster.
+ - cpu_lp: Clock mux for the low-power CPU cluster.
+ - pll_x: Fast PLL clocksource.
+ - pll_p: Auxiliary PLL used during fast PLL rate changes.
+ - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
+- vdd-cpu-supply: Regulator for CPU voltage
+
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock,
+ in unit of nanoseconds.
+
+Example:
+--------
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+
+ clocks = <&tegra_car TEGRA124_CLK_CCLK_G>,
+ <&tegra_car TEGRA124_CLK_CCLK_LP>,
+ <&tegra_car TEGRA124_CLK_PLL_X>,
+ <&tegra_car TEGRA124_CLK_PLL_P>,
+ <&dfll>;
+ clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
+ clock-latency = <300000>;
+ vdd-cpu-supply: <&vdd_cpu>;
+ };
+
+ <...>
+};
diff --git a/dts/Bindings/crypto/fsl-sec4.txt b/dts/Bindings/crypto/fsl-sec4.txt
index e402277..6831d02 100644
--- a/dts/Bindings/crypto/fsl-sec4.txt
+++ b/dts/Bindings/crypto/fsl-sec4.txt
@@ -106,6 +106,18 @@ PROPERTIES
to the interrupt parent to which the child domain
is being mapped.
+ - clocks
+ Usage: required if SEC 4.0 requires explicit enablement of clocks
+ Value type: <prop_encoded-array>
+ Definition: A list of phandle and clock specifier pairs describing
+ the clocks required for enabling and disabling SEC 4.0.
+
+ - clock-names
+ Usage: required if SEC 4.0 requires explicit enablement of clocks
+ Value type: <string>
+ Definition: A list of clock name strings in the same order as the
+ clocks property.
+
Note: All other standard properties (see the ePAPR) are allowed
but are optional.
@@ -120,6 +132,11 @@ EXAMPLE
ranges = <0 0x300000 0x10000>;
interrupt-parent = <&mpic>;
interrupts = <92 2>;
+ clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
+ <&clks IMX6QDL_CLK_CAAM_ACLK>,
+ <&clks IMX6QDL_CLK_CAAM_IPG>,
+ <&clks IMX6QDL_CLK_EIM_SLOW>;
+ clock-names = "mem", "aclk", "ipg", "emi_slow";
};
=====================================================================
@@ -288,12 +305,13 @@ Secure Non-Volatile Storage (SNVS) Node
Node defines address range and the associated
interrupt for the SNVS function. This function
monitors security state information & reports
- security violations.
+ security violations. This also included rtc,
+ system power off and ON/OFF key.
- compatible
Usage: required
Value type: <string>
- Definition: Must include "fsl,sec-v4.0-mon".
+ Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
- reg
Usage: required
@@ -324,7 +342,7 @@ Secure Non-Volatile Storage (SNVS) Node
the child address, parent address, & length.
- interrupts
- Usage: required
+ Usage: optional
Value type: <prop_encoded-array>
Definition: Specifies the interrupts generated by this
device. The value of the interrupts property
@@ -341,7 +359,7 @@ Secure Non-Volatile Storage (SNVS) Node
EXAMPLE
sec_mon@314000 {
- compatible = "fsl,sec-v4.0-mon";
+ compatible = "fsl,sec-v4.0-mon", "syscon";
reg = <0x314000 0x1000>;
ranges = <0 0x314000 0x1000>;
interrupt-parent = <&mpic>;
@@ -358,16 +376,72 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
Value type: <string>
Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
- - reg
+ - interrupts
Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical
- address and length of the SNVS LP configuration registers.
+ Value type: <prop_encoded-array>
+ Definition: Specifies the interrupts generated by this
+ device. The value of the interrupts property
+ consists of one interrupt specifier. The format
+ of the specifier is defined by the binding document
+ describing the node's interrupt parent.
+
+ - regmap
+ Usage: required
+ Value type: <phandle>
+ Definition: this is phandle to the register map node.
+
+ - offset
+ Usage: option
+ value type: <u32>
+ Definition: LP register offset. default it is 0x34.
EXAMPLE
- sec_mon_rtc_lp@314000 {
+ sec_mon_rtc_lp@1 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
- reg = <0x34 0x58>;
+ interrupts = <93 2>;
+ regmap = <&snvs>;
+ offset = <0x34>;
+ };
+
+=====================================================================
+System ON/OFF key driver
+
+ The snvs-pwrkey is designed to enable POWER key function which controlled
+ by SNVS ONOFF, the driver can report the status of POWER key and wakeup
+ system if pressed after system suspend.
+
+ - compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Mush include "fsl,sec-v4.0-pwrkey".
+
+ - interrupts:
+ Usage: required
+ Value type: <prop_encoded-array>
+ Definition: The SNVS ON/OFF interrupt number to the CPU(s).
+
+ - linux,keycode:
+ Usage: option
+ Value type: <int>
+ Definition: Keycode to emit, KEY_POWER by default.
+
+ - wakeup-source:
+ Usage: option
+ Value type: <boo>
+ Definition: Button can wake-up the system.
+
+ - regmap:
+ Usage: required:
+ Value type: <phandle>
+ Definition: this is phandle to the register map node.
+
+EXAMPLE:
+ snvs-pwrkey@0x020cc000 {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&snvs>;
+ interrupts = <0 4 0x4>
+ linux,keycode = <116>; /* KEY_POWER */
+ wakeup;
};
=====================================================================
@@ -443,12 +517,20 @@ FULL EXAMPLE
compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
ranges = <0 0x314000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <93 2>;
sec_mon_rtc_lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
- reg = <0x34 0x58>;
+ regmap = <&sec_mon>;
+ offset = <0x34>;
+ interrupts = <93 2>;
+ };
+
+ snvs-pwrkey@0x020cc000 {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&sec_mon>;
+ interrupts = <0 4 0x4>;
+ linux,keycode = <116>; /* KEY_POWER */
+ wakeup;
};
};
diff --git a/dts/Bindings/crypto/sun4i-ss.txt b/dts/Bindings/crypto/sun4i-ss.txt
new file mode 100644
index 0000000..5d38e9b
--- /dev/null
+++ b/dts/Bindings/crypto/sun4i-ss.txt
@@ -0,0 +1,23 @@
+* Allwinner Security System found on A20 SoC
+
+Required properties:
+- compatible : Should be "allwinner,sun4i-a10-crypto".
+- reg: Should contain the Security System register location and length.
+- interrupts: Should contain the IRQ line for the Security System.
+- clocks : List of clock specifiers, corresponding to ahb and ss.
+- clock-names : Name of the functional clock, should be
+ * "ahb" : AHB gating clock
+ * "mod" : SS controller clock
+
+Optional properties:
+ - resets : phandle + reset specifier pair
+ - reset-names : must contain "ahb"
+
+Example:
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ahb_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ };
diff --git a/dts/Bindings/devfreq/event/exynos-ppmu.txt b/dts/Bindings/devfreq/event/exynos-ppmu.txt
index b54bf3a..3e36c1d 100644
--- a/dts/Bindings/devfreq/event/exynos-ppmu.txt
+++ b/dts/Bindings/devfreq/event/exynos-ppmu.txt
@@ -11,15 +11,14 @@ to various devfreq devices. The devfreq devices would use the event data when
derterming the current state of each IP.
Required properties:
-- compatible: Should be "samsung,exynos-ppmu".
+- compatible: Should be "samsung,exynos-ppmu" or "samsung,exynos-ppmu-v2.
- reg: physical base address of each PPMU and length of memory mapped region.
Optional properties:
- clock-names : the name of clock used by the PPMU, "ppmu"
- clocks : phandles for clock specified in "clock-names" property
-- #clock-cells: should be 1.
-Example1 : PPMU nodes in exynos3250.dtsi are listed below.
+Example1 : PPMUv1 nodes in exynos3250.dtsi are listed below.
ppmu_dmc0: ppmu_dmc0@106a0000 {
compatible = "samsung,exynos-ppmu";
@@ -108,3 +107,41 @@ Example2 : Events of each PPMU node in exynos3250-rinato.dts are listed below.
};
};
};
+
+Example3 : PPMUv2 nodes in exynos5433.dtsi are listed below.
+
+ ppmu_d0_cpu: ppmu_d0_cpu@10480000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x10480000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d0_general: ppmu_d0_general@10490000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x10490000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d0_rt: ppmu_d0_rt@104a0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104a0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_cpu: ppmu_d1_cpu@104b0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104b0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_general: ppmu_d1_general@104c0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104c0000 0x2000>;
+ status = "disabled";
+ };
+
+ ppmu_d1_rt: ppmu_d1_rt@104d0000 {
+ compatible = "samsung,exynos-ppmu-v2";
+ reg = <0x104d0000 0x2000>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/dma/adi,axi-dmac.txt b/dts/Bindings/dma/adi,axi-dmac.txt
new file mode 100644
index 0000000..47cb1d1
--- /dev/null
+++ b/dts/Bindings/dma/adi,axi-dmac.txt
@@ -0,0 +1,61 @@
+Analog Device AXI-DMAC DMA controller
+
+Required properties:
+ - compatible: Must be "adi,axi-dmac-1.00.a".
+ - reg: Specification for the controllers memory mapped register map.
+ - interrupts: Specification for the controllers interrupt.
+ - clocks: Phandle and specifier to the controllers AXI interface clock
+ - #dma-cells: Must be 1.
+
+Required sub-nodes:
+ - adi,channels: This sub-node must contain a sub-node for each DMA channel. For
+ the channel sub-nodes the following bindings apply. They must match the
+ configuration options of the peripheral as it was instantiated.
+
+Required properties for adi,channels sub-node:
+ - #size-cells: Must be 0
+ - #address-cells: Must be 1
+
+Required channel sub-node properties:
+ - reg: Which channel this node refers to.
+ - adi,length-width: Width of the DMA transfer length register.
+ - adi,source-bus-width,
+ adi,destination-bus-width: Width of the source or destination bus in bits.
+ - adi,source-bus-type,
+ adi,destination-bus-type: Type of the source or destination bus. Must be one
+ of the following:
+ 0 (AXI_DMAC_TYPE_AXI_MM): Memory mapped AXI interface
+ 1 (AXI_DMAC_TYPE_AXI_STREAM): Streaming AXI interface
+ 2 (AXI_DMAC_TYPE_AXI_FIFO): FIFO interface
+
+Optional channel properties:
+ - adi,cyclic: Must be set if the channel supports hardware cyclic DMA
+ transfers.
+ - adi,2d: Must be set if the channel supports hardware 2D DMA transfers.
+
+DMA clients connected to the AXI-DMAC DMA controller must use the format
+described in the dma.txt file using a one-cell specifier. The value of the
+specifier refers to the DMA channel index.
+
+Example:
+
+dma: dma@7c420000 {
+ compatible = "adi,axi-dmac-1.00.a";
+ reg = <0x7c420000 0x10000>;
+ interrupts = <0 57 0>;
+ clocks = <&clkc 16>;
+ #dma-cells = <1>;
+
+ adi,channels {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ dma-channel@0 {
+ reg = <0>;
+ adi,source-bus-width = <32>;
+ adi,source-bus-type = <ADI_AXI_DMAC_TYPE_MM_AXI>;
+ adi,destination-bus-width = <64>;
+ adi,destination-bus-type = <ADI_AXI_DMAC_TYPE_FIFO>;
+ };
+ };
+};
diff --git a/dts/Bindings/dma/arm-pl08x.txt b/dts/Bindings/dma/arm-pl08x.txt
new file mode 100644
index 0000000..8a0097a
--- /dev/null
+++ b/dts/Bindings/dma/arm-pl08x.txt
@@ -0,0 +1,54 @@
+* ARM PrimeCells PL080 and PL081 and derivatives DMA controller
+
+Required properties:
+- compatible: "arm,pl080", "arm,primecell";
+ "arm,pl081", "arm,primecell";
+- reg: Address range of the PL08x registers
+- interrupt: The PL08x interrupt number
+- clocks: The clock running the IP core clock
+- clock-names: Must contain "apb_pclk"
+- lli-bus-interface-ahb1: if AHB master 1 is eligible for fetching LLIs
+- lli-bus-interface-ahb2: if AHB master 2 is eligible for fetching LLIs
+- mem-bus-interface-ahb1: if AHB master 1 is eligible for fetching memory contents
+- mem-bus-interface-ahb2: if AHB master 2 is eligible for fetching memory contents
+- #dma-cells: must be <2>. First cell should contain the DMA request,
+ second cell should contain either 1 or 2 depending on
+ which AHB master that is used.
+
+Optional properties:
+- dma-channels: contains the total number of DMA channels supported by the DMAC
+- dma-requests: contains the total number of DMA requests supported by the DMAC
+- memcpy-burst-size: the size of the bursts for memcpy: 1, 4, 8, 16, 32
+ 64, 128 or 256 bytes are legal values
+- memcpy-bus-width: the bus width used for memcpy: 8, 16 or 32 are legal
+ values
+
+Clients
+Required properties:
+- dmas: List of DMA controller phandle, request channel and AHB master id
+- dma-names: Names of the aforementioned requested channels
+
+Example:
+
+dmac0: dma-controller@10130000 {
+ compatible = "arm,pl080", "arm,primecell";
+ reg = <0x10130000 0x1000>;
+ interrupt-parent = <&vica>;
+ interrupts = <15>;
+ clocks = <&hclkdma0>;
+ clock-names = "apb_pclk";
+ lli-bus-interface-ahb1;
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+ #dma-cells = <2>;
+};
+
+device@40008000 {
+ ...
+ dmas = <&dmac0 0 2
+ &dmac0 1 2>;
+ dma-names = "tx", "rx";
+ ...
+};
diff --git a/dts/Bindings/dma/lpc1850-dmamux.txt b/dts/Bindings/dma/lpc1850-dmamux.txt
new file mode 100644
index 0000000..87740ad
--- /dev/null
+++ b/dts/Bindings/dma/lpc1850-dmamux.txt
@@ -0,0 +1,54 @@
+NXP LPC18xx/43xx DMA MUX (DMA request router)
+
+Required properties:
+- compatible: "nxp,lpc1850-dmamux"
+- reg: Memory map for accessing module
+- #dma-cells: Should be set to <3>.
+ * 1st cell contain the master dma request signal
+ * 2nd cell contain the mux value (0-3) for the peripheral
+ * 3rd cell contain either 1 or 2 depending on the AHB
+ master used.
+- dma-requests: Number of DMA requests for the mux
+- dma-masters: phandle pointing to the DMA controller
+
+The DMA controller node need to have the following poroperties:
+- dma-requests: Number of DMA requests the controller can handle
+
+Example:
+
+dmac: dma@40002000 {
+ compatible = "nxp,lpc1850-gpdma", "arm,pl080", "arm,primecell";
+ arm,primecell-periphid = <0x00041080>;
+ reg = <0x40002000 0x1000>;
+ interrupts = <2>;
+ clocks = <&ccu1 CLK_CPU_DMA>;
+ clock-names = "apb_pclk";
+ #dma-cells = <2>;
+ dma-channels = <8>;
+ dma-requests = <16>;
+ lli-bus-interface-ahb1;
+ lli-bus-interface-ahb2;
+ mem-bus-interface-ahb1;
+ mem-bus-interface-ahb2;
+ memcpy-burst-size = <256>;
+ memcpy-bus-width = <32>;
+};
+
+dmamux: dma-mux {
+ compatible = "nxp,lpc1850-dmamux";
+ #dma-cells = <3>;
+ dma-requests = <64>;
+ dma-masters = <&dmac>;
+};
+
+uart0: serial@40081000 {
+ compatible = "nxp,lpc1850-uart", "ns16550a";
+ reg = <0x40081000 0x1000>;
+ reg-shift = <2>;
+ interrupts = <24>;
+ clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
+ clock-names = "uartclk", "reg";
+ dmas = <&dmamux 1 1 2
+ &dmamux 2 1 2>;
+ dma-names = "tx", "rx";
+};
diff --git a/dts/Bindings/dma/mv-xor.txt b/dts/Bindings/dma/mv-xor.txt
index cc29c35..276ef81 100644
--- a/dts/Bindings/dma/mv-xor.txt
+++ b/dts/Bindings/dma/mv-xor.txt
@@ -12,10 +12,13 @@ XOR engine has. Those sub-nodes have the following required
properties:
- interrupts: interrupt of the XOR channel
-And the following optional properties:
+The sub-nodes used to contain one or several of the following
+properties, but they are now deprecated:
- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations
- dmacap,memset to indicate that the XOR channel is capable of memset operations
- dmacap,xor to indicate that the XOR channel is capable of xor operations
+- dmacap,interrupt to indicate that the XOR channel is capable of
+ generating interrupts
Example:
@@ -28,13 +31,8 @@ xor@d0060900 {
xor00 {
interrupts = <51>;
- dmacap,memcpy;
- dmacap,xor;
};
xor01 {
interrupts = <52>;
- dmacap,memcpy;
- dmacap,xor;
- dmacap,memset;
};
};
diff --git a/dts/Bindings/dma/sun4i-dma.txt b/dts/Bindings/dma/sun4i-dma.txt
new file mode 100644
index 0000000..f1634a2
--- /dev/null
+++ b/dts/Bindings/dma/sun4i-dma.txt
@@ -0,0 +1,46 @@
+Allwinner A10 DMA Controller
+
+This driver follows the generic DMA bindings defined in dma.txt.
+
+Required properties:
+
+- compatible: Must be "allwinner,sun4i-a10-dma"
+- reg: Should contain the registers base address and length
+- interrupts: Should contain a reference to the interrupt used by this device
+- clocks: Should contain a reference to the parent AHB clock
+- #dma-cells : Should be 2, first cell denoting normal or dedicated dma,
+ second cell holding the request line number.
+
+Example:
+ dma: dma-controller@01c02000 {
+ compatible = "allwinner,sun4i-a10-dma";
+ reg = <0x01c02000 0x1000>;
+ interrupts = <27>;
+ clocks = <&ahb_gates 6>;
+ #dma-cells = <2>;
+ };
+
+Clients:
+
+DMA clients connected to the Allwinner A10 DMA controller must use the
+format described in the dma.txt file, using a three-cell specifier for
+each channel: a phandle plus two integer cells.
+The three cells in order are:
+
+1. A phandle pointing to the DMA controller.
+2. Whether it is using normal (0) or dedicated (1) channels
+3. The port ID as specified in the datasheet
+
+Example:
+ spi2: spi@01c17000 {
+ compatible = "allwinner,sun4i-a10-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <0 12 4>;
+ clocks = <&ahb_gates 22>, <&spi2_clk>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 1 29>, <&dma 1 28>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
diff --git a/dts/Bindings/dma/zxdma.txt b/dts/Bindings/dma/zxdma.txt
new file mode 100644
index 0000000..3207ceb
--- /dev/null
+++ b/dts/Bindings/dma/zxdma.txt
@@ -0,0 +1,38 @@
+* ZTE ZX296702 DMA controller
+
+Required properties:
+- compatible: Should be "zte,zx296702-dma"
+- reg: Should contain DMA registers location and length.
+- interrupts: Should contain one interrupt shared by all channel
+- #dma-cells: see dma.txt, should be 1, para number
+- dma-channels: physical channels supported
+- dma-requests: virtual channels supported, each virtual channel
+ have specific request line
+- clocks: clock required
+
+Example:
+
+Controller:
+ dma: dma-controller@0x09c00000{
+ compatible = "zte,zx296702-dma";
+ reg = <0x09c00000 0x1000>;
+ clocks = <&topclk ZX296702_DMA_ACLK>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <24>;
+ dma-requests = <24>;
+ };
+
+Client:
+Use specific request line passing from dmax
+For example, spdif0 tx channel request line is 4
+ spdif0: spdif0@0b004000 {
+ #sound-dai-cells = <0>;
+ compatible = "zte,zx296702-spdif";
+ reg = <0x0b004000 0x1000>;
+ clocks = <&lsp0clk ZX296702_SPDIF0_DIV>;
+ clock-names = "tx";
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dma 4>;
+ dma-names = "tx";
+ }
diff --git a/dts/Bindings/drm/msm/dsi.txt b/dts/Bindings/drm/msm/dsi.txt
index cd8fe6c..d56923c 100644
--- a/dts/Bindings/drm/msm/dsi.txt
+++ b/dts/Bindings/drm/msm/dsi.txt
@@ -30,20 +30,27 @@ Optional properties:
- panel@0: Node of panel connected to this DSI controller.
See files in Documentation/devicetree/bindings/panel/ for each supported
panel.
-- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is
+- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
driving a panel which needs 2 DSI links.
-- qcom,master-panel: Boolean value indicating if the DSI controller is driving
+- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
the master link of the 2-DSI panel.
-- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is
+- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
driving a 2-DSI panel whose 2 links need receive command simultaneously.
- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
through MDP block
+- pinctrl-names: the pin control state names; should contain "default"
+- pinctrl-0: the default pinctrl state (active)
+- pinctrl-n: the "sleep" pinctrl state
+- port: DSI controller output port. This contains one endpoint subnode, with its
+ remote-endpoint set to the phandle of the connected panel's endpoint.
+ See Documentation/devicetree/bindings/graph.txt for device graph info.
DSI PHY:
Required properties:
- compatible: Could be the following
* "qcom,dsi-phy-28nm-hpm"
* "qcom,dsi-phy-28nm-lp"
+ * "qcom,dsi-phy-20nm"
- reg: Physical base address and length of the registers of PLL, PHY and PHY
regulator
- reg-names: The names of register regions. The following regions are required:
@@ -59,6 +66,10 @@ Required properties:
* "iface_clk"
- vddio-supply: phandle to vdd-io regulator device node
+Optional properties:
+- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
+ regulator is wanted.
+
Example:
mdss_dsi0: qcom,mdss_dsi@fd922800 {
compatible = "qcom,mdss-dsi-ctrl";
@@ -90,9 +101,13 @@ Example:
qcom,dsi-phy = <&mdss_dsi_phy0>;
- qcom,dual-panel-mode;
- qcom,master-panel;
- qcom,sync-dual-panel;
+ qcom,dual-dsi-mode;
+ qcom,master-dsi;
+ qcom,sync-dual-dsi;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mdss_dsi_active>;
+ pinctrl-1 = <&mdss_dsi_suspend>;
panel: panel@0 {
compatible = "sharp,lq101r1sx01";
@@ -101,6 +116,18 @@ Example:
power-supply = <...>;
backlight = <...>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+
+ port {
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
};
};
@@ -117,4 +144,6 @@ Example:
clock-names = "iface_clk";
clocks = <&mmcc MDSS_AHB_CLK>;
vddio-supply = <&pma8084_l12>;
+
+ qcom,dsi-phy-regulator-ldo-mode;
};
diff --git a/dts/Bindings/drm/msm/hdmi.txt b/dts/Bindings/drm/msm/hdmi.txt
index c43aa53..e926239 100644
--- a/dts/Bindings/drm/msm/hdmi.txt
+++ b/dts/Bindings/drm/msm/hdmi.txt
@@ -2,8 +2,9 @@ Qualcomm adreno/snapdragon hdmi output
Required properties:
- compatible: one of the following
+ * "qcom,hdmi-tx-8994"
* "qcom,hdmi-tx-8084"
- * "qcom,hdmi-tx-8074"
+ * "qcom,hdmi-tx-8974"
* "qcom,hdmi-tx-8660"
* "qcom,hdmi-tx-8960"
- reg: Physical base address and length of the controller's registers
diff --git a/dts/Bindings/extcon/extcon-palmas.txt b/dts/Bindings/extcon/extcon-palmas.txt
index 45414bb..f61d5af 100644
--- a/dts/Bindings/extcon/extcon-palmas.txt
+++ b/dts/Bindings/extcon/extcon-palmas.txt
@@ -10,8 +10,11 @@ Required Properties:
Optional Properties:
- ti,wakeup : To enable the wakeup comparator in probe
- - ti,enable-id-detection: Perform ID detection.
+ - ti,enable-id-detection: Perform ID detection. If id-gpio is specified
+ it performs id-detection using GPIO else using OTG core.
- ti,enable-vbus-detection: Perform VBUS detection.
+ - id-gpio: gpio for GPIO ID detection. See gpio binding.
+ - debounce-delay-ms: debounce delay for GPIO ID pin in milliseconds.
palmas-usb {
compatible = "ti,twl6035-usb", "ti,palmas-usb";
diff --git a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt
index 435f1bc..b405b44 100644
--- a/dts/Bindings/gpio/brcm,brcmstb-gpio.txt
+++ b/dts/Bindings/gpio/brcm,brcmstb-gpio.txt
@@ -33,6 +33,13 @@ Optional properties:
- interrupt-parent:
phandle of the parent interrupt controller
+- interrupts-extended:
+ Alternate form of specifying interrupts and parents that allows for
+ multiple parents. This takes precedence over 'interrupts' and
+ 'interrupt-parent'. Wakeup-capable GPIO controllers often route their
+ wakeup interrupt lines through a different interrupt controller than the
+ primary interrupt line, making this property necessary.
+
- #interrupt-cells:
Should be <2>. The first cell is the GPIO number, the second should specify
flags. The following subset of flags is supported:
@@ -47,19 +54,33 @@ Optional properties:
- interrupt-controller:
Marks the device node as an interrupt controller
-- interrupt-names:
- The name of the IRQ resource used by this controller
+- wakeup-source:
+ GPIOs for this controller can be used as a wakeup source
Example:
upg_gio: gpio@f040a700 {
- #gpio-cells = <0x2>;
- #interrupt-cells = <0x2>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
gpio-controller;
interrupt-controller;
reg = <0xf040a700 0x80>;
- interrupt-parent = <0xf>;
+ interrupt-parent = <&irq0_intc>;
+ interrupts = <0x6>;
+ brcm,gpio-bank-widths = <32 32 32 24>;
+ };
+
+ upg_gio_aon: gpio@f04172c0 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0xf04172c0 0x40>;
+ interrupt-parent = <&irq0_aon_intc>;
interrupts = <0x6>;
- interrupt-names = "upg_gio";
- brcm,gpio-bank-widths = <0x20 0x20 0x20 0x18>;
+ interrupts-extended = <&irq0_aon_intc 0x6>,
+ <&aon_pm_l2_intc 0x5>;
+ wakeup-source;
+ brcm,gpio-bank-widths = <18 4>;
};
diff --git a/dts/Bindings/gpio/gpio-etraxfs.txt b/dts/Bindings/gpio/gpio-etraxfs.txt
index abf4db7..170194a 100644
--- a/dts/Bindings/gpio/gpio-etraxfs.txt
+++ b/dts/Bindings/gpio/gpio-etraxfs.txt
@@ -2,8 +2,9 @@ Axis ETRAX FS General I/O controller bindings
Required properties:
-- compatible:
+- compatible: one of:
- "axis,etraxfs-gio"
+ - "axis,artpec3-gio"
- reg: Physical base address and length of the controller's registers.
- #gpio-cells: Should be 3
- The first cell is the gpio offset number.
diff --git a/dts/Bindings/gpio/gpio-mpc8xxx.txt b/dts/Bindings/gpio/gpio-mpc8xxx.txt
new file mode 100644
index 0000000..805ddcd
--- /dev/null
+++ b/dts/Bindings/gpio/gpio-mpc8xxx.txt
@@ -0,0 +1,22 @@
+* Freescale MPC512x/MPC8xxx GPIO controller
+
+Required properties:
+- compatible : Should be "fsl,<soc>-gpio"
+ The following <soc>s are known to be supported:
+ mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq
+- reg : Address and length of the register set for the device
+- interrupts : Should be the port interrupt shared by all 32 pins.
+- #gpio-cells : Should be two. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+
+Example:
+
+gpio0: gpio@1100 {
+ compatible = "fsl,mpc5125-gpio";
+ #gpio-cells = <2>;
+ reg = <0x1100 0x080>;
+ interrupts = <78 0x8>;
+ status = "okay";
+};
diff --git a/dts/Bindings/gpio/renesas,gpio-rcar.txt b/dts/Bindings/gpio/renesas,gpio-rcar.txt
index 38fb86f..f60e2f4 100644
--- a/dts/Bindings/gpio/renesas,gpio-rcar.txt
+++ b/dts/Bindings/gpio/renesas,gpio-rcar.txt
@@ -9,6 +9,7 @@ Required Properties:
- "renesas,gpio-r8a7791": for R8A7791 (R-Car M2-W) compatible GPIO controller.
- "renesas,gpio-r8a7793": for R8A7793 (R-Car M2-N) compatible GPIO controller.
- "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO controller.
+ - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO controller.
- "renesas,gpio-rcar": for generic R-Car GPIO controller.
- reg: Base address and length of each memory resource used by the GPIO
diff --git a/dts/Bindings/gpio/zx296702-gpio.txt b/dts/Bindings/gpio/zx296702-gpio.txt
new file mode 100644
index 0000000..0dab156
--- /dev/null
+++ b/dts/Bindings/gpio/zx296702-gpio.txt
@@ -0,0 +1,24 @@
+ZTE ZX296702 GPIO controller
+
+Required properties:
+- compatible : "zte,zx296702-gpio"
+- #gpio-cells : Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters:
+ - bit 0 specifies polarity (0 for normal, 1 for inverted)
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupts : Interrupt mapping for GPIO IRQ.
+- gpio-ranges : Interaction with the PINCTRL subsystem.
+
+gpio1: gpio@b008040 {
+ compatible = "zte,zx296702-gpio";
+ reg = <0xb008040 0x40>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clock-names = "gpio_pclk";
+ clocks = <&lsp0clk ZX296702_GPIO_CLK>;
+};
diff --git a/dts/Bindings/gpu/nvidia,tegra20-host1x.txt b/dts/Bindings/gpu/nvidia,tegra20-host1x.txt
index 009f4bf..e685610 100644
--- a/dts/Bindings/gpu/nvidia,tegra20-host1x.txt
+++ b/dts/Bindings/gpu/nvidia,tegra20-host1x.txt
@@ -197,9 +197,11 @@ of the following host1x client modules:
- sor: serial output resource
Required properties:
- - compatible: For Tegra124, must contain "nvidia,tegra124-sor". Otherwise,
- must contain '"nvidia,<chip>-sor", "nvidia,tegra124-sor"', where <chip>
- is tegra132.
+ - compatible: Should be:
+ - "nvidia,tegra124-sor": for Tegra124 and Tegra132
+ - "nvidia,tegra132-sor": for Tegra132
+ - "nvidia,tegra210-sor": for Tegra210
+ - "nvidia,tegra210-sor1": for Tegra210
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt outputs from the controller.
- clocks: Must contain an entry for each entry in clock-names.
diff --git a/dts/Bindings/gpu/st,stih4xx.txt b/dts/Bindings/gpu/st,stih4xx.txt
index 6b1d75f..a36dfce 100644
--- a/dts/Bindings/gpu/st,stih4xx.txt
+++ b/dts/Bindings/gpu/st,stih4xx.txt
@@ -52,10 +52,9 @@ STMicroelectronics stih4xx platforms
See ../reset/reset.txt for details.
- reset-names: names of the resets listed in resets property in the same
order.
- - ranges: to allow probing of subdevices
- sti-hdmi: hdmi output block
- must be a child of sti-tvout
+ must be a child of sti-display-subsystem
Required properties:
- compatible: "st,stih<chip>-hdmi";
- reg: Physical base address of the IP registers and length of memory mapped region.
@@ -72,7 +71,7 @@ STMicroelectronics stih4xx platforms
sti-hda:
Required properties:
- must be a child of sti-tvout
+ must be a child of sti-display-subsystem
- compatible: "st,stih<chip>-hda"
- reg: Physical base address of the IP registers and length of memory mapped region.
- reg-names: names of the mapped memory regions listed in regs property in
@@ -85,7 +84,7 @@ sti-hda:
sti-dvo:
Required properties:
- must be a child of sti-tvout
+ must be a child of sti-display-subsystem
- compatible: "st,stih<chip>-dvo"
- reg: Physical base address of the IP registers and length of memory mapped region.
- reg-names: names of the mapped memory regions listed in regs property in
@@ -195,38 +194,37 @@ Example:
reg-names = "tvout-reg", "hda-reg", "syscfg";
reset-names = "tvout";
resets = <&softreset STIH416_HDTVOUT_SOFTRESET>;
- ranges;
-
- sti-hdmi@fe85c000 {
- compatible = "st,stih416-hdmi";
- reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
- reg-names = "hdmi-reg", "syscfg";
- interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
- interrupt-names = "irq";
- clock-names = "pix", "tmds", "phy", "audio";
- clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
- };
-
- sti-hda@fe85a000 {
- compatible = "st,stih416-hda";
- reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
- reg-names = "hda-reg", "video-dacs-ctrl";
- clock-names = "pix", "hddac";
- clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
- };
-
- sti-dvo@8d00400 {
- compatible = "st,stih407-dvo";
- reg = <0x8d00400 0x200>;
- reg-names = "dvo-reg";
- clock-names = "dvo_pix", "dvo",
- "main_parent", "aux_parent";
- clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
- <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_dvo>;
- sti,panel = <&panel_dvo>;
- };
+ };
+
+ sti-hdmi@fe85c000 {
+ compatible = "st,stih416-hdmi";
+ reg = <0xfe85c000 0x1000>, <0xfe830000 0x10000>;
+ reg-names = "hdmi-reg", "syscfg";
+ interrupts = <GIC_SPI 173 IRQ_TYPE_NONE>;
+ interrupt-names = "irq";
+ clock-names = "pix", "tmds", "phy", "audio";
+ clocks = <&clockgen_c_vcc CLK_S_PIX_HDMI>, <&clockgen_c_vcc CLK_S_TMDS_HDMI>, <&clockgen_c_vcc CLK_S_HDMI_REJECT_PLL>, <&clockgen_b1 CLK_S_PCM_0>;
+ };
+
+ sti-hda@fe85a000 {
+ compatible = "st,stih416-hda";
+ reg = <0xfe85a000 0x400>, <0xfe83085c 0x4>;
+ reg-names = "hda-reg", "video-dacs-ctrl";
+ clock-names = "pix", "hddac";
+ clocks = <&clockgen_c_vcc CLK_S_PIX_HD>, <&clockgen_c_vcc CLK_S_HDDAC>;
+ };
+
+ sti-dvo@8d00400 {
+ compatible = "st,stih407-dvo";
+ reg = <0x8d00400 0x200>;
+ reg-names = "dvo-reg";
+ clock-names = "dvo_pix", "dvo",
+ "main_parent", "aux_parent";
+ clocks = <&clk_s_d2_flexgen CLK_PIX_DVO>, <&clk_s_d2_flexgen CLK_DVO>,
+ <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dvo>;
+ sti,panel = <&panel_dvo>;
};
sti-hqvdp@9c000000 {
@@ -237,7 +235,7 @@ Example:
reset-names = "hqvdp";
resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
st,vtg = <&vtg_main>;
- };
+ };
};
...
};
diff --git a/dts/Bindings/i2c/ina209.txt b/dts/Bindings/hwmon/ina209.txt
index 9dd2bee..9dd2bee 100644
--- a/dts/Bindings/i2c/ina209.txt
+++ b/dts/Bindings/hwmon/ina209.txt
diff --git a/dts/Bindings/i2c/ina2xx.txt b/dts/Bindings/hwmon/ina2xx.txt
index a2ad85d..a2ad85d 100644
--- a/dts/Bindings/i2c/ina2xx.txt
+++ b/dts/Bindings/hwmon/ina2xx.txt
diff --git a/dts/Bindings/hwmon/lm70.txt b/dts/Bindings/hwmon/lm70.txt
new file mode 100644
index 0000000..e7fd921
--- /dev/null
+++ b/dts/Bindings/hwmon/lm70.txt
@@ -0,0 +1,21 @@
+* LM70/TMP121/LM71/LM74 thermometer.
+
+Required properties:
+- compatible: one of
+ "ti,lm70"
+ "ti,tmp121"
+ "ti,lm71"
+ "ti,lm74"
+
+See Documentation/devicetree/bindings/spi/spi-bus.txt for more required and
+optional properties.
+
+Example:
+
+spi_master {
+ temperature-sensor@0 {
+ compatible = "ti,lm70";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
diff --git a/dts/Bindings/hwmon/ltc2978.txt b/dts/Bindings/hwmon/ltc2978.txt
index ed2f09d..a7afbf6 100644
--- a/dts/Bindings/hwmon/ltc2978.txt
+++ b/dts/Bindings/hwmon/ltc2978.txt
@@ -3,10 +3,16 @@ ltc2978
Required properties:
- compatible: should contain one of:
* "lltc,ltc2974"
+ * "lltc,ltc2975"
* "lltc,ltc2977"
* "lltc,ltc2978"
+ * "lltc,ltc2980"
* "lltc,ltc3880"
+ * "lltc,ltc3882"
* "lltc,ltc3883"
+ * "lltc,ltc3886"
+ * "lltc,ltc3887"
+ * "lltc,ltm2987"
* "lltc,ltm4676"
- reg: I2C slave address
@@ -17,10 +23,10 @@ Optional properties:
standard binding for regulators; see regulator.txt.
Valid names of regulators depend on number of supplies supported per device:
- * ltc2974 : vout0 - vout3
- * ltc2977 : vout0 - vout7
+ * ltc2974, ltc2975 : vout0 - vout3
+ * ltc2977, ltc2980, ltm2987 : vout0 - vout7
* ltc2978 : vout0 - vout7
- * ltc3880 : vout0 - vout1
+ * ltc3880, ltc3882, ltc3886 : vout0 - vout1
* ltc3883 : vout0
* ltm4676 : vout0 - vout1
diff --git a/dts/Bindings/i2c/max6697.txt b/dts/Bindings/hwmon/max6697.txt
index 5f79399..5f79399 100644
--- a/dts/Bindings/i2c/max6697.txt
+++ b/dts/Bindings/hwmon/max6697.txt
diff --git a/dts/Bindings/i2c/i2c-cadence.txt b/dts/Bindings/i2c/i2c-cadence.txt
index 7cb0b56..ebaa90c 100644
--- a/dts/Bindings/i2c/i2c-cadence.txt
+++ b/dts/Bindings/i2c/i2c-cadence.txt
@@ -2,7 +2,11 @@ Binding for the Cadence I2C controller
Required properties:
- reg: Physical base address and size of the controller's register area.
- - compatible: Compatibility string. Must be 'cdns,i2c-r1p10'.
+ - compatible: Should contain one of:
+ * "cdns,i2c-r1p10"
+ Note: Use this when cadence i2c controller version 1.0 is used.
+ * "cdns,i2c-r1p14"
+ Note: Use this when cadence i2c controller version 1.4 is used.
- clocks: Input clock specifier. Refer to common clock bindings.
- interrupts: Interrupt specifier. Refer to interrupt bindings.
- #address-cells: Should be 1.
diff --git a/dts/Bindings/i2c/i2c-emev2.txt b/dts/Bindings/i2c/i2c-emev2.txt
new file mode 100644
index 0000000..5ed1ea1
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-emev2.txt
@@ -0,0 +1,22 @@
+Device tree configuration for Renesas EMEV2 IIC controller
+
+Required properties:
+- compatible : "renesas,iic-emev2"
+- reg : address start and address range size of device
+- interrupts : specifier for the IIC controller interrupt
+- clocks : phandle to the IP core SCLK
+- clock-names : must be "sclk"
+- #address-cells : should be <1>
+- #size-cells : should be <0>
+
+Example:
+
+ iic0: i2c@e0070000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,iic-emev2";
+ reg = <0xe0070000 0x28>;
+ interrupts = <0 32 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&iic0_sclk>;
+ clock-names = "sclk";
+ };
diff --git a/dts/Bindings/i2c/i2c-lpc2k.txt b/dts/Bindings/i2c/i2c-lpc2k.txt
new file mode 100644
index 0000000..4101aa6
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-lpc2k.txt
@@ -0,0 +1,33 @@
+NXP I2C controller for LPC2xxx/178x/18xx/43xx
+
+Required properties:
+ - compatible: must be "nxp,lpc1788-i2c"
+ - reg: physical address and length of the device registers
+ - interrupts: a single interrupt specifier
+ - clocks: clock for the device
+ - #address-cells: should be <1>
+ - #size-cells: should be <0>
+
+Optional properties:
+- clock-frequency: the desired I2C bus clock frequency in Hz; in
+ absence of this property the default value is used (100 kHz).
+
+Example:
+i2c0: i2c@400a1000 {
+ compatible = "nxp,lpc1788-i2c";
+ reg = <0x400a1000 0x1000>;
+ interrupts = <18>;
+ clocks = <&ccu1 CLK_APB1_I2C0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&i2c0 {
+ clock-frequency = <400000>;
+
+ lm75@48 {
+ compatible = "nxp,lm75";
+ reg = <0x48>;
+ };
+};
+
diff --git a/dts/Bindings/i2c/i2c-mux-reg.txt b/dts/Bindings/i2c/i2c-mux-reg.txt
new file mode 100644
index 0000000..688783f
--- /dev/null
+++ b/dts/Bindings/i2c/i2c-mux-reg.txt
@@ -0,0 +1,74 @@
+Register-based I2C Bus Mux
+
+This binding describes an I2C bus multiplexer that uses a single register
+to route the I2C signals.
+
+Required properties:
+- compatible: i2c-mux-reg
+- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
+ port is connected to.
+* Standard I2C mux properties. See mux.txt in this directory.
+* I2C child bus nodes. See mux.txt in this directory.
+
+Optional properties:
+- reg: this pair of <offset size> specifies the register to control the mux.
+ The <offset size> depends on its parent node. It can be any memory-mapped
+ address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the
+ resource of this device will be used.
+- little-endian: The existence indicates the register is in little endian.
+- big-endian: The existence indicates the register is in big endian.
+ If both little-endian and big-endian are omitted, the endianness of the
+ CPU will be used.
+- write-only: The existence indicates the register is write-only.
+- idle-state: value to set the muxer to when idle. When no value is
+ given, it defaults to the last value used.
+
+Whenever an access is made to a device on a child bus, the value set
+in the revelant node's reg property will be output to the register.
+
+If an idle state is defined, using the idle-state (optional) property,
+whenever an access is not being made to a device on a child bus, the
+register will be set according to the idle value.
+
+If an idle state is not defined, the most recently used value will be
+left programmed into the register.
+
+Example of a mux on PCIe card, the host is a powerpc SoC (big endian):
+
+ i2c-mux {
+ /* the <offset size> depends on the address translation
+ * of the parent device. If omitted, device resource
+ * will be used instead. The size is to determine
+ * whether iowrite32, iowrite16, or iowrite8 will be used.
+ */
+ reg = <0x6028 0x4>;
+ little-endian; /* little endian register on PCIe */
+ compatible = "i2c-mux-reg";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c1>;
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ si5338: clock-generator@70 {
+ compatible = "silabs,si5338";
+ reg = <0x70>;
+ /* other stuff */
+ };
+ };
+
+ i2c@1 {
+ /* data is written using iowrite32 */
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ si5338: clock-generator@70 {
+ compatible = "silabs,si5338";
+ reg = <0x70>;
+ /* other stuff */
+ };
+ };
+ };
diff --git a/dts/Bindings/i2c/i2c.txt b/dts/Bindings/i2c/i2c.txt
new file mode 100644
index 0000000..8a99150
--- /dev/null
+++ b/dts/Bindings/i2c/i2c.txt
@@ -0,0 +1,45 @@
+Generic device tree bindings for I2C busses
+===========================================
+
+This document describes generic bindings which can be used to describe I2C
+busses in a device tree.
+
+Required properties
+-------------------
+
+- #address-cells - should be <1>. Read more about addresses below.
+- #size-cells - should be <0>.
+- compatible - name of I2C bus controller following generic names
+ recommended practice.
+
+For other required properties e.g. to describe register sets,
+clocks, etc. check the binding documentation of the specific driver.
+
+The cells properties above define that an address of children of an I2C bus
+are described by a single value. This is usually a 7 bit address. However,
+flags can be attached to the address. I2C_TEN_BIT_ADDRESS is used to mark a 10
+bit address. It is needed to avoid the ambiguity between e.g. a 7 bit address
+of 0x50 and a 10 bit address of 0x050 which, in theory, can be on the same bus.
+Another flag is I2C_OWN_SLAVE_ADDRESS to mark addresses on which we listen to
+be devices ourselves.
+
+Optional properties
+-------------------
+
+These properties may not be supported by all drivers. However, if a driver
+wants to support one of the below features, it should adapt the bindings below.
+
+- clock-frequency - frequency of bus clock in Hz.
+- wakeup-source - device can be used as a wakeup source.
+
+- interrupts - interrupts used by the device.
+- interrupt-names - "irq" and "wakeup" names are recognized by I2C core,
+ other names are left to individual drivers.
+
+Binding may contain optional "interrupts" property, describing interrupts
+used by the device. I2C core will assign "irq" interrupt (or the very first
+interrupt if not using interrupt names) as primary interrupt for the slave.
+
+Also, if device is marked as a wakeup source, I2C core will set up "wakeup"
+interrupt for the device. If "wakeup" interrupt name is not present in the
+binding, then primary interrupt will be used as wakeup interrupt.
diff --git a/dts/Bindings/i2c/trivial-devices.txt b/dts/Bindings/i2c/trivial-devices.txt
index 00f8652..d77d412 100644
--- a/dts/Bindings/i2c/trivial-devices.txt
+++ b/dts/Bindings/i2c/trivial-devices.txt
@@ -95,6 +95,8 @@ stm,m41t00 Serial Access TIMEKEEPER
stm,m41t62 Serial real-time clock (RTC) with alarm
stm,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
taos,tsl2550 Ambient Light Sensor with SMBUS/Two Wire Serial Interface
+ti,ads7828 8-Channels, 12-bit ADC
+ti,ads7830 8-Channels, 8-bit ADC
ti,tsc2003 I2C Touch-Screen Controller
ti,tmp102 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
ti,tmp103 Low Power Digital Temperature Sensor with SMBUS/Two Wire Serial Interface
diff --git a/dts/Bindings/iio/adc/mcp320x.txt b/dts/Bindings/iio/adc/mcp320x.txt
index b851843..2a1f3af 100644
--- a/dts/Bindings/iio/adc/mcp320x.txt
+++ b/dts/Bindings/iio/adc/mcp320x.txt
@@ -18,6 +18,7 @@ Required properties:
"mcp3202"
"mcp3204"
"mcp3208"
+ "mcp3301"
Examples:
diff --git a/dts/Bindings/iio/adc/vf610-adc.txt b/dts/Bindings/iio/adc/vf610-adc.txt
index 3eb40e2..1aad051 100644
--- a/dts/Bindings/iio/adc/vf610-adc.txt
+++ b/dts/Bindings/iio/adc/vf610-adc.txt
@@ -17,6 +17,11 @@ Recommended properties:
- Frequency in normal mode (ADLPC=0, ADHSC=0)
- Frequency in high-speed mode (ADLPC=0, ADHSC=1)
- Frequency in low-power mode (ADLPC=1, ADHSC=0)
+- min-sample-time: Minimum sampling time in nanoseconds. This value has
+ to be chosen according to the conversion mode and the connected analog
+ source resistance (R_as) and capacitance (C_as). Refer the datasheet's
+ operating requirements. A safe default across a wide range of R_as and
+ C_as as well as conversion modes is 1000ns.
Example:
adc0: adc@4003b000 {
diff --git a/dts/Bindings/iio/magnetometer/mmc35240.txt b/dts/Bindings/iio/magnetometer/mmc35240.txt
new file mode 100644
index 0000000..a01235c
--- /dev/null
+++ b/dts/Bindings/iio/magnetometer/mmc35240.txt
@@ -0,0 +1,13 @@
+* MEMSIC MMC35240 magnetometer sensor
+
+Required properties:
+
+ - compatible : should be "memsic,mmc35240"
+ - reg : the I2C address of the magnetometer
+
+Example:
+
+mmc35240@30 {
+ compatible = "memsic,mmc35240";
+ reg = <0x30>;
+};
diff --git a/dts/Bindings/iio/st-sensors.txt b/dts/Bindings/iio/st-sensors.txt
index 8a6be3b..d3ccdb1 100644
--- a/dts/Bindings/iio/st-sensors.txt
+++ b/dts/Bindings/iio/st-sensors.txt
@@ -35,6 +35,7 @@ Accelerometers:
- st,lsm303dl-accel
- st,lsm303dlm-accel
- st,lsm330-accel
+- st,lsm303agr-accel
Gyroscopes:
- st,l3g4200d-gyro
@@ -46,6 +47,7 @@ Gyroscopes:
- st,lsm330-gyro
Magnetometers:
+- st,lsm303agr-magn
- st,lsm303dlh-magn
- st,lsm303dlhc-magn
- st,lsm303dlm-magn
diff --git a/dts/Bindings/input/ads7846.txt b/dts/Bindings/input/ads7846.txt
index 5f7619c..df8b127 100644
--- a/dts/Bindings/input/ads7846.txt
+++ b/dts/Bindings/input/ads7846.txt
@@ -64,7 +64,7 @@ Optional properties:
pendown-gpio (u32).
pendown-gpio GPIO handle describing the pin the !PENIRQ
line is connected to.
- linux,wakeup use any event on touchscreen as wakeup event.
+ wakeup-source use any event on touchscreen as wakeup event.
Example for a TSC2046 chip connected to an McSPI controller of an OMAP SoC::
diff --git a/dts/Bindings/input/cap11xx.txt b/dts/Bindings/input/cap11xx.txt
index 7d0a300..8c67a0b 100644
--- a/dts/Bindings/input/cap11xx.txt
+++ b/dts/Bindings/input/cap11xx.txt
@@ -55,5 +55,24 @@ i2c_controller {
<105>, /* KEY_LEFT */
<109>, /* KEY_PAGEDOWN */
<104>; /* KEY_PAGEUP */
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usr@0 {
+ label = "cap11xx:green:usr0";
+ reg = <0>;
+ };
+
+ usr@1 {
+ label = "cap11xx:green:usr1";
+ reg = <1>;
+ };
+
+ alive@2 {
+ label = "cap11xx:green:alive";
+ reg = <2>;
+ linux,default_trigger = "heartbeat";
+ };
};
}
diff --git a/dts/Bindings/input/cypress,cyapa.txt b/dts/Bindings/input/cypress,cyapa.txt
new file mode 100644
index 0000000..635a3b0
--- /dev/null
+++ b/dts/Bindings/input/cypress,cyapa.txt
@@ -0,0 +1,44 @@
+Cypress I2C Touchpad
+
+Required properties:
+- compatible: must be "cypress,cyapa".
+- reg: I2C address of the chip.
+- interrupt-parent: a phandle for the interrupt controller (see interrupt
+ binding[0]).
+- interrupts: interrupt to which the chip is connected (see interrupt
+ binding[0]).
+
+Optional properties:
+- wakeup-source: touchpad can be used as a wakeup source.
+- pinctrl-names: should be "default" (see pinctrl binding [1]).
+- pinctrl-0: a phandle pointing to the pin settings for the device (see
+ pinctrl binding [1]).
+- vcc-supply: a phandle for the regulator supplying 3.3V power.
+
+[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+Example:
+ &i2c0 {
+ /* ... */
+
+ /* Cypress Gen3 touchpad */
+ touchpad@67 {
+ compatible = "cypress,cyapa";
+ reg = <0x24>;
+ interrupt-parent = <&gpio>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO 2 */
+ wakeup-source;
+ };
+
+ /* Cypress Gen5 and later touchpad */
+ touchpad@24 {
+ compatible = "cypress,cyapa";
+ reg = <0x24>;
+ interrupt-parent = <&gpio>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>; /* GPIO 2 */
+ wakeup-source;
+ };
+
+ /* ... */
+ };
diff --git a/dts/Bindings/input/elants_i2c.txt b/dts/Bindings/input/elants_i2c.txt
index a765232..8a71038 100644
--- a/dts/Bindings/input/elants_i2c.txt
+++ b/dts/Bindings/input/elants_i2c.txt
@@ -13,6 +13,9 @@ Optional properties:
- pinctrl-names: should be "default" (see pinctrl binding [1]).
- pinctrl-0: a phandle pointing to the pin settings for the device (see
pinctrl binding [1]).
+- reset-gpios: reset gpio the chip is connected to.
+- vcc33-supply: a phandle for the regulator supplying 3.3V power.
+- vccio-supply: a phandle for the regulator supplying IO power.
[0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
[1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
diff --git a/dts/Bindings/input/gpio-keys-polled.txt b/dts/Bindings/input/gpio-keys-polled.txt
index 313abef..5b91f5a 100644
--- a/dts/Bindings/input/gpio-keys-polled.txt
+++ b/dts/Bindings/input/gpio-keys-polled.txt
@@ -20,7 +20,7 @@ Optional subnode-properties:
If not specified defaults to <1> == EV_KEY.
- debounce-interval: Debouncing interval time in milliseconds.
If not specified defaults to 5.
- - gpio-key,wakeup: Boolean, button can wake-up the system.
+ - wakeup-source: Boolean, button can wake-up the system.
Example nodes:
diff --git a/dts/Bindings/input/gpio-keys.txt b/dts/Bindings/input/gpio-keys.txt
index 44b7057..072bf75 100644
--- a/dts/Bindings/input/gpio-keys.txt
+++ b/dts/Bindings/input/gpio-keys.txt
@@ -23,7 +23,7 @@ Optional subnode-properties:
If not specified defaults to <1> == EV_KEY.
- debounce-interval: Debouncing interval time in milliseconds.
If not specified defaults to 5.
- - gpio-key,wakeup: Boolean, button can wake-up the system.
+ - wakeup-source: Boolean, button can wake-up the system.
- linux,can-disable: Boolean, indicates that button is connected
to dedicated (not shared) interrupt which can be disabled to
suppress events from the button.
diff --git a/dts/Bindings/input/gpio-matrix-keypad.txt b/dts/Bindings/input/gpio-matrix-keypad.txt
index ead641c..4d86059 100644
--- a/dts/Bindings/input/gpio-matrix-keypad.txt
+++ b/dts/Bindings/input/gpio-matrix-keypad.txt
@@ -19,7 +19,7 @@ Required Properties:
Optional Properties:
- linux,no-autorepeat: do no enable autorepeat feature.
-- linux,wakeup: use any event on keypad as wakeup event.
+- wakeup-source: use any event on keypad as wakeup event.
- debounce-delay-ms: debounce interval in milliseconds
- col-scan-delay-us: delay, measured in microseconds, that is needed
before we can scan keypad after activating column gpio
diff --git a/dts/Bindings/input/qcom,pm8xxx-keypad.txt b/dts/Bindings/input/qcom,pm8xxx-keypad.txt
index 7d8cb92..ee62156 100644
--- a/dts/Bindings/input/qcom,pm8xxx-keypad.txt
+++ b/dts/Bindings/input/qcom,pm8xxx-keypad.txt
@@ -33,7 +33,7 @@ PROPERTIES
Value type: <bool>
Definition: don't enable autorepeat feature.
-- linux,keypad-wakeup:
+- wakeup-source:
Usage: optional
Value type: <bool>
Definition: use any event on keypad as wakeup event.
diff --git a/dts/Bindings/input/samsung-keypad.txt b/dts/Bindings/input/samsung-keypad.txt
index 942d071..863e77f 100644
--- a/dts/Bindings/input/samsung-keypad.txt
+++ b/dts/Bindings/input/samsung-keypad.txt
@@ -36,9 +36,11 @@ Required Board Specific Properties:
- pinctrl-0: Should specify pin control groups used for this controller.
- pinctrl-names: Should contain only one value - "default".
+Optional Properties:
+- wakeup-source: use any event on keypad as wakeup event.
+
Optional Properties specific to linux:
- linux,keypad-no-autorepeat: do no enable autorepeat feature.
-- linux,keypad-wakeup: use any event on keypad as wakeup event.
Example:
diff --git a/dts/Bindings/input/snvs-pwrkey.txt b/dts/Bindings/input/snvs-pwrkey.txt
new file mode 100644
index 0000000..70c1425
--- /dev/null
+++ b/dts/Bindings/input/snvs-pwrkey.txt
@@ -0,0 +1 @@
+See Documentation/devicetree/bindings/crypto/fsl-sec4.txt
diff --git a/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
new file mode 100644
index 0000000..9d9e930
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/colibri-vf50-ts.txt
@@ -0,0 +1,36 @@
+* Toradex Colibri VF50 Touchscreen driver
+
+Required Properties:
+- compatible must be toradex,vf50-touchscreen
+- io-channels: adc channels being used by the Colibri VF50 module
+- xp-gpios: FET gate driver for input of X+
+- xm-gpios: FET gate driver for input of X-
+- yp-gpios: FET gate driver for input of Y+
+- ym-gpios: FET gate driver for input of Y-
+- interrupt-parent: phandle for the interrupt controller
+- interrupts: pen irq interrupt for touch detection
+- pinctrl-names: "idle", "default", "gpios"
+- pinctrl-0: pinctrl node for pen/touch detection state pinmux
+- pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux
+- pinctrl-2: pinctrl node for gpios functioning as FET gate drivers
+- vf50-ts-min-pressure: pressure level at which to stop measuring X/Y values
+
+Example:
+
+ touchctrl: vf50_touchctrl {
+ compatible = "toradex,vf50-touchscreen";
+ io-channels = <&adc1 0>,<&adc0 0>,
+ <&adc0 1>,<&adc1 2>;
+ xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+ xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+ yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+ ym-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "idle","default","gpios";
+ pinctrl-0 = <&pinctrl_touchctrl_idle>;
+ pinctrl-1 = <&pinctrl_touchctrl_default>;
+ pinctrl-2 = <&pinctrl_touchctrl_gpios>;
+ vf50-ts-min-pressure = <200>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/input/touchscreen/imx6ul_tsc.txt b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
new file mode 100644
index 0000000..853dff9
--- /dev/null
+++ b/dts/Bindings/input/touchscreen/imx6ul_tsc.txt
@@ -0,0 +1,36 @@
+* Freescale i.MX6UL Touch Controller
+
+Required properties:
+- compatible: must be "fsl,imx6ul-tsc".
+- reg: this touch controller address and the ADC2 address.
+- interrupts: the interrupt of this touch controller and ADC2.
+- clocks: the root clock of touch controller and ADC2.
+- clock-names; must be "tsc" and "adc".
+- xnur-gpio: the X- gpio this controller connect to.
+ This xnur-gpio returns to low once the finger leave the touch screen (The
+ last touch event the touch controller capture).
+
+Optional properties:
+- measure-delay-time: the value of measure delay time.
+ Before X-axis or Y-axis measurement, the screen need some time before
+ even potential distribution ready.
+ This value depends on the touch screen.
+- pre-charge-time: the touch screen need some time to precharge.
+ This value depends on the touch screen.
+
+Example:
+ tsc: tsc@02040000 {
+ compatible = "fsl,imx6ul-tsc";
+ reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX6UL_CLK_IPG>,
+ <&clks IMX6UL_CLK_ADC2>;
+ clock-names = "tsc", "adc";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xfff>;
+ pre-charge-time = <0xffff>;
+ status = "okay";
+ };
diff --git a/dts/Bindings/input/touchscreen/pixcir_i2c_ts.txt b/dts/Bindings/input/touchscreen/pixcir_i2c_ts.txt
index 6e55109..8eb240a 100644
--- a/dts/Bindings/input/touchscreen/pixcir_i2c_ts.txt
+++ b/dts/Bindings/input/touchscreen/pixcir_i2c_ts.txt
@@ -8,6 +8,9 @@ Required properties:
- touchscreen-size-x: horizontal resolution of touchscreen (in pixels)
- touchscreen-size-y: vertical resolution of touchscreen (in pixels)
+Optional properties:
+- reset-gpio: GPIO connected to the RESET line of the chip
+
Example:
i2c@00000000 {
diff --git a/dts/Bindings/input/touchscreen/zforce_ts.txt b/dts/Bindings/input/touchscreen/zforce_ts.txt
index 80c37df..e3c27c4 100644
--- a/dts/Bindings/input/touchscreen/zforce_ts.txt
+++ b/dts/Bindings/input/touchscreen/zforce_ts.txt
@@ -4,12 +4,12 @@ Required properties:
- compatible: must be "neonode,zforce"
- reg: I2C address of the chip
- interrupts: interrupt to which the chip is connected
-- gpios: gpios the chip is connected to
- first one is the interrupt gpio and second one the reset gpio
+- reset-gpios: reset gpio the chip is connected to
- x-size: horizontal resolution of touchscreen
- y-size: vertical resolution of touchscreen
Optional properties:
+- irq-gpios : interrupt gpio the chip is connected to
- vdd-supply: Regulator controlling the controller supply
Example:
@@ -23,8 +23,8 @@ Example:
interrupts = <2 0>;
vdd-supply = <&reg_zforce_vdd>;
- gpios = <&gpio5 6 0>, /* INT */
- <&gpio5 9 0>; /* RST */
+ reset-gpios = <&gpio5 9 0>; /* RST */
+ irq-gpios = <&gpio5 6 0>; /* IRQ, optional */
x-size = <800>;
y-size = <600>;
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt b/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
index 7da578d..2d6c8bb 100644
--- a/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
+++ b/dts/Bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt
@@ -5,9 +5,14 @@ The BCM2835 contains a custom top-level interrupt controller, which supports
controller, or the HW block containing it, is referred to occasionally
as "armctrl" in the SoC documentation, hence naming of this binding.
+The BCM2836 contains the same interrupt controller with the same
+interrupts, but the per-CPU interrupt controller is the root, and an
+interrupt there indicates that the ARMCTRL has an interrupt to handle.
+
Required properties:
-- compatible : should be "brcm,bcm2835-armctrl-ic"
+- compatible : should be "brcm,bcm2835-armctrl-ic" or
+ "brcm,bcm2836-armctrl-ic"
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
@@ -20,6 +25,12 @@ Required properties:
The 2nd cell contains the interrupt number within the bank. Valid values
are 0..7 for bank 0, and 0..31 for bank 1.
+Additional required properties for brcm,bcm2836-armctrl-ic:
+- interrupt-parent : Specifies the parent interrupt controller when this
+ controller is the second level.
+- interrupts : Specifies the interrupt on the parent for this interrupt
+ controller to handle.
+
The interrupt sources are as follows:
Bank 0:
@@ -102,9 +113,21 @@ Bank 2:
Example:
+/* BCM2835, first level */
intc: interrupt-controller {
compatible = "brcm,bcm2835-armctrl-ic";
reg = <0x7e00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
+
+/* BCM2836, second level */
+intc: interrupt-controller {
+ compatible = "brcm,bcm2836-armctrl-ic";
+ reg = <0x7e00b200 0x200>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&local_intc>;
+ interrupts = <8>;
+};
diff --git a/dts/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt b/dts/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
new file mode 100644
index 0000000..f320dcd
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/brcm,bcm2836-l1-intc.txt
@@ -0,0 +1,37 @@
+BCM2836 per-CPU interrupt controller
+
+The BCM2836 has a per-cpu interrupt controller for the timer, PMU
+events, and SMP IPIs. One of the CPUs may receive interrupts for the
+peripheral (GPU) events, which chain to the BCM2835-style interrupt
+controller.
+
+Required properties:
+
+- compatible: Should be "brcm,bcm2836-l1-intc"
+- reg: Specifies base physical address and size of the
+ registers
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 1
+
+Please refer to interrupts.txt in this directory for details of the common
+Interrupt Controllers bindings used by client devices.
+
+The interrupt sources are as follows:
+
+0: CNTPSIRQ
+1: CNTPNSIRQ
+2: CNTHPIRQ
+3: CNTVIRQ
+8: GPU_FAST
+9: PMU_FAST
+
+Example:
+
+local_intc: local_intc {
+ compatible = "brcm,bcm2836-l1-intc";
+ reg = <0x40000000 0x100>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&local_intc>;
+};
diff --git a/dts/Bindings/interrupt-controller/msi.txt b/dts/Bindings/interrupt-controller/msi.txt
new file mode 100644
index 0000000..c60c034
--- /dev/null
+++ b/dts/Bindings/interrupt-controller/msi.txt
@@ -0,0 +1,135 @@
+This document describes the generic device tree binding for MSI controllers and
+their master(s).
+
+Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
+write to an MMIO address.
+
+MSIs were originally specified by PCI (and are used with PCIe), but may also be
+used with other busses, and hence a mechanism is required to relate devices on
+those busses to the MSI controllers which they are capable of using,
+potentially including additional information.
+
+MSIs are distinguished by some combination of:
+
+- The doorbell (the MMIO address written to).
+
+ Devices may be configured by software to write to arbitrary doorbells which
+ they can address. An MSI controller may feature a number of doorbells.
+
+- The payload (the value written to the doorbell).
+
+ Devices may be configured to write an arbitrary payload chosen by software.
+ MSI controllers may have restrictions on permitted payloads.
+
+- Sideband information accompanying the write.
+
+ Typically this is neither configurable nor probeable, and depends on the path
+ taken through the memory system (i.e. it is a property of the combination of
+ MSI controller and device rather than a property of either in isolation).
+
+
+MSI controllers:
+================
+
+An MSI controller signals interrupts to a CPU when a write is made to an MMIO
+address by some master. An MSI controller may feature a number of doorbells.
+
+Required properties:
+--------------------
+
+- msi-controller: Identifies the node as an MSI controller.
+
+Optional properties:
+--------------------
+
+- #msi-cells: The number of cells in an msi-specifier, required if not zero.
+
+ Typically this will encode information related to sideband data, and will
+ not encode doorbells or payloads as these can be configured dynamically.
+
+ The meaning of the msi-specifier is defined by the device tree binding of
+ the specific MSI controller.
+
+
+MSI clients
+===========
+
+MSI clients are devices which generate MSIs. For each MSI they wish to
+generate, the doorbell and payload may be configured, though sideband
+information may not be configurable.
+
+Required properties:
+--------------------
+
+- msi-parent: A list of phandle + msi-specifier pairs, one for each MSI
+ controller which the device is capable of using.
+
+ This property is unordered, and MSIs may be allocated from any combination of
+ MSI controllers listed in the msi-parent property.
+
+ If a device has restrictions on the allocation of MSIs, these restrictions
+ must be described with additional properties.
+
+ When #msi-cells is non-zero, busses with an msi-parent will require
+ additional properties to describe the relationship between devices on the bus
+ and the set of MSIs they can potentially generate.
+
+
+Example
+=======
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ msi_a: msi-controller@a {
+ reg = <0xa 0xf00>;
+ compatible = "vendor-a,some-controller";
+ msi-controller;
+ /* No sideband data, so #msi-cells omitted */
+ };
+
+ msi_b: msi-controller@b {
+ reg = <0xb 0xf00>;
+ compatible = "vendor-b,another-controller";
+ msi-controller;
+ /* Each device has some unique ID */
+ #msi-cells = <1>;
+ };
+
+ msi_c: msi-controller@c {
+ reg = <0xb 0xf00>;
+ compatible = "vendor-b,another-controller";
+ msi-controller;
+ /* Each device has some unique ID */
+ #msi-cells = <1>;
+ };
+
+ dev@0 {
+ reg = <0x0 0xf00>;
+ compatible = "vendor-c,some-device";
+
+ /* Can only generate MSIs to msi_a */
+ msi-parent = <&msi_a>;
+ };
+
+ dev@1 {
+ reg = <0x1 0xf00>;
+ compatible = "vendor-c,some-device";
+
+ /*
+ * Can generate MSIs to either A or B.
+ */
+ msi-parent = <&msi_a>, <&msi_b 0x17>;
+ };
+
+ dev@2 {
+ reg = <0x2 0xf00>;
+ compatible = "vendor-c,some-device";
+ /*
+ * Has different IDs at each MSI controller.
+ * Can generate MSIs to all of the MSI controllers.
+ */
+ msi-parent = <&msi_a>, <&msi_b 0x17>, <&msi_c 0x53>;
+ };
+};
diff --git a/dts/Bindings/iommu/arm,smmu.txt b/dts/Bindings/iommu/arm,smmu.txt
index 0676050..7180745 100644
--- a/dts/Bindings/iommu/arm,smmu.txt
+++ b/dts/Bindings/iommu/arm,smmu.txt
@@ -43,6 +43,12 @@ conditions.
** System MMU optional properties:
+- dma-coherent : Present if page table walks made by the SMMU are
+ cache coherent with the CPU.
+
+ NOTE: this only applies to the SMMU itself, not
+ masters connected upstream of the SMMU.
+
- calxeda,smmu-secure-config-access : Enable proper handling of buggy
implementations that always use secure access to
SMMU configuration registers. In this case non-secure
diff --git a/dts/Bindings/iommu/ti,omap-iommu.txt b/dts/Bindings/iommu/ti,omap-iommu.txt
index 42531dc..8696999 100644
--- a/dts/Bindings/iommu/ti,omap-iommu.txt
+++ b/dts/Bindings/iommu/ti,omap-iommu.txt
@@ -8,6 +8,11 @@ Required properties:
- ti,hwmods : Name of the hwmod associated with the IOMMU instance
- reg : Address space for the configuration registers
- interrupts : Interrupt specifier for the IOMMU instance
+- #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
+ and needs no additional data in the pargs specifier. Please
+ also refer to the generic bindings document for more info
+ on this property,
+ Documentation/devicetree/bindings/iommu/iommu.txt
Optional properties:
- ti,#tlb-entries : Number of entries in the translation look-aside buffer.
@@ -18,6 +23,7 @@ Optional properties:
Example:
/* OMAP3 ISP MMU */
mmu_isp: mmu@480bd400 {
+ #iommu-cells = <0>;
compatible = "ti,omap2-iommu";
reg = <0x480bd400 0x80>;
interrupts = <24>;
diff --git a/dts/Bindings/ipmi.txt b/dts/Bindings/ipmi.txt
new file mode 100644
index 0000000..d5f1a87
--- /dev/null
+++ b/dts/Bindings/ipmi.txt
@@ -0,0 +1,25 @@
+IPMI device
+
+Required properties:
+- compatible: should be one of ipmi-kcs, ipmi-smic, or ipmi-bt
+- device_type: should be ipmi
+- reg: Address and length of the register set for the device
+
+Optional properties:
+- interrupts: The interrupt for the device. Without this the interface
+ is polled.
+- reg-size - The size of the register. Defaults to 1
+- reg-spacing - The number of bytes between register starts. Defaults to 1
+- reg-shift - The amount to shift the registers to the right to get the data
+ into bit zero.
+
+Example:
+
+smic@fff3a000 {
+ compatible = "ipmi-smic";
+ device_type = "ipmi";
+ reg = <0xfff3a000 0x1000>;
+ interrupts = <0 24 4>;
+ reg-size = <4>;
+ reg-spacing = <4>;
+};
diff --git a/dts/Bindings/leds/common.txt b/dts/Bindings/leds/common.txt
index 747c538..6841984 100644
--- a/dts/Bindings/leds/common.txt
+++ b/dts/Bindings/leds/common.txt
@@ -29,14 +29,23 @@ Optional properties for child nodes:
"ide-disk" - LED indicates disk activity
"timer" - LED flashes at a fixed, configurable rate
-- max-microamp : maximum intensity in microamperes of the LED
- (torch LED for flash devices)
-- flash-max-microamp : maximum intensity in microamperes of the
- flash LED; it is mandatory if the LED should
- support the flash mode
-- flash-timeout-us : timeout in microseconds after which the flash
- LED is turned off
+- led-max-microamp : Maximum LED supply current in microamperes. This property
+ can be made mandatory for the board configurations
+ introducing a risk of hardware damage in case an excessive
+ current is set.
+ For flash LED controllers with configurable current this
+ property is mandatory for the LEDs in the non-flash modes
+ (e.g. torch or indicator).
+Required properties for flash LED child nodes:
+- flash-max-microamp : Maximum flash LED supply current in microamperes.
+- flash-max-timeout-us : Maximum timeout in microseconds after which the flash
+ LED is turned off.
+
+For controllers that have no configurable current the flash-max-microamp
+property can be omitted.
+For controllers that have no configurable timeout the flash-max-timeout-us
+property can be omitted.
Examples:
@@ -49,7 +58,7 @@ system-status {
camera-flash {
label = "Flash";
led-sources = <0>, <1>;
- max-microamp = <50000>;
+ led-max-microamp = <50000>;
flash-max-microamp = <320000>;
- flash-timeout-us = <500000>;
+ flash-max-timeout-us = <500000>;
};
diff --git a/dts/Bindings/leds/leds-ns2.txt b/dts/Bindings/leds/leds-ns2.txt
index aef3aca..9f81258 100644
--- a/dts/Bindings/leds/leds-ns2.txt
+++ b/dts/Bindings/leds/leds-ns2.txt
@@ -8,6 +8,9 @@ Each LED is represented as a sub-node of the ns2-leds device.
Required sub-node properties:
- cmd-gpio: Command LED GPIO. See OF device-tree GPIO specification.
- slow-gpio: Slow LED GPIO. See OF device-tree GPIO specification.
+- modes-map: A mapping between LED modes (off, on or SATA activity blinking) and
+ the corresponding cmd-gpio/slow-gpio values. All the GPIO values combinations
+ should be given in order to avoid having an unknown mode at driver probe time.
Optional sub-node properties:
- label: Name for this LED. If omitted, the label is taken from the node name.
@@ -15,6 +18,8 @@ Optional sub-node properties:
Example:
+#include <dt-bindings/leds/leds-ns2.h>
+
ns2-leds {
compatible = "lacie,ns2-leds";
@@ -22,5 +27,9 @@ ns2-leds {
label = "ns2:blue:sata";
slow-gpio = <&gpio0 29 0>;
cmd-gpio = <&gpio0 30 0>;
+ modes-map = <NS_V2_LED_OFF 0 1
+ NS_V2_LED_ON 1 0
+ NS_V2_LED_ON 0 0
+ NS_V2_LED_SATA 1 1>;
};
};
diff --git a/dts/Bindings/leds/leds-powernv.txt b/dts/Bindings/leds/leds-powernv.txt
new file mode 100644
index 0000000..6665569
--- /dev/null
+++ b/dts/Bindings/leds/leds-powernv.txt
@@ -0,0 +1,26 @@
+Device Tree binding for LEDs on IBM Power Systems
+-------------------------------------------------
+
+Required properties:
+- compatible : Should be "ibm,opal-v3-led".
+- led-mode : Should be "lightpath" or "guidinglight".
+
+Each location code of FRU/Enclosure must be expressed in the
+form of a sub-node.
+
+Required properties for the sub nodes:
+- led-types : Supported LED types (attention/identify/fault) provided
+ in the form of string array.
+
+Example:
+
+leds {
+ compatible = "ibm,opal-v3-led";
+ led-mode = "lightpath";
+
+ U78C9.001.RST0027-P1-C1 {
+ led-types = "identify", "fault";
+ };
+ ...
+ ...
+};
diff --git a/dts/Bindings/media/i2c/adv7604.txt b/dts/Bindings/media/i2c/adv7604.txt
index c27cede..8337f75 100644
--- a/dts/Bindings/media/i2c/adv7604.txt
+++ b/dts/Bindings/media/i2c/adv7604.txt
@@ -1,15 +1,17 @@
-* Analog Devices ADV7604/11 video decoder with HDMI receiver
+* Analog Devices ADV7604/11/12 video decoder with HDMI receiver
-The ADV7604 and ADV7611 are multiformat video decoders with an integrated HDMI
-receiver. The ADV7604 has four multiplexed HDMI inputs and one analog input,
-and the ADV7611 has one HDMI input and no analog input.
+The ADV7604 and ADV7611/12 are multiformat video decoders with an integrated
+HDMI receiver. The ADV7604 has four multiplexed HDMI inputs and one analog
+input, and the ADV7611 has one HDMI input and no analog input. The 7612 is
+similar to the 7611 but has 2 HDMI inputs.
-These device tree bindings support the ADV7611 only at the moment.
+These device tree bindings support the ADV7611/12 only at the moment.
Required Properties:
- compatible: Must contain one of the following
- "adi,adv7611" for the ADV7611
+ - "adi,adv7612" for the ADV7612
- reg: I2C slave address
@@ -22,10 +24,10 @@ port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
are numbered as follows.
- Port ADV7611
+ Port ADV7611 ADV7612
------------------------------------------------------------
- HDMI 0
- Digital output 1
+ HDMI 0 0, 1
+ Digital output 1 2
The digital output port node must contain at least one endpoint.
@@ -45,6 +47,7 @@ Optional Endpoint Properties:
If none of hsync-active, vsync-active and pclk-sample is specified the
endpoint will use embedded BT.656 synchronization.
+ - default-input: Select which input is selected after reset.
Example:
@@ -58,6 +61,8 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
+ default-input = <0>;
+
port@0 {
reg = <0>;
};
diff --git a/dts/Bindings/media/i2c/tc358743.txt b/dts/Bindings/media/i2c/tc358743.txt
new file mode 100644
index 0000000..5218921
--- /dev/null
+++ b/dts/Bindings/media/i2c/tc358743.txt
@@ -0,0 +1,48 @@
+* Toshiba TC358743 HDMI-RX to MIPI CSI2-TX Bridge
+
+The Toshiba TC358743 HDMI-RX to MIPI CSI2-TX (H2C) is a bridge that converts
+a HDMI stream to MIPI CSI-2 TX. It is programmable through I2C.
+
+Required Properties:
+
+- compatible: value should be "toshiba,tc358743"
+- clocks, clock-names: should contain a phandle link to the reference clock
+ source, the clock input is named "refclk".
+
+Optional Properties:
+
+- reset-gpios: gpio phandle GPIO connected to the reset pin
+- interrupts, interrupt-parent: GPIO connected to the interrupt pin
+- data-lanes: should be <1 2 3 4> for four-lane operation,
+ or <1 2> for two-lane operation
+- clock-lanes: should be <0>
+- clock-noncontinuous: Presence of this boolean property decides whether the
+ MIPI CSI-2 clock is continuous or non-continuous.
+- link-frequencies: List of allowed link frequencies in Hz. Each frequency is
+ expressed as a 64-bit big-endian integer. The frequency
+ is half of the bps per lane due to DDR transmission.
+
+For further information on the MIPI CSI-2 endpoint node properties, see
+Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+Example:
+
+ tc358743@0f {
+ compatible = "toshiba,tc358743";
+ reg = <0x0f>;
+ clocks = <&hdmi_osc>;
+ clock-names = "refclk";
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+
+ port {
+ tc358743_out: endpoint {
+ remote-endpoint = <&mipi_csi2_in>;
+ data-lanes = <1 2 3 4>;
+ clock-lanes = <0>;
+ clock-noncontinuous;
+ link-frequencies = /bits/ 64 <297000000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/media/renesas,jpu.txt b/dts/Bindings/media/renesas,jpu.txt
new file mode 100644
index 0000000..0cb9420
--- /dev/null
+++ b/dts/Bindings/media/renesas,jpu.txt
@@ -0,0 +1,24 @@
+* Renesas JPEG Processing Unit
+
+The JPEG processing unit (JPU) incorporates the JPEG codec with an encoding
+and decoding function conforming to the JPEG baseline process, so that the JPU
+can encode image data and decode JPEG data quickly.
+
+Required properties:
+ - compatible: should containg one of the following:
+ - "renesas,jpu-r8a7790" for R-Car H2
+ - "renesas,jpu-r8a7791" for R-Car M2-W
+ - "renesas,jpu-r8a7792" for R-Car V2H
+ - "renesas,jpu-r8a7793" for R-Car M2-N
+
+ - reg: Base address and length of the registers block for the JPU.
+ - interrupts: JPU interrupt specifier.
+ - clocks: A phandle + clock-specifier pair for the JPU functional clock.
+
+Example: R8A7790 (R-Car H2) JPU node
+ jpeg-codec@fe980000 {
+ compatible = "renesas,jpu-r8a7790";
+ reg = <0 0xfe980000 0 0x10300>;
+ interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mstp1_clks R8A7790_CLK_JPU>;
+ };
diff --git a/dts/Bindings/media/stih407-c8sectpfe.txt b/dts/Bindings/media/stih407-c8sectpfe.txt
new file mode 100644
index 0000000..d4def76
--- /dev/null
+++ b/dts/Bindings/media/stih407-c8sectpfe.txt
@@ -0,0 +1,89 @@
+STMicroelectronics STi c8sectpfe binding
+============================================
+
+This document describes the c8sectpfe device bindings that is used to get transport
+stream data into the SoC on the TS pins, and into DDR for further processing.
+
+It is typically used in conjunction with one or more demodulator and tuner devices
+which converts from the RF to digital domain. Demodulators and tuners are usually
+located on an external DVB frontend card connected to SoC TS input pins.
+
+Currently 7 TS input (tsin) channels are supported on the stih407 family SoC.
+
+Required properties (controller (parent) node):
+- compatible : Should be "stih407-c8sectpfe"
+
+- reg : Address and length of register sets for each device in
+ "reg-names"
+
+- reg-names : The names of the register addresses corresponding to the
+ registers filled in "reg":
+ - c8sectpfe: c8sectpfe registers
+ - c8sectpfe-ram: c8sectpfe internal sram
+
+- clocks : phandle list of c8sectpfe clocks
+- clock-names : should be "c8sectpfe"
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+- pinctrl-names : a pinctrl state named tsin%d-serial or tsin%d-parallel (where %d is tsin-num)
+ must be defined for each tsin child node.
+- pinctrl-0 : phandle referencing pin configuration for this tsin configuration
+See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+
+Required properties (tsin (child) node):
+
+- tsin-num : tsin id of the InputBlock (must be between 0 to 6)
+- i2c-bus : phandle to the I2C bus DT node which the demodulators & tuners on this tsin channel are connected.
+- rst-gpio : reset gpio for this tsin channel.
+
+Optional properties (tsin (child) node):
+
+- invert-ts-clk : Bool property to control sense of ts input clock (data stored on falling edge of clk).
+- serial-not-parallel : Bool property to configure input bus width (serial on ts_data<7>).
+- async-not-sync : Bool property to control if data is received in asynchronous mode
+ (all bits/bytes with ts_valid or ts_packet asserted are valid).
+
+- dvb-card : Describes the NIM card connected to this tsin channel.
+
+Example:
+
+/* stih410 SoC b2120 + b2004a + stv0367-pll(NIMB) + stv0367-tda18212 (NIMA) DT example) */
+
+ c8sectpfe@08a20000 {
+ compatible = "st,stih407-c8sectpfe";
+ status = "okay";
+ reg = <0x08a20000 0x10000>, <0x08a00000 0x4000>;
+ reg-names = "stfe", "stfe-ram";
+ interrupts = <0 34 0>, <0 35 0>;
+ interrupt-names = "stfe-error-irq", "stfe-idle-irq";
+
+ pinctrl-names = "tsin0-serial", "tsin0-parallel", "tsin3-serial",
+ "tsin4-serial", "tsin5-serial";
+
+ pinctrl-0 = <&pinctrl_tsin0_serial>;
+ pinctrl-1 = <&pinctrl_tsin0_parallel>;
+ pinctrl-2 = <&pinctrl_tsin3_serial>;
+ pinctrl-3 = <&pinctrl_tsin4_serial_alt3>;
+ pinctrl-4 = <&pinctrl_tsin5_serial_alt1>;
+
+ clocks = <&clk_s_c0_flexgen CLK_PROC_STFE>;
+ clock-names = "stfe";
+
+ /* tsin0 is TSA on NIMA */
+ tsin0: port@0 {
+ tsin-num = <0>;
+ serial-not-parallel;
+ i2c-bus = <&ssc2>;
+ rst-gpio = <&pio15 4 0>;
+ dvb-card = <STV0367_TDA18212_NIMA_1>;
+ };
+
+ tsin3: port@3 {
+ tsin-num = <3>;
+ serial-not-parallel;
+ i2c-bus = <&ssc3>;
+ rst-gpio = <&pio15 7 0>;
+ dvb-card = <STV0367_TDA18212_NIMB_1>;
+ };
+ };
diff --git a/dts/Bindings/memory-controllers/arm,pl172.txt b/dts/Bindings/memory-controllers/arm,pl172.txt
new file mode 100644
index 0000000..e6df32f
--- /dev/null
+++ b/dts/Bindings/memory-controllers/arm,pl172.txt
@@ -0,0 +1,125 @@
+* Device tree bindings for ARM PL172 MultiPort Memory Controller
+
+Required properties:
+
+- compatible: "arm,pl172", "arm,primecell"
+
+- reg: Must contains offset/length value for controller.
+
+- #address-cells: Must be 2. The partition number has to be encoded in the
+ first address cell and it may accept values 0..N-1
+ (N - total number of partitions). The second cell is the
+ offset into the partition.
+
+- #size-cells: Must be set to 1.
+
+- ranges: Must contain one or more chip select memory regions.
+
+- clocks: Must contain references to controller clocks.
+
+- clock-names: Must contain "mpmcclk" and "apb_pclk".
+
+- clock-ranges: Empty property indicating that child nodes can inherit
+ named clocks. Required only if clock tree data present
+ in device tree.
+ See clock-bindings.txt
+
+Child chip-select (cs) nodes contain the memory devices nodes connected to
+such as NOR (e.g. cfi-flash) and NAND.
+
+Required child cs node properties:
+
+- #address-cells: Must be 2.
+
+- #size-cells: Must be 1.
+
+- ranges: Empty property indicating that child nodes can inherit
+ memory layout.
+
+- clock-ranges: Empty property indicating that child nodes can inherit
+ named clocks. Required only if clock tree data present
+ in device tree.
+
+- mpmc,cs: Chip select number. Indicates to the pl0172 driver
+ which chipselect is used for accessing the memory.
+
+- mpmc,memory-width: Width of the chip select memory. Must be equal to
+ either 8, 16 or 32.
+
+Optional child cs node config properties:
+
+- mpmc,async-page-mode: Enable asynchronous page mode.
+
+- mpmc,cs-active-high: Set chip select polarity to active high.
+
+- mpmc,byte-lane-low: Set byte lane state to low.
+
+- mpmc,extended-wait: Enable extended wait.
+
+- mpmc,buffer-enable: Enable write buffer.
+
+- mpmc,write-protect: Enable write protect.
+
+Optional child cs node timing properties:
+
+- mpmc,write-enable-delay: Delay from chip select assertion to write
+ enable (WE signal) in nano seconds.
+
+- mpmc,output-enable-delay: Delay from chip select assertion to output
+ enable (OE signal) in nano seconds.
+
+- mpmc,write-access-delay: Delay from chip select assertion to write
+ access in nano seconds.
+
+- mpmc,read-access-delay: Delay from chip select assertion to read
+ access in nano seconds.
+
+- mpmc,page-mode-read-delay: Delay for asynchronous page mode sequential
+ accesses in nano seconds.
+
+- mpmc,turn-round-delay: Delay between access to memory banks in nano
+ seconds.
+
+If any of the above timing parameters are absent, current parameter value will
+be taken from the corresponding HW reg.
+
+Example for pl172 with nor flash on chip select 0 shown below.
+
+emc: memory-controller@40005000 {
+ compatible = "arm,pl172", "arm,primecell";
+ reg = <0x40005000 0x1000>;
+ clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
+ clock-names = "mpmcclk", "apb_pclk";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0 0x1c000000 0x1000000
+ 1 0 0x1d000000 0x1000000
+ 2 0 0x1e000000 0x1000000
+ 3 0 0x1f000000 0x1000000>;
+
+ cs0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ mpmc,cs = <0>;
+ mpmc,memory-width = <16>;
+ mpmc,byte-lane-low;
+ mpmc,write-enable-delay = <0>;
+ mpmc,output-enable-delay = <0>;
+ mpmc,read-enable-delay = <70>;
+ mpmc,page-mode-read-delay = <70>;
+
+ flash@0,0 {
+ compatible = "sst,sst39vf320", "cfi-flash";
+ reg = <0 0 0x400000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "data";
+ reg = <0 0x400000>;
+ };
+ };
+ };
+};
diff --git a/dts/Bindings/memory-controllers/fsl/ifc.txt b/dts/Bindings/memory-controllers/fsl/ifc.txt
index d5e3704..89427b0 100644
--- a/dts/Bindings/memory-controllers/fsl/ifc.txt
+++ b/dts/Bindings/memory-controllers/fsl/ifc.txt
@@ -18,6 +18,8 @@ Properties:
interrupt (NAND_EVTER_STAT). If there is only one,
that interrupt reports both types of event.
+- little-endian : If this property is absent, the big-endian mode will
+ be in use as default for registers.
- ranges : Each range corresponds to a single chipselect, and covers
the entire access window as configured.
@@ -34,6 +36,7 @@ Example:
#size-cells = <1>;
reg = <0x0 0xffe1e000 0 0x2000>;
interrupts = <16 2 19 2>;
+ little-endian;
/* NOR, NAND Flashes and CPLD on board */
ranges = <0x0 0x0 0x0 0xee000000 0x02000000
diff --git a/dts/Bindings/memory-controllers/synopsys.txt b/dts/Bindings/memory-controllers/synopsys.txt
index f9c6454..a43d26d 100644
--- a/dts/Bindings/memory-controllers/synopsys.txt
+++ b/dts/Bindings/memory-controllers/synopsys.txt
@@ -1,5 +1,9 @@
Binding for Synopsys IntelliDDR Multi Protocol Memory Controller
+This controller has an optional ECC support in half-bus width (16-bit)
+configuration. The ECC controller corrects one bit error and detects
+two bit errors.
+
Required properties:
- compatible: Should be 'xlnx,zynq-ddrc-a05'
- reg: Base address and size of the controllers memory area
diff --git a/dts/Bindings/mfd/atmel-hlcdc.txt b/dts/Bindings/mfd/atmel-hlcdc.txt
index f64de95..ad5d904 100644
--- a/dts/Bindings/mfd/atmel-hlcdc.txt
+++ b/dts/Bindings/mfd/atmel-hlcdc.txt
@@ -2,7 +2,11 @@ Device-Tree bindings for Atmel's HLCDC (High LCD Controller) MFD driver
Required properties:
- compatible: value should be one of the following:
+ "atmel,at91sam9n12-hlcdc"
+ "atmel,at91sam9x5-hlcdc"
+ "atmel,sama5d2-hlcdc"
"atmel,sama5d3-hlcdc"
+ "atmel,sama5d4-hlcdc"
- reg: base address and size of the HLCDC device registers.
- clock-names: the name of the 3 clocks requested by the HLCDC device.
Should contain "periph_clk", "sys_clk" and "slow_clk".
diff --git a/dts/Bindings/mfd/axp20x.txt b/dts/Bindings/mfd/axp20x.txt
index 753f14f..4181122 100644
--- a/dts/Bindings/mfd/axp20x.txt
+++ b/dts/Bindings/mfd/axp20x.txt
@@ -1,12 +1,14 @@
AXP family PMIC device tree bindings
The axp20x family current members :
+axp152 (X-Powers)
axp202 (X-Powers)
axp209 (X-Powers)
axp221 (X-Powers)
Required properties:
-- compatible: "x-powers,axp202", "x-powers,axp209", "x-powers,axp221"
+- compatible: "x-powers,axp152", "x-powers,axp202", "x-powers,axp209",
+ "x-powers,axp221"
- reg: The I2C slave address for the AXP chip
- interrupt-parent: The parent interrupt controller
- interrupts: SoC NMI / GPIO interrupt connected to the PMIC's IRQ pin
diff --git a/dts/Bindings/mfd/da9062.txt b/dts/Bindings/mfd/da9062.txt
new file mode 100644
index 0000000..38802b5
--- /dev/null
+++ b/dts/Bindings/mfd/da9062.txt
@@ -0,0 +1,88 @@
+* Dialog DA9062 Power Management Integrated Circuit (PMIC)
+
+DA9062 consists of a large and varied group of sub-devices:
+
+Device Supply Names Description
+------ ------------ -----------
+da9062-regulator : : LDOs & BUCKs
+da9062-rtc : : Real-Time Clock
+da9062-watchdog : : Watchdog Timer
+
+======
+
+Required properties:
+
+- compatible : Should be "dlg,da9062".
+- reg : Specifies the I2C slave address (this defaults to 0x58 but it can be
+ modified to match the chip's OTP settings).
+- interrupt-parent : Specifies the reference to the interrupt controller for
+ the DA9062.
+- interrupts : IRQ line information.
+- interrupt-controller
+
+See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
+further information on IRQ bindings.
+
+Sub-nodes:
+
+- regulators : This node defines the settings for the LDOs and BUCKs. The
+ DA9062 regulators are bound using their names listed below:
+
+ buck1 : BUCK_1
+ buck2 : BUCK_2
+ buck3 : BUCK_3
+ buck4 : BUCK_4
+ ldo1 : LDO_1
+ ldo2 : LDO_2
+ ldo3 : LDO_3
+ ldo4 : LDO_4
+
+ The component follows the standard regulator framework and the bindings
+ details of individual regulator device can be found in:
+ Documentation/devicetree/bindings/regulator/regulator.txt
+
+
+- rtc : This node defines settings required for the Real-Time Clock associated
+ with the DA9062. There are currently no entries in this binding, however
+ compatible = "dlg,da9062-rtc" should be added if a node is created.
+
+- watchdog: This node defines the settings for the watchdog driver associated
+ with the DA9062 PMIC. The compatible = "dlg,da9062-watchdog" should be added
+ if a node is created.
+
+
+Example:
+
+ pmic0: da9062@58 {
+ compatible = "dlg,da9062";
+ reg = <0x58>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ rtc {
+ compatible = "dlg,da9062-rtc";
+ };
+
+ watchdog {
+ compatible = "dlg,da9062-watchdog";
+ };
+
+ regulators {
+ DA9062_BUCK1: buck1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <500000>;
+ regulator-max-microamp = <2000000>;
+ regulator-boot-on;
+ };
+ DA9062_LDO1: ldo1 {
+ regulator-name = "LDO_1";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-boot-on;
+ };
+ };
+ };
+
diff --git a/dts/Bindings/mfd/max77686.txt b/dts/Bindings/mfd/max77686.txt
index 163bd81..741e766 100644
--- a/dts/Bindings/mfd/max77686.txt
+++ b/dts/Bindings/mfd/max77686.txt
@@ -7,8 +7,9 @@ different i2c slave address,presently for which we are statically creating i2c
client while probing.This document describes the binding for mfd device and
PMIC submodule.
-Binding for the built-in 32k clock generator block is defined separately
-in bindings/clk/maxim,max77686.txt file.
+Bindings for the built-in 32k clock generator block and
+regulators are defined in ../clk/maxim,max77686.txt and
+../regulator/max77686.txt respectively.
Required properties:
- compatible : Must be "maxim,max77686";
@@ -16,67 +17,11 @@ Required properties:
- interrupts : This i2c device has an IRQ line connected to the main SoC.
- interrupt-parent : The parent interrupt controller.
-Optional node:
-- voltage-regulators : The regulators of max77686 have to be instantiated
- under subnode named "voltage-regulators" using the following format.
-
- regulator_name {
- regulator-compatible = LDOn/BUCKn
- standard regulator constraints....
- };
- refer Documentation/devicetree/bindings/regulator/regulator.txt
-
- The regulator-compatible property of regulator should initialized with string
-to get matched with their hardware counterparts as follow:
-
- -LDOn : for LDOs, where n can lie in range 1 to 26.
- example: LDO1, LDO2, LDO26.
- -BUCKn : for BUCKs, where n can lie in range 1 to 9.
- example: BUCK1, BUCK5, BUCK9.
-
- Regulators which can be turned off during system suspend:
- -LDOn : 2, 6-8, 10-12, 14-16,
- -BUCKn : 1-4.
- Use standard regulator bindings for it ('regulator-off-in-suspend').
-
- LDO20, LDO21, LDO22, BUCK8 and BUCK9 can be configured to GPIO enable
- control. To turn this feature on this property must be added to the regulator
- sub-node:
- - maxim,ena-gpios : one GPIO specifier enable control (the gpio
- flags are actually ignored and always
- ACTIVE_HIGH is used)
-
Example:
- max77686@09 {
+ max77686: pmic@09 {
compatible = "maxim,max77686";
interrupt-parent = <&wakeup_eint>;
interrupts = <26 0>;
reg = <0x09>;
-
- voltage-regulators {
- ldo11_reg {
- regulator-compatible = "LDO11";
- regulator-name = "vdd_ldo11";
- regulator-min-microvolt = <1900000>;
- regulator-max-microvolt = <1900000>;
- regulator-always-on;
- };
-
- buck1_reg {
- regulator-compatible = "BUCK1";
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck9_reg {
- regulator-compatible = "BUCK9";
- regulator-name = "CAM_ISP_CORE_1.2V";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1200000>;
- maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
- };
- }
+ };
diff --git a/dts/Bindings/mfd/max77802.txt b/dts/Bindings/mfd/max77802.txt
new file mode 100644
index 0000000..51fc1a6
--- /dev/null
+++ b/dts/Bindings/mfd/max77802.txt
@@ -0,0 +1,26 @@
+Maxim MAX77802 multi-function device
+
+The Maxim MAX77802 is a Power Management IC (PMIC) that contains 10 high
+efficiency Buck regulators, 32 Low-DropOut (LDO) regulators used to power
+up application processors and peripherals, a 2-channel 32kHz clock outputs,
+a Real-Time-Clock (RTC) and a I2C interface to program the individual
+regulators, clocks outputs and the RTC.
+
+Bindings for the built-in 32k clock generator block and
+regulators are defined in ../clk/maxim,max77802.txt and
+../regulator/max77802.txt respectively.
+
+Required properties:
+- compatible : Must be "maxim,max77802"
+- reg : Specifies the I2C slave address of PMIC block.
+- interrupts : I2C device IRQ line connected to the main SoC.
+- interrupt-parent : The parent interrupt controller.
+
+Example:
+
+ max77802: pmic@09 {
+ compatible = "maxim,max77802";
+ interrupt-parent = <&intc>;
+ interrupts = <26 IRQ_TYPE_NONE>;
+ reg = <0x09>;
+ };
diff --git a/dts/Bindings/mfd/rk808.txt b/dts/Bindings/mfd/rk808.txt
index 9e6e259..4ca6aab 100644
--- a/dts/Bindings/mfd/rk808.txt
+++ b/dts/Bindings/mfd/rk808.txt
@@ -24,6 +24,10 @@ Optional properties:
- vcc10-supply: The input supply for LDO_REG6
- vcc11-supply: The input supply for LDO_REG8
- vcc12-supply: The input supply for SWITCH_REG2
+- dvs-gpios: buck1/2 can be controlled by gpio dvs, this is GPIO specifiers
+ for 2 host gpio's used for dvs. The format of the gpio specifier depends in
+ the gpio controller. If DVS GPIOs aren't present, voltage changes will happen
+ very quickly with no slow ramp time.
Regulators: All the regulators of RK808 to be instantiated shall be
listed in a child node named 'regulators'. Each regulator is represented
@@ -55,7 +59,9 @@ Example:
interrupt-parent = <&gpio0>;
interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
- pinctrl-0 = <&pmic_int>;
+ pinctrl-0 = <&pmic_int &dvs_1 &dvs_2>;
+ dvs-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>,
+ <&gpio7 15 GPIO_ACTIVE_HIGH>;
reg = <0x1b>;
rockchip,system-power-controller;
wakeup-source;
diff --git a/dts/Bindings/mfd/tc3589x.txt b/dts/Bindings/mfd/tc3589x.txt
index 6fcedba..37bf7f1 100644
--- a/dts/Bindings/mfd/tc3589x.txt
+++ b/dts/Bindings/mfd/tc3589x.txt
@@ -55,7 +55,7 @@ Optional nodes:
- linux,keymap: the definition can be found in
bindings/input/matrix-keymap.txt
- linux,no-autorepeat: do no enable autorepeat feature.
- - linux,wakeup: use any event on keypad as wakeup event.
+ - wakeup-source: use any event on keypad as wakeup event.
Example:
@@ -84,7 +84,6 @@ tc35893@44 {
keypad,num-columns = <8>;
keypad,num-rows = <8>;
linux,no-autorepeat;
- linux,wakeup;
linux,keymap = <0x0301006b
0x04010066
0x06040072
@@ -103,5 +102,6 @@ tc35893@44 {
0x01030039
0x07060069
0x050500d9>;
+ wakeup-source;
};
};
diff --git a/dts/Bindings/mmc/arasan,sdhci.txt b/dts/Bindings/mmc/arasan,sdhci.txt
index 7e94903..da541c3 100644
--- a/dts/Bindings/mmc/arasan,sdhci.txt
+++ b/dts/Bindings/mmc/arasan,sdhci.txt
@@ -9,7 +9,7 @@ Device Tree Bindings for the Arasan SDHCI Controller
Required Properties:
- compatible: Compatibility string. Must be 'arasan,sdhci-8.9a' or
- 'arasan,sdhci-4.9a'
+ 'arasan,sdhci-4.9a' or 'arasan,sdhci-5.1'
- reg: From mmc bindings: Register location and length.
- clocks: From clock bindings: Handles to clock inputs.
- clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb"
diff --git a/dts/Bindings/mmc/fsl-imx-esdhc.txt b/dts/Bindings/mmc/fsl-imx-esdhc.txt
index 211e778..dca56d6 100644
--- a/dts/Bindings/mmc/fsl-imx-esdhc.txt
+++ b/dts/Bindings/mmc/fsl-imx-esdhc.txt
@@ -15,6 +15,7 @@ Required properties:
"fsl,imx6q-usdhc"
"fsl,imx6sl-usdhc"
"fsl,imx6sx-usdhc"
+ "fsl,imx7d-usdhc"
Optional properties:
- fsl,wp-controller : Indicate to use controller internal write protection
@@ -27,6 +28,11 @@ Optional properties:
transparent level shifters on the outputs of the controller. Two cells are
required, first cell specifies minimum slot voltage (mV), second cell
specifies maximum slot voltage (mV). Several ranges could be specified.
+- fsl,tuning-step: Specify the increasing delay cell steps in tuning procedure.
+ The uSDHC use one delay cell as default increasing step to do tuning process.
+ This property allows user to change the tuning step to more than one delay
+ cells which is useful for some special boards or cards when the default
+ tuning step can't find the proper delay window within limited tuning retries.
Examples:
diff --git a/dts/Bindings/mmc/sdhci-atmel.txt b/dts/Bindings/mmc/sdhci-atmel.txt
new file mode 100644
index 0000000..1b662d7
--- /dev/null
+++ b/dts/Bindings/mmc/sdhci-atmel.txt
@@ -0,0 +1,21 @@
+* Atmel SDHCI controller
+
+This file documents the differences between the core properties in
+Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
+sdhci-of-at91 driver.
+
+Required properties:
+- compatible: Must be "atmel,sama5d2-sdhci".
+- clocks: Phandlers to the clocks.
+- clock-names: Must be "hclock", "multclk", "baseclk";
+
+
+Example:
+
+sdmmc0: sdio-host@a0000000 {
+ compatible = "atmel,sama5d2-sdhci";
+ reg = <0xa0000000 0x300>;
+ interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
+ clock-names = "hclock", "multclk", "baseclk";
+};
diff --git a/dts/Bindings/mmc/ti-omap-hsmmc.txt b/dts/Bindings/mmc/ti-omap-hsmmc.txt
index 76bf087..74166a0 100644
--- a/dts/Bindings/mmc/ti-omap-hsmmc.txt
+++ b/dts/Bindings/mmc/ti-omap-hsmmc.txt
@@ -102,7 +102,7 @@ not every application needs SDIO irq, e.g. MMC cards.
pinctrl-1 = <&mmc1_idle>;
pinctrl-2 = <&mmc1_sleep>;
...
- interrupts-extended = <&intc 64 &gpio2 28 0>;
+ interrupts-extended = <&intc 64 &gpio2 28 GPIO_ACTIVE_LOW>;
};
mmc1_idle : pinmux_cirq_pin {
diff --git a/dts/Bindings/mtd/fsl-quadspi.txt b/dts/Bindings/mtd/fsl-quadspi.txt
index 4461dc7..862aa2f 100644
--- a/dts/Bindings/mtd/fsl-quadspi.txt
+++ b/dts/Bindings/mtd/fsl-quadspi.txt
@@ -1,7 +1,8 @@
* Freescale Quad Serial Peripheral Interface(QuadSPI)
Required properties:
- - compatible : Should be "fsl,vf610-qspi" or "fsl,imx6sx-qspi"
+ - compatible : Should be "fsl,vf610-qspi", "fsl,imx6sx-qspi",
+ "fsl,imx7d-qspi", "fsl,imx6ul-qspi"
- reg : the first contains the register location and length,
the second contains the memory mapping address and length
- reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory"
diff --git a/dts/Bindings/mtd/nxp-spifi.txt b/dts/Bindings/mtd/nxp-spifi.txt
new file mode 100644
index 0000000..f8b6b25
--- /dev/null
+++ b/dts/Bindings/mtd/nxp-spifi.txt
@@ -0,0 +1,58 @@
+* NXP SPI Flash Interface (SPIFI)
+
+NXP SPIFI is a specialized SPI interface for serial Flash devices.
+It supports one Flash device with 1-, 2- and 4-bits width in SPI
+mode 0 or 3. The controller operates in either command or memory
+mode. In memory mode the Flash is accessible from the CPU as
+normal memory.
+
+Required properties:
+ - compatible : Should be "nxp,lpc1773-spifi"
+ - reg : the first contains the register location and length,
+ the second contains the memory mapping address and length
+ - reg-names: Should contain the reg names "spifi" and "flash"
+ - interrupts : Should contain the interrupt for the device
+ - clocks : The clocks needed by the SPIFI controller
+ - clock-names : Should contain the clock names "spifi" and "reg"
+
+Optional properties:
+ - resets : phandle + reset specifier
+
+The SPI Flash must be a child of the SPIFI node and must have a
+compatible property as specified in bindings/mtd/jedec,spi-nor.txt
+
+Optionally it can also contain the following properties.
+ - spi-cpol : Controller only supports mode 0 and 3 so either
+ both spi-cpol and spi-cpha should be present or
+ none of them
+ - spi-cpha : See above
+ - spi-rx-bus-width : Used to select how many pins that are used
+ for input on the controller
+
+See bindings/spi/spi-bus.txt for more information.
+
+Example:
+spifi: spifi@40003000 {
+ compatible = "nxp,lpc1773-spifi";
+ reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
+ reg-names = "spifi", "flash";
+ interrupts = <30>;
+ clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
+ clock-names = "spifi", "reg";
+ resets = <&rgu 53>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-cpol;
+ spi-cpha;
+ spi-rx-bus-width = <4>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "data";
+ reg = <0 0x200000>;
+ };
+ };
+};
+
diff --git a/dts/Bindings/mtd/pxa3xx-nand.txt b/dts/Bindings/mtd/pxa3xx-nand.txt
index 4f833e3..d9b655f 100644
--- a/dts/Bindings/mtd/pxa3xx-nand.txt
+++ b/dts/Bindings/mtd/pxa3xx-nand.txt
@@ -11,6 +11,7 @@ Required properties:
Optional properties:
+ - dmas: dma data channel, see dma.txt binding doc
- marvell,nand-enable-arbiter: Set to enable the bus arbiter
- marvell,nand-keep-config: Set to keep the NAND controller config as set
by the bootloader
@@ -32,6 +33,8 @@ Example:
compatible = "marvell,pxa3xx-nand";
reg = <0x43100000 90>;
interrupts = <45>;
+ dmas = <&pdma 97 0>;
+ dma-names = "data";
#address-cells = <1>;
marvell,nand-enable-arbiter;
diff --git a/dts/Bindings/net/cpsw.txt b/dts/Bindings/net/cpsw.txt
index 33fe846..a9df21a 100644
--- a/dts/Bindings/net/cpsw.txt
+++ b/dts/Bindings/net/cpsw.txt
@@ -2,7 +2,11 @@ TI SoC Ethernet Switch Controller Device Tree Bindings
------------------------------------------------------
Required properties:
-- compatible : Should be "ti,cpsw"
+- compatible : Should be one of the below:-
+ "ti,cpsw" for backward compatible
+ "ti,am335x-cpsw" for AM335x controllers
+ "ti,am4372-cpsw" for AM437x controllers
+ "ti,dra7-cpsw" for DRA7x controllers
- reg : physical base address and size of the cpsw
registers map
- interrupts : property with a value describing the interrupt
diff --git a/dts/Bindings/net/dsa/dsa.txt b/dts/Bindings/net/dsa/dsa.txt
index f0b4cd7..04e6bef 100644
--- a/dts/Bindings/net/dsa/dsa.txt
+++ b/dts/Bindings/net/dsa/dsa.txt
@@ -44,9 +44,10 @@ Note that a port labelled "dsa" will imply checking for the uplink phandle
described below.
Optionnal property:
-- link : Should be a phandle to another switch's DSA port.
+- link : Should be a list of phandles to another switch's DSA port.
This property is only used when switches are being
- chained/cascaded together.
+ chained/cascaded together. This port is used as outgoing port
+ towards the phandle port, which can be more than one hop away.
- phy-handle : Phandle to a PHY on an external MDIO bus, not the
switch internal one. See
@@ -58,6 +59,10 @@ Optionnal property:
Documentation/devicetree/bindings/net/ethernet.txt
for details.
+- mii-bus : Should be a phandle to a valid MDIO bus device node.
+ This mii-bus will be used in preference to the
+ global dsa,mii-bus defined above, for this switch.
+
Optional subnodes:
- fixed-link : Fixed-link subnode describing a link to a non-MDIO
managed entity. See
@@ -96,10 +101,11 @@ Example:
label = "cpu";
};
- switch0uplink: port@6 {
+ switch0port6: port@6 {
reg = <6>;
label = "dsa";
- link = <&switch1uplink>;
+ link = <&switch1port0
+ &switch2port0>;
};
};
@@ -107,11 +113,31 @@ Example:
#address-cells = <1>;
#size-cells = <0>;
reg = <17 1>; /* MDIO address 17, switch 1 in tree */
+ mii-bus = <&mii_bus1>;
+
+ switch1port0: port@0 {
+ reg = <0>;
+ label = "dsa";
+ link = <&switch0port6>;
+ };
+ switch1port1: port@1 {
+ reg = <1>;
+ label = "dsa";
+ link = <&switch2port1>;
+ };
+ };
+
+ switch@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <18 2>; /* MDIO address 18, switch 2 in tree */
+ mii-bus = <&mii_bus1>;
- switch1uplink: port@0 {
+ switch2port0: port@0 {
reg = <0>;
label = "dsa";
- link = <&switch0uplink>;
+ link = <&switch1port1
+ &switch0port6>;
};
};
};
diff --git a/dts/Bindings/net/ethernet.txt b/dts/Bindings/net/ethernet.txt
index 41b3f3f..5d88f37 100644
--- a/dts/Bindings/net/ethernet.txt
+++ b/dts/Bindings/net/ethernet.txt
@@ -25,7 +25,11 @@ The following properties are common to the Ethernet controllers:
flow control thresholds.
- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
is used for components that can have configurable fifo sizes.
+- managed: string, specifies the PHY management type. Supported values are:
+ "auto", "in-band-status". "auto" is the default, it usess MDIO for
+ management if fixed-link is not specified.
Child nodes of the Ethernet controller are typically the individual PHY devices
connected via the MDIO bus (sometimes the MDIO bus controller is separate).
They are described in the phy.txt file in this same directory.
+For non-MDIO PHY management see fixed-link.txt.
diff --git a/dts/Bindings/net/fixed-link.txt b/dts/Bindings/net/fixed-link.txt
index 82bf7e0..ec5d889 100644
--- a/dts/Bindings/net/fixed-link.txt
+++ b/dts/Bindings/net/fixed-link.txt
@@ -17,6 +17,8 @@ properties:
enabled.
* 'asym-pause' (boolean, optional), to indicate that asym_pause should
be enabled.
+* 'link-gpios' ('gpio-list', optional), to indicate if a gpio can be read
+ to determine if the link is up.
Old, deprecated 'fixed-link' binding:
@@ -30,7 +32,7 @@ Old, deprecated 'fixed-link' binding:
- e: asymmetric pause configuration: 0 for no asymmetric pause, 1 for
asymmetric pause
-Example:
+Examples:
ethernet@0 {
...
@@ -40,3 +42,13 @@ ethernet@0 {
};
...
};
+
+ethernet@1 {
+ ...
+ fixed-link {
+ speed = <1000>;
+ pause;
+ link-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+ };
+ ...
+};
diff --git a/dts/Bindings/net/keystone-netcp.txt b/dts/Bindings/net/keystone-netcp.txt
index d0e6fa3..b30ab6b 100644
--- a/dts/Bindings/net/keystone-netcp.txt
+++ b/dts/Bindings/net/keystone-netcp.txt
@@ -130,7 +130,11 @@ Required properties:
Optional properties:
- efuse-mac: If this is 1, then the MAC address for the interface is
- obtained from the device efuse mac address register
+ obtained from the device efuse mac address register.
+ If this is 2, the two DWORDs occupied by the MAC address
+ are swapped. The netcp driver will swap the two DWORDs
+ back to the proper order when this property is set to 2
+ when it obtains the mac address from efuse.
- local-mac-address: the driver is designed to use the of_get_mac_address api
only if efuse-mac is 0. When efuse-mac is 0, the MAC
address is obtained from local-mac-address. If this
diff --git a/dts/Bindings/net/nfc/s3fwrn5.txt b/dts/Bindings/net/nfc/s3fwrn5.txt
new file mode 100644
index 0000000..fb1e75f
--- /dev/null
+++ b/dts/Bindings/net/nfc/s3fwrn5.txt
@@ -0,0 +1,27 @@
+* Samsung S3FWRN5 NCI NFC Controller
+
+Required properties:
+- compatible: Should be "samsung,s3fwrn5-i2c".
+- reg: address on the bus
+- interrupt-parent: phandle for the interrupt gpio controller
+- interrupts: GPIO interrupt to which the chip is connected
+- s3fwrn5,en-gpios: Output GPIO pin used for enabling/disabling the chip
+- s3fwrn5,fw-gpios: Output GPIO pin used to enter firmware mode and
+ sleep/wakeup control
+
+Example:
+
+&hsi2c_4 {
+ status = "okay";
+ s3fwrn5@27 {
+ compatible = "samsung,s3fwrn5-i2c";
+
+ reg = <0x27>;
+
+ interrupt-parent = <&gpa1>;
+ interrupts = <3 0 0>;
+
+ s3fwrn5,en-gpios = <&gpf1 4 0>;
+ s3fwrn5,fw-gpios = <&gpj0 2 0>;
+ };
+};
diff --git a/dts/Bindings/net/nfc/st-nci.txt b/dts/Bindings/net/nfc/st-nci-i2c.txt
index d707588..d707588 100644
--- a/dts/Bindings/net/nfc/st-nci.txt
+++ b/dts/Bindings/net/nfc/st-nci-i2c.txt
diff --git a/dts/Bindings/net/nfc/st-nci-spi.txt b/dts/Bindings/net/nfc/st-nci-spi.txt
new file mode 100644
index 0000000..525681b
--- /dev/null
+++ b/dts/Bindings/net/nfc/st-nci-spi.txt
@@ -0,0 +1,31 @@
+* STMicroelectronics SAS. ST NCI NFC Controller
+
+Required properties:
+- compatible: Should be "st,st21nfcb-spi"
+- spi-max-frequency: Maximum SPI frequency (<= 10000000).
+- interrupt-parent: phandle for the interrupt gpio controller
+- interrupts: GPIO interrupt to which the chip is connected
+- reset-gpios: Output GPIO pin used to reset the ST21NFCB
+
+Optional SoC Specific Properties:
+- pinctrl-names: Contains only one value - "default".
+- pintctrl-0: Specifies the pin control groups used for this controller.
+
+Example (for ARM-based BeagleBoard xM with ST21NFCB on SPI4):
+
+&mcspi4 {
+
+ status = "okay";
+
+ st21nfcb: st21nfcb@0 {
+
+ compatible = "st,st21nfcb-spi";
+
+ clock-frequency = <4000000>;
+
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
+
+ reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
+ };
+};
diff --git a/dts/Bindings/net/snps,dwc-qos-ethernet.txt b/dts/Bindings/net/snps,dwc-qos-ethernet.txt
new file mode 100644
index 0000000..51f8d2e
--- /dev/null
+++ b/dts/Bindings/net/snps,dwc-qos-ethernet.txt
@@ -0,0 +1,75 @@
+* Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
+
+
+Required properties:
+- compatible: Should be "snps,dwc-qos-ethernet-4.10"
+- reg: Address and length of the register set for the device
+- clocks: Phandles to the reference clock and the bus clock
+- clock-names: Should be "phy_ref_clk" for the reference clock and "apb_pclk"
+ for the bus clock.
+- interrupt-parent: Should be the phandle for the interrupt controller
+ that services interrupts for this device
+- interrupts: Should contain the core's combined interrupt signal
+- phy-mode: See ethernet.txt file in the same directory
+
+Optional properties:
+- dma-coherent: Present if dma operations are coherent
+- mac-address: See ethernet.txt in the same directory
+- local-mac-address: See ethernet.txt in the same directory
+- snps,en-lpi: If present it enables use of the AXI low-power interface
+- snps,write-requests: Number of write requests that the AXI port can issue.
+ It depends on the SoC configuration.
+- snps,read-requests: Number of read requests that the AXI port can issue.
+ It depends on the SoC configuration.
+- snps,burst-map: Bitmap of allowed AXI burst lengts, with the LSB
+ representing 4, then 8 etc.
+- snps,txpbl: DMA Programmable burst length for the TX DMA
+- snps,rxpbl: DMA Programmable burst length for the RX DMA
+- snps,en-tx-lpi-clockgating: Enable gating of the MAC TX clock during
+ TX low-power mode.
+- phy-handle: See ethernet.txt file in the same directory
+- mdio device tree subnode: When the GMAC has a phy connected to its local
+ mdio, there must be device tree subnode with the following
+ required properties:
+ - compatible: Must be "snps,dwc-qos-ethernet-mdio".
+ - #address-cells: Must be <1>.
+ - #size-cells: Must be <0>.
+
+ For each phy on the mdio bus, there must be a node with the following
+ fields:
+
+ - reg: phy id used to communicate to phy.
+ - device_type: Must be "ethernet-phy".
+ - fixed-mode device tree subnode: see fixed-link.txt in the same directory
+
+Examples:
+ethernet2@40010000 {
+ clock-names = "phy_ref_clk", "apb_pclk";
+ clocks = <&clkc 17>, <&clkc 15>;
+ compatible = "snps,dwc-qos-ethernet-4.10";
+ interrupt-parent = <&intc>;
+ interrupts = <0x0 0x1e 0x4>;
+ reg = <0x40010000 0x4000>;
+ phy-handle = <&phy2>;
+ phy-mode = "gmii";
+
+ snps,en-tx-lpi-clockgating;
+ snps,en-lpi;
+ snps,write-requests = <2>;
+ snps,read-requests = <16>;
+ snps,burst-map = <0x7>;
+ snps,txpbl = <8>;
+ snps,rxpbl = <2>;
+
+ dma-coherent;
+
+ mdio {
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ phy2: phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ device_type = "ethernet-phy";
+ reg = <0x1>;
+ };
+ };
+};
diff --git a/dts/Bindings/misc/allwinner,sunxi-sid.txt b/dts/Bindings/nvmem/allwinner,sunxi-sid.txt
index fabdf64..d543ed3 100644
--- a/dts/Bindings/misc/allwinner,sunxi-sid.txt
+++ b/dts/Bindings/nvmem/allwinner,sunxi-sid.txt
@@ -4,6 +4,10 @@ Required properties:
- compatible: "allwinner,sun4i-a10-sid" or "allwinner,sun7i-a20-sid"
- reg: Should contain registers location and length
+= Data cells =
+Are child nodes of qfprom, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
Example for sun4i:
sid@01c23800 {
compatible = "allwinner,sun4i-a10-sid";
diff --git a/dts/Bindings/nvmem/nvmem.txt b/dts/Bindings/nvmem/nvmem.txt
new file mode 100644
index 0000000..b52bc11
--- /dev/null
+++ b/dts/Bindings/nvmem/nvmem.txt
@@ -0,0 +1,80 @@
+= NVMEM(Non Volatile Memory) Data Device Tree Bindings =
+
+This binding is intended to represent the location of hardware
+configuration data stored in NVMEMs like eeprom, efuses and so on.
+
+On a significant proportion of boards, the manufacturer has stored
+some data on NVMEM, for the OS to be able to retrieve these information
+and act upon it. Obviously, the OS has to know about where to retrieve
+these data from, and where they are stored on the storage device.
+
+This document is here to document this.
+
+= Data providers =
+Contains bindings specific to provider drivers and data cells as children
+of this node.
+
+Optional properties:
+ read-only: Mark the provider as read only.
+
+= Data cells =
+These are the child nodes of the provider which contain data cell
+information like offset and size in nvmem provider.
+
+Required properties:
+reg: specifies the offset in byte within the storage device.
+
+Optional properties:
+
+bits: Is pair of bit location and number of bits, which specifies offset
+ in bit and number of bits within the address range specified by reg property.
+ Offset takes values from 0-7.
+
+For example:
+
+ /* Provider */
+ qfprom: qfprom@00700000 {
+ ...
+
+ /* Data cells */
+ tsens_calibration: calib@404 {
+ reg = <0x404 0x10>;
+ };
+
+ tsens_calibration_bckp: calib_bckp@504 {
+ reg = <0x504 0x11>;
+ bits = <6 128>
+ };
+
+ pvs_version: pvs-version@6 {
+ reg = <0x6 0x2>
+ bits = <7 2>
+ };
+
+ speed_bin: speed-bin@c{
+ reg = <0xc 0x1>;
+ bits = <2 3>;
+
+ };
+ ...
+ };
+
+= Data consumers =
+Are device nodes which consume nvmem data cells/providers.
+
+Required-properties:
+nvmem-cells: list of phandle to the nvmem data cells.
+nvmem-cell-names: names for the each nvmem-cells specified. Required if
+ nvmem-cells is used.
+
+Optional-properties:
+nvmem : list of phandles to nvmem providers.
+nvmem-names: names for the each nvmem provider. required if nvmem is used.
+
+For example:
+
+ tsens {
+ ...
+ nvmem-cells = <&tsens_calibration>;
+ nvmem-cell-names = "calibration";
+ };
diff --git a/dts/Bindings/nvmem/qfprom.txt b/dts/Bindings/nvmem/qfprom.txt
new file mode 100644
index 0000000..4ad68b7
--- /dev/null
+++ b/dts/Bindings/nvmem/qfprom.txt
@@ -0,0 +1,35 @@
+= Qualcomm QFPROM device tree bindings =
+
+This binding is intended to represent QFPROM which is found in most QCOM SOCs.
+
+Required properties:
+- compatible: should be "qcom,qfprom"
+- reg: Should contain registers location and length
+
+= Data cells =
+Are child nodes of qfprom, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+Example:
+
+ qfprom: qfprom@00700000 {
+ compatible = "qcom,qfprom";
+ reg = <0x00700000 0x8000>;
+ ...
+ /* Data cells */
+ tsens_calibration: calib@404 {
+ reg = <0x4404 0x10>;
+ };
+ };
+
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+
+ tsens {
+ ...
+ nvmem-cells = <&tsens_calibration>;
+ nvmem-cell-names = "calibration";
+ };
diff --git a/dts/Bindings/power/opp.txt b/dts/Bindings/opp/opp.txt
index 0d5e7c9..0cb44dc 100644
--- a/dts/Bindings/power/opp.txt
+++ b/dts/Bindings/opp/opp.txt
@@ -88,7 +88,7 @@ This defines voltage-current-frequency combinations along with other related
properties.
Required properties:
-- opp-hz: Frequency in Hz
+- opp-hz: Frequency in Hz, expressed as a 64-bit big-endian integer.
Optional properties:
- opp-microvolt: voltage in micro Volts.
@@ -158,20 +158,20 @@ Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states together.
opp-shared;
opp00 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000 975000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp01 {
- opp-hz = <1100000000>;
+ opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <980000 1000000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
opp02 {
- opp-hz = <1200000000>;
+ opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1025000>;
clock-latency-ns = <290000>;
turbo-mode;
@@ -237,20 +237,20 @@ independently.
*/
opp00 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000 975000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp01 {
- opp-hz = <1100000000>;
+ opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <980000 1000000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
opp02 {
- opp-hz = <1200000000>;
+ opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1025000>;
opp-microamp = <90000;
lock-latency-ns = <290000>;
@@ -313,20 +313,20 @@ DVFS state together.
opp-shared;
opp00 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000 975000 985000>;
opp-microamp = <70000>;
clock-latency-ns = <300000>;
opp-suspend;
};
opp01 {
- opp-hz = <1100000000>;
+ opp-hz = /bits/ 64 <1100000000>;
opp-microvolt = <980000 1000000 1010000>;
opp-microamp = <80000>;
clock-latency-ns = <310000>;
};
opp02 {
- opp-hz = <1200000000>;
+ opp-hz = /bits/ 64 <1200000000>;
opp-microvolt = <1025000>;
opp-microamp = <90000>;
clock-latency-ns = <290000>;
@@ -339,20 +339,20 @@ DVFS state together.
opp-shared;
opp10 {
- opp-hz = <1300000000>;
+ opp-hz = /bits/ 64 <1300000000>;
opp-microvolt = <1045000 1050000 1055000>;
opp-microamp = <95000>;
clock-latency-ns = <400000>;
opp-suspend;
};
opp11 {
- opp-hz = <1400000000>;
+ opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <1075000>;
opp-microamp = <100000>;
clock-latency-ns = <400000>;
};
opp12 {
- opp-hz = <1500000000>;
+ opp-hz = /bits/ 64 <1500000000>;
opp-microvolt = <1010000 1100000 1110000>;
opp-microamp = <95000>;
clock-latency-ns = <400000>;
@@ -379,7 +379,7 @@ Example 4: Handling multiple regulators
opp-shared;
opp00 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000>, /* Supply 0 */
<960000>, /* Supply 1 */
<960000>; /* Supply 2 */
@@ -392,7 +392,7 @@ Example 4: Handling multiple regulators
/* OR */
opp00 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000 975000 985000>, /* Supply 0 */
<960000 965000 975000>, /* Supply 1 */
<960000 965000 975000>; /* Supply 2 */
@@ -405,7 +405,7 @@ Example 4: Handling multiple regulators
/* OR */
opp00 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000 975000 985000>, /* Supply 0 */
<960000 965000 975000>, /* Supply 1 */
<960000 965000 975000>; /* Supply 2 */
@@ -437,12 +437,12 @@ Example 5: Multiple OPP tables
opp-shared;
opp00 {
- opp-hz = <600000000>;
+ opp-hz = /bits/ 64 <600000000>;
...
};
opp01 {
- opp-hz = <800000000>;
+ opp-hz = /bits/ 64 <800000000>;
...
};
};
@@ -453,12 +453,12 @@ Example 5: Multiple OPP tables
opp-shared;
opp10 {
- opp-hz = <1000000000>;
+ opp-hz = /bits/ 64 <1000000000>;
...
};
opp11 {
- opp-hz = <1100000000>;
+ opp-hz = /bits/ 64 <1100000000>;
...
};
};
diff --git a/dts/Bindings/panel/auo,b080uan01.txt b/dts/Bindings/panel/auo,b080uan01.txt
new file mode 100644
index 0000000..bae0e2b
--- /dev/null
+++ b/dts/Bindings/panel/auo,b080uan01.txt
@@ -0,0 +1,7 @@
+AU Optronics Corporation 8.0" WUXGA TFT LCD panel
+
+Required properties:
+- compatible: should be "auo,b101ean01"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/panel/lg,lg4573.txt b/dts/Bindings/panel/lg,lg4573.txt
new file mode 100644
index 0000000..824441f
--- /dev/null
+++ b/dts/Bindings/panel/lg,lg4573.txt
@@ -0,0 +1,19 @@
+LG LG4573 TFT Liquid Crystal Display with SPI control bus
+
+Required properties:
+ - compatible: "lg,lg4573"
+ - reg: address of the panel on the SPI bus
+
+The panel must obey rules for SPI slave device specified in document [1].
+
+[1]: Documentation/devicetree/bindings/spi/spi-bus.txt
+
+Example:
+
+ lcd_panel: display@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "lg,lg4573";
+ spi-max-frequency = <10000000>;
+ reg = <0>;
+ };
diff --git a/dts/Bindings/panel/nec,nl4827hc19-05b.txt b/dts/Bindings/panel/nec,nl4827hc19-05b.txt
new file mode 100644
index 0000000..8e1914d
--- /dev/null
+++ b/dts/Bindings/panel/nec,nl4827hc19-05b.txt
@@ -0,0 +1,7 @@
+NEC LCD Technologies,Ltd. WQVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "nec,nl4827hc19-05b"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/panel/okaya,rs800480t-7x0gp.txt b/dts/Bindings/panel/okaya,rs800480t-7x0gp.txt
new file mode 100644
index 0000000..ddf8e21
--- /dev/null
+++ b/dts/Bindings/panel/okaya,rs800480t-7x0gp.txt
@@ -0,0 +1,7 @@
+OKAYA Electric America, Inc. RS800480T-7X0GP 7" WVGA LCD panel
+
+Required properties:
+- compatible: should be "okaya,rs800480t-7x0gp"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/dts/Bindings/pci/ti-pci.txt b/dts/Bindings/pci/ti-pci.txt
index 3d21791..60e2516 100644
--- a/dts/Bindings/pci/ti-pci.txt
+++ b/dts/Bindings/pci/ti-pci.txt
@@ -23,6 +23,9 @@ PCIe Designware Controller
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
+Optional Property:
+ - gpios : Should be added if a gpio line is required to drive PERST# line
+
Example:
axi {
compatible = "simple-bus";
diff --git a/dts/Bindings/phy/phy-lpc18xx-usb-otg.txt b/dts/Bindings/phy/phy-lpc18xx-usb-otg.txt
new file mode 100644
index 0000000..bd61b46
--- /dev/null
+++ b/dts/Bindings/phy/phy-lpc18xx-usb-otg.txt
@@ -0,0 +1,26 @@
+NXP LPC18xx/43xx internal USB OTG PHY binding
+---------------------------------------------
+
+This file contains documentation for the internal USB OTG PHY found
+in NXP LPC18xx and LPC43xx SoCs.
+
+Required properties:
+- compatible : must be "nxp,lpc1850-usb-otg-phy"
+- clocks : must be exactly one entry
+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- #phy-cells : must be 0 for this phy
+See: Documentation/devicetree/bindings/phy/phy-bindings.txt
+
+The phy node must be a child of the creg syscon node.
+
+Example:
+creg: syscon@40043000 {
+ compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
+ reg = <0x40043000 0x1000>;
+
+ usb0_otg_phy: phy@004 {
+ compatible = "nxp,lpc1850-usb-otg-phy";
+ clocks = <&ccu1 CLK_USB0>;
+ #phy-cells = <0>;
+ };
+};
diff --git a/dts/Bindings/phy/sun4i-usb-phy.txt b/dts/Bindings/phy/sun4i-usb-phy.txt
index 16528b9..0cebf74 100644
--- a/dts/Bindings/phy/sun4i-usb-phy.txt
+++ b/dts/Bindings/phy/sun4i-usb-phy.txt
@@ -7,6 +7,8 @@ Required properties:
* allwinner,sun5i-a13-usb-phy
* allwinner,sun6i-a31-usb-phy
* allwinner,sun7i-a20-usb-phy
+ * allwinner,sun8i-a23-usb-phy
+ * allwinner,sun8i-a33-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
@@ -17,12 +19,21 @@ Required properties:
- clock-names :
* "usb_phy" for sun4i, sun5i or sun7i
* "usb0_phy", "usb1_phy" and "usb2_phy" for sun6i
+ * "usb0_phy", "usb1_phy" for sun8i
- resets : a list of phandle + reset specifier pairs
- reset-names :
* "usb0_reset"
* "usb1_reset"
* "usb2_reset" for sun4i, sun6i or sun7i
+Optional properties:
+- usb0_id_det-gpios : gpio phandle for reading the otg id pin value
+- usb0_vbus_det-gpios : gpio phandle for detecting the presence of usb0 vbus
+- usb0_vbus_power-supply: power-supply phandle for usb0 vbus presence detect
+- usb0_vbus-supply : regulator phandle for controller usb0 vbus
+- usb1_vbus-supply : regulator phandle for controller usb1 vbus
+- usb2_vbus-supply : regulator phandle for controller usb2 vbus
+
Example:
usbphy: phy@0x01c13400 {
#phy-cells = <1>;
@@ -32,6 +43,13 @@ Example:
reg-names = "phy_ctrl", "pmu1", "pmu2";
clocks = <&usb_clk 8>;
clock-names = "usb_phy";
- resets = <&usb_clk 1>, <&usb_clk 2>;
- reset-names = "usb1_reset", "usb2_reset";
+ resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
+ reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
+ usb0_id_det-gpios = <&pio 7 19 GPIO_ACTIVE_HIGH>; /* PH19 */
+ usb0_vbus_det-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+ usb2_vbus-supply = <&reg_usb2_vbus>;
};
diff --git a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
index 9462ab7..3c821cd 100644
--- a/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
+++ b/dts/Bindings/pinctrl/allwinner,sunxi-pinctrl.txt
@@ -48,7 +48,7 @@ Optional subnode-properties:
Examples:
-pinctrl@01c20800 {
+pio: pinctrl@01c20800 {
compatible = "allwinner,sun5i-a13-pinctrl";
reg = <0x01c20800 0x400>;
#address-cells = <1>;
@@ -68,3 +68,38 @@ pinctrl@01c20800 {
allwinner,pull = <0>;
};
};
+
+
+GPIO and interrupt controller
+-----------------------------
+
+This hardware also acts as a GPIO controller and an interrupt
+controller.
+
+Consumers that would want to refer to one or the other (or both)
+should provide through the usual *-gpios and interrupts properties a
+cell with 3 arguments, first the number of the bank, then the pin
+inside that bank, and finally the flags for the GPIO/interrupts.
+
+Example:
+
+xio: gpio@38 {
+ compatible = "nxp,pcf8574a";
+ reg = <0x38>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-parent = <&pio>;
+ interrupts = <6 0 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
+reg_usb1_vbus: usb1-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>;
+};
diff --git a/dts/Bindings/pinctrl/cnxt,cx92755-pinctrl.txt b/dts/Bindings/pinctrl/cnxt,cx92755-pinctrl.txt
new file mode 100644
index 0000000..23ce8dc
--- /dev/null
+++ b/dts/Bindings/pinctrl/cnxt,cx92755-pinctrl.txt
@@ -0,0 +1,86 @@
+Conexant Digicolor CX92755 General Purpose Pin Mapping
+
+This document describes the device tree binding of the pin mapping hardware
+modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
+Digicolor series of SoCs.
+
+=== Pin Controller Node ===
+
+Required Properties:
+
+- compatible: Must be "cnxt,cx92755-pinctrl"
+- reg: Base address of the General Purpose Pin Mapping register block and the
+ size of the block.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Must be <2>. The first cell is the pin number and the
+ second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
+ for possible values.
+
+For example, the following is the bare minimum node:
+
+ pinctrl: pinctrl@f0000e20 {
+ compatible = "cnxt,cx92755-pinctrl";
+ reg = <0xf0000e20 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+As a pin controller device, in addition to the required properties, this node
+should also contain the pin configuration nodes that client devices reference,
+if any.
+
+For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
+
+=== Pin Configuration Node ===
+
+Each pin configuration node is a sub-node of the pin controller node and is a
+container of an arbitrary number of subnodes, called pin group nodes in this
+document.
+
+Please refer to the pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the definition of a
+"pin configuration node".
+
+=== Pin Group Node ===
+
+A pin group node specifies the desired pin mux for an arbitrary number of
+pins. The name of the pin group node is optional and not used.
+
+A pin group node only affects the properties specified in the node, and has no
+effect on any properties that are omitted.
+
+The pin group node accepts a subset of the generic pin config properties. For
+details generic pin config properties, please refer to pinctrl-bindings.txt
+and <include/linux/pinctrl/pinconfig-generic.h>.
+
+Required Pin Group Node Properties:
+
+- pins: Multiple strings. Specifies the name(s) of one or more pins to be
+ configured by this node. The format of a pin name string is "GP_xy", where x
+ is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
+- function: String. Specifies the pin mux selection. Values must be one of:
+ "gpio", "client_a", "client_b", "client_c"
+
+Example:
+ pinctrl: pinctrl@f0000e20 {
+ compatible = "cnxt,cx92755-pinctrl";
+ reg = <0xf0000e20 0x100>;
+
+ uart0_default: uart0_active {
+ data_signals {
+ pins = "GP_O0", "GP_O1";
+ function = "client_b";
+ };
+ };
+ };
+
+ uart0: uart@f0000740 {
+ compatible = "cnxt,cx92755-usart";
+ ...
+ pinctrl-0 = <&uart0_default>;
+ pinctrl-names = "default";
+ };
+
+In the example above, a single pin group configuration node defines the
+"client select" for the Rx and Tx signals of uart0. The uart0 node references
+that pin configuration node using the &uart0_default phandle.
diff --git a/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt b/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt
new file mode 100644
index 0000000..a81bbf3
--- /dev/null
+++ b/dts/Bindings/pinctrl/fsl,imx6ul-pinctrl.txt
@@ -0,0 +1,36 @@
+* Freescale i.MX6 UltraLite IOMUX Controller
+
+Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
+and usage.
+
+Required properties:
+- compatible: "fsl,imx6ul-iomuxc"
+- fsl,pins: each entry consists of 6 integers and represents the mux and config
+ setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
+ input_val> are specified using a PIN_FUNC_ID macro, which can be found in
+ imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is
+ the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite
+ Reference Manual for detailed CONFIG settings.
+
+CONFIG bits definition:
+PAD_CTL_HYS (1 << 16)
+PAD_CTL_PUS_100K_DOWN (0 << 14)
+PAD_CTL_PUS_47K_UP (1 << 14)
+PAD_CTL_PUS_100K_UP (2 << 14)
+PAD_CTL_PUS_22K_UP (3 << 14)
+PAD_CTL_PUE (1 << 13)
+PAD_CTL_PKE (1 << 12)
+PAD_CTL_ODE (1 << 11)
+PAD_CTL_SPEED_LOW (0 << 6)
+PAD_CTL_SPEED_MED (1 << 6)
+PAD_CTL_SPEED_HIGH (3 << 6)
+PAD_CTL_DSE_DISABLE (0 << 3)
+PAD_CTL_DSE_260ohm (1 << 3)
+PAD_CTL_DSE_130ohm (2 << 3)
+PAD_CTL_DSE_87ohm (3 << 3)
+PAD_CTL_DSE_65ohm (4 << 3)
+PAD_CTL_DSE_52ohm (5 << 3)
+PAD_CTL_DSE_43ohm (6 << 3)
+PAD_CTL_DSE_37ohm (7 << 3)
+PAD_CTL_SRE_FAST (1 << 0)
+PAD_CTL_SRE_SLOW (0 << 0)
diff --git a/dts/Bindings/pinctrl/qcom,pmic-mpp.txt b/dts/Bindings/pinctrl/qcom,pmic-mpp.txt
index ed19991..d7803a2 100644
--- a/dts/Bindings/pinctrl/qcom,pmic-mpp.txt
+++ b/dts/Bindings/pinctrl/qcom,pmic-mpp.txt
@@ -7,8 +7,13 @@ of PMIC's from Qualcomm.
Usage: required
Value type: <string>
Definition: Should contain one of:
+ "qcom,pm8018-mpp",
+ "qcom,pm8038-mpp",
+ "qcom,pm8821-mpp",
"qcom,pm8841-mpp",
"qcom,pm8916-mpp",
+ "qcom,pm8917-mpp",
+ "qcom,pm8921-mpp",
"qcom,pm8941-mpp",
"qcom,pma8084-mpp",
@@ -77,12 +82,9 @@ to specify in a pin configuration subnode:
Value type: <string>
Definition: Specify the alternative function to be configured for the
specified pins. Valid values are:
- "normal",
- "paired",
- "dtest1",
- "dtest2",
- "dtest3",
- "dtest4"
+ "digital",
+ "analog",
+ "sink"
- bias-disable:
Usage: optional
@@ -127,12 +129,18 @@ to specify in a pin configuration subnode:
Definition: Selects the power source for the specified pins. Valid power
sources are defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
-- qcom,analog-mode:
+- qcom,analog-level:
Usage: optional
- Value type: <none>
- Definition: Selects Analog mode of operation: combined with input-enable
- and/or output-high, output-low MPP could operate as
- Bidirectional Logic, Analog Input, Analog Output.
+ Value type: <u32>
+ Definition: Selects the source for analog output. Valued values are
+ defined in <dt-binding/pinctrl/qcom,pmic-mpp.h>
+ PMIC_MPP_AOUT_LVL_*
+
+- qcom,dtest:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects which dtest rail to be routed in the various functions.
+ Valid values are 1-4
- qcom,amux-route:
Usage: optional
@@ -140,6 +148,10 @@ to specify in a pin configuration subnode:
Definition: Selects the source for analog input. Valid values are
defined in <dt-bindings/pinctrl/qcom,pmic-mpp.h>
PMIC_MPP_AMUX_ROUTE_CH5, PMIC_MPP_AMUX_ROUTE_CH6...
+- qcom,paired:
+ Usage: optional
+ Value type: <none>
+ Definition: Indicates that the pin should be operating in paired mode.
Example:
@@ -156,7 +168,7 @@ Example:
pm8841_default: default {
gpio {
pins = "mpp1", "mpp2", "mpp3", "mpp4";
- function = "normal";
+ function = "digital";
input-enable;
power-source = <PM8841_MPP_S3>;
};
diff --git a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
index 51cee44..9496934 100644
--- a/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
+++ b/dts/Bindings/pinctrl/renesas,pfc-pinctrl.txt
@@ -58,12 +58,12 @@ are parsed through phandles and processed purely based on their content.
Pin Configuration Node Properties:
-- renesas,pins : An array of strings, each string containing the name of a pin.
-- renesas,groups : An array of strings, each string containing the name of a pin
+- pins : An array of strings, each string containing the name of a pin.
+- groups : An array of strings, each string containing the name of a pin
group.
-- renesas,function: A string containing the name of the function to mux to the
- pin group(s) specified by the renesas,groups property
+- function: A string containing the name of the function to mux to the pin
+ group(s) specified by the groups property.
Valid values for pin, group and function names can be found in the group and
function arrays of the PFC data file corresponding to the SoC
@@ -71,7 +71,9 @@ Pin Configuration Node Properties:
The pin configuration parameters use the generic pinconf bindings defined in
pinctrl-bindings.txt in this directory. The supported parameters are
-bias-disable, bias-pull-up and bias-pull-down.
+bias-disable, bias-pull-up, bias-pull-down and power-source. For pins that
+have a configurable I/O voltage, the power-source value should be the
+nominal I/O voltage in millivolts.
GPIO
@@ -141,19 +143,19 @@ Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps
mmcif_pins: mmcif {
mux {
- renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
- renesas,function = "mmc0";
+ groups = "mmc0_data8_0", "mmc0_ctrl_0";
+ function = "mmc0";
};
cfg {
- renesas,groups = "mmc0_data8_0";
- renesas,pins = "PORT279";
+ groups = "mmc0_data8_0";
+ pins = "PORT279";
bias-pull-up;
};
};
scifa4_pins: scifa4 {
- renesas,groups = "scifa4_data", "scifa4_ctrl";
- renesas,function = "scifa4";
+ groups = "scifa4_data", "scifa4_ctrl";
+ function = "scifa4";
};
};
diff --git a/dts/Bindings/pinctrl/ste,nomadik.txt b/dts/Bindings/pinctrl/ste,nomadik.txt
index f63fcb3..2213802 100644
--- a/dts/Bindings/pinctrl/ste,nomadik.txt
+++ b/dts/Bindings/pinctrl/ste,nomadik.txt
@@ -3,7 +3,9 @@ ST Ericsson Nomadik pinmux controller
Required properties:
- compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
"stericsson,stn8815-pinctrl"
-- reg: Should contain the register physical address and length of the PRCMU.
+- nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
+ (these have the register ranges used by the pin controller).
+- prcm: phandle to the PRCMU managing the back end of this pin controller
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
@@ -74,7 +76,8 @@ Example board file extract:
pinctrl@80157000 {
compatible = "stericsson,db8500-pinctrl";
- reg = <0x80157000 0x2000>;
+ nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>;
+ prcm = <&prcmu>;
pinctrl-names = "default";
diff --git a/dts/Bindings/power/power_domain.txt b/dts/Bindings/power/power_domain.txt
index 0f8ed37..025b5e7 100644
--- a/dts/Bindings/power/power_domain.txt
+++ b/dts/Bindings/power/power_domain.txt
@@ -48,7 +48,7 @@ Example 2:
#power-domain-cells = <1>;
};
- child: power-controller@12340000 {
+ child: power-controller@12341000 {
compatible = "foo,power-controller";
reg = <0x12341000 0x1000>;
power-domains = <&parent 0>;
diff --git a/dts/Bindings/power/qcom,coincell-charger.txt b/dts/Bindings/power/qcom,coincell-charger.txt
new file mode 100644
index 0000000..0e6d875
--- /dev/null
+++ b/dts/Bindings/power/qcom,coincell-charger.txt
@@ -0,0 +1,48 @@
+Qualcomm Coincell Charger:
+
+The hardware block controls charging for a coincell or capacitor that is
+used to provide power backup for certain features of the power management
+IC (PMIC)
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be: "qcom,pm8941-coincell"
+
+- reg:
+ Usage: required
+ Value type: <u32>
+ Definition: base address of the coincell charger registers
+
+- qcom,rset-ohms:
+ Usage: required
+ Value type: <u32>
+ Definition: resistance (in ohms) for current-limiting resistor
+ must be one of: 800, 1200, 1700, 2100
+
+- qcom,vset-millivolts:
+ Usage: required
+ Value type: <u32>
+ Definition: voltage (in millivolts) to apply for charging
+ must be one of: 2500, 3000, 3100, 3200
+
+- qcom,charger-disable:
+ Usage: optional
+ Value type: <boolean>
+ Definition: definining this property disables charging
+
+This charger is a sub-node of one of the 8941 PMIC blocks, and is specified
+as a child node in DTS of that node. See ../mfd/qcom,spmi-pmic.txt and
+../mfd/qcom-pm8xxx.txt
+
+Example:
+
+ pm8941@0 {
+ coincell@2800 {
+ compatible = "qcom,pm8941-coincell";
+ reg = <0x2800>;
+
+ qcom,rset-ohms = <2100>;
+ qcom,vset-millivolts = <3000>;
+ };
+ };
diff --git a/dts/Bindings/power/rockchip-io-domain.txt b/dts/Bindings/power/rockchip-io-domain.txt
index 8b70db1..b8627e7 100644
--- a/dts/Bindings/power/rockchip-io-domain.txt
+++ b/dts/Bindings/power/rockchip-io-domain.txt
@@ -33,6 +33,8 @@ Required properties:
- compatible: should be one of:
- "rockchip,rk3188-io-voltage-domain" for rk3188
- "rockchip,rk3288-io-voltage-domain" for rk3288
+ - "rockchip,rk3368-io-voltage-domain" for rk3368
+ - "rockchip,rk3368-pmu-io-voltage-domain" for rk3368 pmu-domains
- rockchip,grf: phandle to the syscon managing the "general register files"
@@ -64,6 +66,18 @@ Possible supplies for rk3288:
- sdcard-supply: The supply connected to SDMMC0_VDD.
- wifi-supply: The supply connected to APIO3_VDD. Also known as SDIO0.
+Possible supplies for rk3368:
+- audio-supply: The supply connected to APIO3_VDD.
+- dvp-supply: The supply connected to DVPIO_VDD.
+- flash0-supply: The supply connected to FLASH0_VDD. Typically for eMMC
+- gpio30-supply: The supply connected to APIO1_VDD.
+- gpio1830 The supply connected to APIO4_VDD.
+- sdcard-supply: The supply connected to SDMMC0_VDD.
+- wifi-supply: The supply connected to APIO2_VDD. Also known as SDIO0.
+
+Possible supplies for rk3368 pmu-domains:
+- pmu-supply: The supply connected to PMUIO_VDD.
+- vop-supply: The supply connected to LCDC_VDD.
Example:
diff --git a/dts/Bindings/powerpc/fsl/mpc5121-psc.txt b/dts/Bindings/powerpc/fsl/mpc5121-psc.txt
index 8832e87..6478175 100644
--- a/dts/Bindings/powerpc/fsl/mpc5121-psc.txt
+++ b/dts/Bindings/powerpc/fsl/mpc5121-psc.txt
@@ -6,14 +6,14 @@ PSC in UART mode
For PSC in UART mode the needed PSC serial devices
are specified by fsl,mpc5121-psc-uart nodes in the
fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
-Controller node fsl,mpc5121-psc-fifo is requered there:
+Controller node fsl,mpc5121-psc-fifo is required there:
-fsl,mpc5121-psc-uart nodes
+fsl,mpc512x-psc-uart nodes
--------------------------
Required properties :
- - compatible : Should contain "fsl,mpc5121-psc-uart" and "fsl,mpc5121-psc"
- - cell-index : Index of the PSC in hardware
+ - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
+ Supported <soc>s: mpc5121, mpc5125
- reg : Offset and length of the register set for the PSC device
- interrupts : <a b> where a is the interrupt number of the
PSC FIFO Controller and b is a field that represents an
@@ -25,12 +25,21 @@ Recommended properties :
- fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
- fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
+PSC in SPI mode
+---------------
-fsl,mpc5121-psc-fifo node
+Similar to the UART mode a PSC can be operated in SPI mode. The compatible used
+for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
+The required and recommended properties are identical to the
+fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible
+string.
+
+fsl,mpc512x-psc-fifo node
-------------------------
Required properties :
- - compatible : Should be "fsl,mpc5121-psc-fifo"
+ - compatible : Should be "fsl,<soc>-psc-fifo"
+ Supported <soc>s: mpc5121, mpc5125
- reg : Offset and length of the register set for the PSC
FIFO Controller
- interrupts : <a b> where a is the interrupt number of the
@@ -39,6 +48,9 @@ Required properties :
- interrupt-parent : the phandle for the interrupt controller that
services interrupts for this device.
+Recommended properties :
+ - clocks : specifies the clock needed to operate the fifo controller
+ - clock-names : name(s) for the clock(s) listed in clocks
Example for a board using PSC0 and PSC1 devices in serial mode:
diff --git a/dts/Bindings/powerpc/fsl/scfg.txt b/dts/Bindings/powerpc/fsl/scfg.txt
new file mode 100644
index 0000000..0532c46
--- /dev/null
+++ b/dts/Bindings/powerpc/fsl/scfg.txt
@@ -0,0 +1,18 @@
+Freescale Supplement configuration unit (SCFG)
+
+SCFG is the supplemental configuration unit, that provides SoC specific
+configuration and status registers for the chip. Such as getting PEX port
+status.
+
+Required properties:
+
+- compatible: should be "fsl,<chip>-scfg"
+- reg: should contain base address and length of SCFG memory-mapped
+registers
+
+Example:
+
+ scfg: global-utilities@fc000 {
+ compatible = "fsl,t1040-scfg";
+ reg = <0xfc000 0x1000>;
+ };
diff --git a/dts/Bindings/pwm/lpc1850-sct-pwm.txt b/dts/Bindings/pwm/lpc1850-sct-pwm.txt
new file mode 100644
index 0000000..36e49d4
--- /dev/null
+++ b/dts/Bindings/pwm/lpc1850-sct-pwm.txt
@@ -0,0 +1,20 @@
+* NXP LPC18xx State Configurable Timer - Pulse Width Modulator driver
+
+Required properties:
+ - compatible: Should be "nxp,lpc1850-sct-pwm"
+ - reg: Should contain physical base address and length of pwm registers.
+ - clocks: Must contain an entry for each entry in clock-names.
+ See ../clock/clock-bindings.txt for details.
+ - clock-names: Must include the following entries.
+ - pwm: PWM operating clock.
+ - #pwm-cells: Should be 3. See pwm.txt in this directory for the description
+ of the cells format.
+
+Example:
+ pwm: pwm@40000000 {
+ compatible = "nxp,lpc1850-sct-pwm";
+ reg = <0x40000000 0x1000>;
+ clocks =<&ccu1 CLK_CPU_SCT>;
+ clock-names = "pwm";
+ #pwm-cells = <3>;
+ };
diff --git a/dts/Bindings/regulator/da9210.txt b/dts/Bindings/regulator/da9210.txt
index 3297c53..7aa9b1f 100644
--- a/dts/Bindings/regulator/da9210.txt
+++ b/dts/Bindings/regulator/da9210.txt
@@ -5,6 +5,10 @@ Required properties:
- compatible: must be "dlg,da9210"
- reg: the i2c slave address of the regulator. It should be 0x68.
+Optional properties:
+
+- interrupts: a reference to the DA9210 interrupt, if available.
+
Any standard regulator properties can be used to configure the single da9210
DCDC.
diff --git a/dts/Bindings/regulator/da9211.txt b/dts/Bindings/regulator/da9211.txt
index eb61890..c620493 100644
--- a/dts/Bindings/regulator/da9211.txt
+++ b/dts/Bindings/regulator/da9211.txt
@@ -1,7 +1,7 @@
-* Dialog Semiconductor DA9211/DA9213 Voltage Regulator
+* Dialog Semiconductor DA9211/DA9213/DA9215 Voltage Regulator
Required properties:
-- compatible: "dlg,da9211" or "dlg,da9213".
+- compatible: "dlg,da9211" or "dlg,da9213" or "dlg,da9215"
- reg: I2C slave address, usually 0x68.
- interrupts: the interrupt outputs of the controller
- regulators: A node that houses a sub-node for each regulator within the
@@ -66,3 +66,31 @@ Example 2) DA9213
};
};
};
+
+
+Example 3) DA9215
+ pmic: da9215@68 {
+ compatible = "dlg,da9215";
+ reg = <0x68>;
+ interrupts = <3 27>;
+
+ regulators {
+ BUCKA {
+ regulator-name = "VBUCKA";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <4000000>;
+ regulator-max-microamp = <7000000>;
+ enable-gpios = <&gpio 27 0>;
+ };
+ BUCKB {
+ regulator-name = "VBUCKB";
+ regulator-min-microvolt = < 300000>;
+ regulator-max-microvolt = <1570000>;
+ regulator-min-microamp = <4000000>;
+ regulator-max-microamp = <7000000>;
+ enable-gpios = <&gpio 17 0>;
+ };
+ };
+ };
+
diff --git a/dts/Bindings/regulator/max77686.txt b/dts/Bindings/regulator/max77686.txt
new file mode 100644
index 0000000..0dded64
--- /dev/null
+++ b/dts/Bindings/regulator/max77686.txt
@@ -0,0 +1,71 @@
+Binding for Maxim MAX77686 regulators
+
+This is a part of the device tree bindings of MAX77686 multi-function device.
+More information can be found in ../mfd/max77686.txt file.
+
+The MAX77686 PMIC has 9 high-efficiency Buck and 26 Low-DropOut (LDO)
+regulators that can be controlled over I2C.
+
+Following properties should be present in main device node of the MFD chip.
+
+Optional node:
+- voltage-regulators : The regulators of max77686 have to be instantiated
+ under subnode named "voltage-regulators" using the following format.
+
+ regulator_name {
+ regulator-compatible = LDOn/BUCKn
+ standard regulator constraints....
+ };
+ refer Documentation/devicetree/bindings/regulator/regulator.txt
+
+ The regulator node's name should be initialized with a string
+to get matched with their hardware counterparts as follow:
+
+ -LDOn : for LDOs, where n can lie in range 1 to 26.
+ example: LDO1, LDO2, LDO26.
+ -BUCKn : for BUCKs, where n can lie in range 1 to 9.
+ example: BUCK1, BUCK5, BUCK9.
+
+ Regulators which can be turned off during system suspend:
+ -LDOn : 2, 6-8, 10-12, 14-16,
+ -BUCKn : 1-4.
+ Use standard regulator bindings for it ('regulator-off-in-suspend').
+
+ LDO20, LDO21, LDO22, BUCK8 and BUCK9 can be configured to GPIO enable
+ control. To turn this feature on this property must be added to the regulator
+ sub-node:
+ - maxim,ena-gpios : one GPIO specifier enable control (the gpio
+ flags are actually ignored and always
+ ACTIVE_HIGH is used)
+
+Example:
+
+ max77686: pmic@09 {
+ compatible = "maxim,max77686";
+ interrupt-parent = <&wakeup_eint>;
+ interrupts = <26 IRQ_TYPE_NONE>;
+ reg = <0x09>;
+
+ voltage-regulators {
+ ldo11_reg: LDO11 {
+ regulator-name = "vdd_ldo11";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <1900000>;
+ regulator-always-on;
+ };
+
+ buck1_reg: BUCK1 {
+ regulator-name = "vdd_mif";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ buck9_reg: BUCK9 {
+ regulator-name = "CAM_ISP_CORE_1.2V";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1200000>;
+ maxim,ena-gpios = <&gpm0 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
diff --git a/dts/Bindings/regulator/max8973-regulator.txt b/dts/Bindings/regulator/max8973-regulator.txt
index 55efb24..f80ea2f 100644
--- a/dts/Bindings/regulator/max8973-regulator.txt
+++ b/dts/Bindings/regulator/max8973-regulator.txt
@@ -25,6 +25,12 @@ Optional properties:
-maxim,enable-frequency-shift: boolean, enable 9% frequency shift.
-maxim,enable-bias-control: boolean, enable bias control. By enabling this
startup delay can be reduce to 20us from 220us.
+-maxim,enable-etr: boolean, enable Enhanced Transient Response.
+-maxim,enable-high-etr-sensitivity: boolean, Enhanced transient response
+ circuit is enabled and set for high sensitivity. If this
+ property is available then etr will be enable default.
+
+Enhanced transient response (ETR) will affect the configuration of CKADV.
Example:
diff --git a/dts/Bindings/regulator/mt6311-regulator.txt b/dts/Bindings/regulator/mt6311-regulator.txt
new file mode 100644
index 0000000..02649d8
--- /dev/null
+++ b/dts/Bindings/regulator/mt6311-regulator.txt
@@ -0,0 +1,35 @@
+Mediatek MT6311 Regulator Driver
+
+Required properties:
+- compatible: "mediatek,mt6311-regulator"
+- reg: I2C slave address, usually 0x6b.
+- regulators: List of regulators provided by this controller. It is named
+ to VDVFS and VBIASN.
+ The definition for each of these nodes is defined using the standard binding
+ for regulators at Documentation/devicetree/bindings/regulator/regulator.txt.
+
+The valid names for regulators are:
+BUCK:
+ VDVFS
+LDO:
+ VBIASN
+
+Example:
+ mt6311: pmic@6b {
+ compatible = "mediatek,mt6311-regulator";
+ reg = <0x6b>;
+
+ regulators {
+ mt6311_vcpu_reg: VDVFS {
+ regulator-name = "VDVFS";
+ regulator-min-microvolt = < 600000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-ramp-delay = <10000>;
+ };
+ mt6311_ldo_reg: VBIASN {
+ regulator-name = "VBIASN";
+ regulator-min-microvolt = <200000>;
+ regulator-max-microvolt = <800000>;
+ };
+ };
+ };
diff --git a/dts/Bindings/regulator/pwm-regulator.txt b/dts/Bindings/regulator/pwm-regulator.txt
index ce91f61..ed936f0 100644
--- a/dts/Bindings/regulator/pwm-regulator.txt
+++ b/dts/Bindings/regulator/pwm-regulator.txt
@@ -1,27 +1,68 @@
-pwm regulator bindings
+Bindings for the Generic PWM Regulator
+======================================
+
+Currently supports 2 modes of operation:
+
+Voltage Table: When in this mode, a voltage table (See below) of
+ predefined voltage <=> duty-cycle values must be
+ provided via DT. Limitations are that the regulator can
+ only operate at the voltages supplied in the table.
+ Intermediary duty-cycle values which would normally
+ allow finer grained voltage selection are ignored and
+ rendered useless. Although more control is given to
+ the user if the assumptions made in continuous-voltage
+ mode do not reign true.
+
+Continuous Voltage: This mode uses the regulator's maximum and minimum
+ supplied voltages specified in the
+ regulator-{min,max}-microvolt properties to calculate
+ appropriate duty-cycle values. This allows for a much
+ more fine grained solution when compared with
+ voltage-table mode above. This solution does make an
+ assumption that a %50 duty-cycle value will cause the
+ regulator voltage to run at half way between the
+ supplied max_uV and min_uV values.
Required properties:
-- compatible: Should be "pwm-regulator"
-- pwms: OF device-tree PWM specification (see PWM binding pwm.txt)
-- voltage-table: voltage and duty table, include 2 members in each set of
- brackets, first one is voltage(unit: uv), the next is duty(unit: percent)
+--------------------
+- compatible: Should be "pwm-regulator"
+
+- pwms: PWM specification (See: ../pwm/pwm.txt)
+
+Only required for Voltage Table Mode:
+- voltage-table: Voltage and Duty-Cycle table consisting of 2 cells
+ First cell is voltage in microvolts (uV)
+ Second cell is duty-cycle in percent (%)
+
+NB: To be clear, if voltage-table is provided, then the device will be used
+in Voltage Table Mode. If no voltage-table is provided, then the device will
+be used in Continuous Voltage Mode.
-Any property defined as part of the core regulator binding defined in
-regulator.txt can also be used.
+Any property defined as part of the core regulator binding can also be used.
+(See: ../regulator/regulator.txt)
-Example:
+Continuous Voltage Example:
pwm_regulator {
compatible = "pwm-regulator;
pwms = <&pwm1 0 8448 0>;
+ regulator-min-microvolt = <1016000>;
+ regulator-max-microvolt = <1114000>;
+ regulator-name = "vdd_logic";
+ };
+Voltage Table Example:
+ pwm_regulator {
+ compatible = "pwm-regulator;
+ pwms = <&pwm1 0 8448 0>;
+ regulator-min-microvolt = <1016000>;
+ regulator-max-microvolt = <1114000>;
+ regulator-name = "vdd_logic";
+
+ /* Voltage Duty-Cycle */
voltage-table = <1114000 0>,
<1095000 10>,
<1076000 20>,
<1056000 30>,
<1036000 40>,
<1016000 50>;
-
- regulator-min-microvolt = <1016000>;
- regulator-max-microvolt = <1114000>;
- regulator-name = "vdd_logic";
};
diff --git a/dts/Bindings/regulator/qcom,spmi-regulator.txt b/dts/Bindings/regulator/qcom,spmi-regulator.txt
index 75b4604..d00bfd8 100644
--- a/dts/Bindings/regulator/qcom,spmi-regulator.txt
+++ b/dts/Bindings/regulator/qcom,spmi-regulator.txt
@@ -91,13 +91,65 @@ see regulator.txt - with additional custom properties described below:
- regulator-initial-mode:
Usage: optional
Value type: <u32>
- Descrption: 1 = Set initial mode to high power mode (HPM), also referred
- to as NPM. HPM consumes more ground current than LPM, but
+ Description: 2 = Set initial mode to auto mode (automatically select
+ between HPM and LPM); not available on boost type
+ regulators.
+
+ 1 = Set initial mode to high power mode (HPM), also referred
+ to as NPM. HPM consumes more ground current than LPM, but
it can source significantly higher load current. HPM is not
available on boost type regulators. For voltage switch type
regulators, HPM implies that over current protection and
- soft start are active all the time. 0 = Set initial mode to
- low power mode (LPM).
+ soft start are active all the time.
+
+ 0 = Set initial mode to low power mode (LPM).
+
+- qcom,ocp-max-retries:
+ Usage: optional
+ Value type: <u32>
+ Description: Maximum number of times to try toggling a voltage switch
+ off and back on as a result of consecutive over current
+ events.
+
+- qcom,ocp-retry-delay:
+ Usage: optional
+ Value type: <u32>
+ Description: Time to delay in milliseconds between each voltage switch
+ toggle after an over current event takes place.
+
+- qcom,pin-ctrl-enable:
+ Usage: optional
+ Value type: <u32>
+ Description: Bit mask specifying which hardware pins should be used to
+ enable the regulator, if any; supported bits are:
+ 0 = ignore all hardware enable signals
+ BIT(0) = follow HW0_EN signal
+ BIT(1) = follow HW1_EN signal
+ BIT(2) = follow HW2_EN signal
+ BIT(3) = follow HW3_EN signal
+
+- qcom,pin-ctrl-hpm:
+ Usage: optional
+ Value type: <u32>
+ Description: Bit mask specifying which hardware pins should be used to
+ force the regulator into high power mode, if any;
+ supported bits are:
+ 0 = ignore all hardware enable signals
+ BIT(0) = follow HW0_EN signal
+ BIT(1) = follow HW1_EN signal
+ BIT(2) = follow HW2_EN signal
+ BIT(3) = follow HW3_EN signal
+ BIT(4) = follow PMIC awake state
+
+- qcom,vs-soft-start-strength:
+ Usage: optional
+ Value type: <u32>
+ Description: This property sets the soft start strength for voltage
+ switch type regulators; supported values are:
+ 0 = 0.05 uA
+ 1 = 0.25 uA
+ 2 = 0.55 uA
+ 3 = 0.75 uA
Example:
diff --git a/dts/Bindings/regulator/regulator.txt b/dts/Bindings/regulator/regulator.txt
index db88feb..24bd422 100644
--- a/dts/Bindings/regulator/regulator.txt
+++ b/dts/Bindings/regulator/regulator.txt
@@ -42,6 +42,7 @@ Optional properties:
- regulator-system-load: Load in uA present on regulator that is not captured by
any consumer request.
- regulator-pull-down: Enable pull down resistor when the regulator is disabled.
+- regulator-over-current-protection: Enable over current protection.
Deprecated properties:
- regulator-compatible: If a regulator chip contains multiple
diff --git a/dts/Bindings/reset/ath79-reset.txt b/dts/Bindings/reset/ath79-reset.txt
new file mode 100644
index 0000000..4c56330
--- /dev/null
+++ b/dts/Bindings/reset/ath79-reset.txt
@@ -0,0 +1,20 @@
+Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required Properties:
+- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
+ as fallback
+- reg: Base address and size of the controllers memory area
+- #reset-cells : Specifies the number of cells needed to encode reset
+ line, should be 1
+
+Example:
+
+ reset-controller@1806001c {
+ compatible = "qca,ar9132-reset", "qca,ar7100-reset";
+ reg = <0x1806001c 0x4>;
+
+ #reset-cells = <1>;
+ };
diff --git a/dts/Bindings/reset/nxp,lpc1850-rgu.txt b/dts/Bindings/reset/nxp,lpc1850-rgu.txt
new file mode 100644
index 0000000..b4e96a2
--- /dev/null
+++ b/dts/Bindings/reset/nxp,lpc1850-rgu.txt
@@ -0,0 +1,84 @@
+NXP LPC1850 Reset Generation Unit (RGU)
+========================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+Required properties:
+- compatible: Should be "nxp,lpc1850-rgu"
+- reg: register base and length
+- clocks: phandle and clock specifier to RGU clocks
+- clock-names: should contain "delay" and "reg"
+- #reset-cells: should be 1
+
+See table below for valid peripheral reset numbers. Numbers not
+in the table below are either reserved or not applicable for
+normal operation.
+
+Reset Peripheral
+ 9 System control unit (SCU)
+ 12 ARM Cortex-M0 subsystem core (LPC43xx only)
+ 13 CPU core
+ 16 LCD controller
+ 17 USB0
+ 18 USB1
+ 19 DMA
+ 20 SDIO
+ 21 External memory controller (EMC)
+ 22 Ethernet
+ 25 Flash bank A
+ 27 EEPROM
+ 28 GPIO
+ 29 Flash bank B
+ 32 Timer0
+ 33 Timer1
+ 34 Timer2
+ 35 Timer3
+ 36 Repetitive Interrupt timer (RIT)
+ 37 State Configurable Timer (SCT)
+ 38 Motor control PWM (MCPWM)
+ 39 QEI
+ 40 ADC0
+ 41 ADC1
+ 42 DAC
+ 44 USART0
+ 45 UART1
+ 46 USART2
+ 47 USART3
+ 48 I2C0
+ 49 I2C1
+ 50 SSP0
+ 51 SSP1
+ 52 I2S0 and I2S1
+ 53 Serial Flash Interface (SPIFI)
+ 54 C_CAN1
+ 55 C_CAN0
+ 56 ARM Cortex-M0 application core (LPC4370 only)
+ 57 SGPIO (LPC43xx only)
+ 58 SPI (LPC43xx only)
+ 60 ADCHS (12-bit ADC) (LPC4370 only)
+
+Refer to NXP LPC18xx or LPC43xx user manual for more details about
+the reset signals and the connected block/peripheral.
+
+Reset provider example:
+rgu: reset-controller@40053000 {
+ compatible = "nxp,lpc1850-rgu";
+ reg = <0x40053000 0x1000>;
+ clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
+ clock-names = "delay", "reg";
+ #reset-cells = <1>;
+};
+
+Reset consumer example:
+mac: ethernet@40010000 {
+ compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
+ reg = <0x40010000 0x2000>;
+ interrupts = <5>;
+ interrupt-names = "macirq";
+ clocks = <&ccu1 CLK_CPU_ETHERNET>;
+ clock-names = "stmmaceth";
+ resets = <&rgu 22>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+};
diff --git a/dts/Bindings/reset/socfpga-reset.txt b/dts/Bindings/reset/socfpga-reset.txt
index 32c1c8b..98c9f56 100644
--- a/dts/Bindings/reset/socfpga-reset.txt
+++ b/dts/Bindings/reset/socfpga-reset.txt
@@ -3,6 +3,7 @@ Altera SOCFPGA Reset Manager
Required properties:
- compatible : "altr,rst-mgr"
- reg : Should contain 1 register ranges(address and length)
+- altr,modrst-offset : Should contain the offset of the first modrst register.
- #reset-cells: 1
Example:
@@ -10,4 +11,5 @@ Example:
#reset-cells = <1>;
compatible = "altr,rst-mgr";
reg = <0xffd05000 0x1000>;
+ altr,modrst-offset = <0x10>;
};
diff --git a/dts/Bindings/reset/st,sti-picophyreset.txt b/dts/Bindings/reset/st,sti-picophyreset.txt
index 54ae9f7..9ca2776 100644
--- a/dts/Bindings/reset/st,sti-picophyreset.txt
+++ b/dts/Bindings/reset/st,sti-picophyreset.txt
@@ -39,4 +39,4 @@ Example:
};
Macro definitions for the supported reset channels can be found in:
-include/dt-bindings/reset-controller/stih407-resets.h
+include/dt-bindings/reset/stih407-resets.h
diff --git a/dts/Bindings/reset/st,sti-powerdown.txt b/dts/Bindings/reset/st,sti-powerdown.txt
index 5ab26b7..1cfd21d 100644
--- a/dts/Bindings/reset/st,sti-powerdown.txt
+++ b/dts/Bindings/reset/st,sti-powerdown.txt
@@ -43,5 +43,5 @@ example:
Macro definitions for the supported reset channels can be found in:
-include/dt-bindings/reset-controller/stih415-resets.h
-include/dt-bindings/reset-controller/stih416-resets.h
+include/dt-bindings/reset/stih415-resets.h
+include/dt-bindings/reset/stih416-resets.h
diff --git a/dts/Bindings/reset/st,sti-softreset.txt b/dts/Bindings/reset/st,sti-softreset.txt
index a8d3d3c..891a2fd 100644
--- a/dts/Bindings/reset/st,sti-softreset.txt
+++ b/dts/Bindings/reset/st,sti-softreset.txt
@@ -42,5 +42,5 @@ example:
Macro definitions for the supported reset channels can be found in:
-include/dt-bindings/reset-controller/stih415-resets.h
-include/dt-bindings/reset-controller/stih416-resets.h
+include/dt-bindings/reset/stih415-resets.h
+include/dt-bindings/reset/stih416-resets.h
diff --git a/dts/Bindings/reset/zynq-reset.txt b/dts/Bindings/reset/zynq-reset.txt
new file mode 100644
index 0000000..5860120
--- /dev/null
+++ b/dts/Bindings/reset/zynq-reset.txt
@@ -0,0 +1,68 @@
+Xilinx Zynq Reset Manager
+
+The Zynq AP-SoC has several different resets.
+
+See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
+
+Required properties:
+- compatible: "xlnx,zynq-reset"
+- reg: SLCR offset and size taken via syscon <0x200 0x48>
+- syscon: <&slcr>
+ This should be a phandle to the Zynq's SLCR registers.
+- #reset-cells: Must be 1
+
+The Zynq Reset Manager needs to be a childnode of the SLCR.
+
+Example:
+ rstc: rstc@200 {
+ compatible = "xlnx,zynq-reset";
+ reg = <0x200 0x48>;
+ #reset-cells = <1>;
+ syscon = <&slcr>;
+ };
+
+Reset outputs:
+ 0 : soft reset
+ 32 : ddr reset
+ 64 : topsw reset
+ 96 : dmac reset
+ 128: usb0 reset
+ 129: usb1 reset
+ 160: gem0 reset
+ 161: gem1 reset
+ 164: gem0 rx reset
+ 165: gem1 rx reset
+ 166: gem0 ref reset
+ 167: gem1 ref reset
+ 192: sdio0 reset
+ 193: sdio1 reset
+ 196: sdio0 ref reset
+ 197: sdio1 ref reset
+ 224: spi0 reset
+ 225: spi1 reset
+ 226: spi0 ref reset
+ 227: spi1 ref reset
+ 256: can0 reset
+ 257: can1 reset
+ 258: can0 ref reset
+ 259: can1 ref reset
+ 288: i2c0 reset
+ 289: i2c1 reset
+ 320: uart0 reset
+ 321: uart1 reset
+ 322: uart0 ref reset
+ 323: uart1 ref reset
+ 352: gpio reset
+ 384: lqspi reset
+ 385: qspi ref reset
+ 416: smc reset
+ 417: smc ref reset
+ 448: ocm reset
+ 512: fpga0 out reset
+ 513: fpga1 out reset
+ 514: fpga2 out reset
+ 515: fpga3 out reset
+ 544: a9 reset 0
+ 545: a9 reset 1
+ 552: peri reset
+
diff --git a/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt b/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt
index 34c1505..5d3791e 100644
--- a/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt
+++ b/dts/Bindings/rtc/atmel,at91rm9200-rtc.txt
@@ -5,6 +5,7 @@ Required properties:
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: rtc alarm/event interrupt
+- clocks: phandle to input clock.
Example:
@@ -12,4 +13,5 @@ rtc@fffffe00 {
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x100>;
interrupts = <1 4 7>;
+ clocks = <&clk32k>;
};
diff --git a/dts/Bindings/rtc/nxp,lpc1788-rtc.txt b/dts/Bindings/rtc/nxp,lpc1788-rtc.txt
new file mode 100644
index 0000000..3c97bd1
--- /dev/null
+++ b/dts/Bindings/rtc/nxp,lpc1788-rtc.txt
@@ -0,0 +1,21 @@
+NXP LPC1788 real-time clock
+
+The LPC1788 RTC provides calendar and clock functionality
+together with periodic tick and alarm interrupt support.
+
+Required properties:
+- compatible : must contain "nxp,lpc1788-rtc"
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A single interrupt specifier.
+- clocks : Must contain clock specifiers for rtc and register clock
+- clock-names : Must contain "rtc" and "reg"
+ See ../clocks/clock-bindings.txt for details.
+
+Example:
+rtc: rtc@40046000 {
+ compatible = "nxp,lpc1788-rtc";
+ reg = <0x40046000 0x1000>;
+ interrupts = <47>;
+ clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
+ clock-names = "rtc", "reg";
+};
diff --git a/dts/Bindings/rtc/rtc-mxc.txt b/dts/Bindings/rtc/rtc-mxc.txt
new file mode 100644
index 0000000..5bcd31d
--- /dev/null
+++ b/dts/Bindings/rtc/rtc-mxc.txt
@@ -0,0 +1,26 @@
+* Real Time Clock of the i.MX SoCs
+
+RTC controller for the i.MX SoCs
+
+Required properties:
+- compatible: Should be "fsl,imx1-rtc" or "fsl,imx21-rtc".
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: IRQ line for the RTC.
+- clocks: should contain two entries:
+ * one for the input reference
+ * one for the the SoC RTC
+- clock-names: should contain:
+ * "ref" for the input reference clock
+ * "ipg" for the SoC RTC clock
+
+Example:
+
+rtc@10007000 {
+ compatible = "fsl,imx21-rtc";
+ reg = <0x10007000 0x1000>;
+ interrupts = <22>;
+ clocks = <&clks IMX27_CLK_CKIL>,
+ <&clks IMX27_CLK_RTC_IPG_GATE>;
+ clock-names = "ref", "ipg";
+};
diff --git a/dts/Bindings/rtc/rtc-omap.txt b/dts/Bindings/rtc/rtc-omap.txt
index 4ba4dbd..bf7d11a 100644
--- a/dts/Bindings/rtc/rtc-omap.txt
+++ b/dts/Bindings/rtc/rtc-omap.txt
@@ -8,6 +8,7 @@ Required properties:
Wakeup generation for event Alarm. It can also be
used to control an external PMIC via the
pmic_power_en pin.
+ - "ti,am4372-rtc" - for RTC IP used similar to that on AM437X SoC family.
- reg: Address range of rtc register set
- interrupts: rtc timer, alarm interrupts in order
- interrupt-parent: phandle for the interrupt controller
@@ -15,6 +16,8 @@ Required properties:
Optional properties:
- system-power-controller: whether the rtc is controlling the system power
through pmic_power_en
+- clocks: Any internal or external clocks feeding in to rtc
+- clock-names: Corresponding names of the clocks
Example:
@@ -25,4 +28,6 @@ rtc@1c23000 {
19>;
interrupt-parent = <&intc>;
system-power-controller;
+ clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+ clock-names = "ext-clk", "int-clk";
};
diff --git a/dts/Bindings/rtc/rtc-st-lpc.txt b/dts/Bindings/rtc/rtc-st-lpc.txt
index 73407f5..daf8826 100644
--- a/dts/Bindings/rtc/rtc-st-lpc.txt
+++ b/dts/Bindings/rtc/rtc-st-lpc.txt
@@ -1,20 +1,23 @@
STMicroelectronics Low Power Controller (LPC) - RTC
===================================================
-LPC currently supports Watchdog OR Real Time Clock functionality.
+LPC currently supports Watchdog OR Real Time Clock OR Clocksource
+functionality.
[See: ../watchdog/st_lpc_wdt.txt for Watchdog options]
+[See: ../timer/st,stih407-lpc for Clocksource options]
Required properties
-- compatible : Must be one of: "st,stih407-lpc" "st,stih416-lpc"
- "st,stih415-lpc" "st,stid127-lpc"
+- compatible : Must be: "st,stih407-lpc"
- reg : LPC registers base address + size
- interrupts : LPC interrupt line number and associated flags
- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
-- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or
- ST_LPC_MODE_WDT [1]. One (and only one) mode must be
- selected.
+- st,lpc-mode : The LPC can run either one of three modes:
+ ST_LPC_MODE_RTC [0]
+ ST_LPC_MODE_WDT [1]
+ ST_LPC_MODE_CLKSRC [2]
+ One (and only one) mode must be selected.
Example:
lpc@fde05000 {
diff --git a/dts/Bindings/i2c/ti,bq32k.txt b/dts/Bindings/rtc/ti,bq32k.txt
index e204906..e204906 100644
--- a/dts/Bindings/i2c/ti,bq32k.txt
+++ b/dts/Bindings/rtc/ti,bq32k.txt
diff --git a/dts/Bindings/rtc/xlnx-rtc.txt b/dts/Bindings/rtc/xlnx-rtc.txt
new file mode 100644
index 0000000..0df6f01
--- /dev/null
+++ b/dts/Bindings/rtc/xlnx-rtc.txt
@@ -0,0 +1,25 @@
+* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
+
+RTC controller for the Xilinx Zynq MPSoC Real Time Clock
+Separate IRQ lines for seconds and alarm
+
+Required properties:
+- compatible: Should be "xlnx,zynqmp-rtc"
+- reg: Physical base address of the controller and length
+ of memory mapped region.
+- interrupts: IRQ lines for the RTC.
+- interrupt-names: interrupt line names eg. "sec" "alarm"
+
+Optional:
+- calibration: calibration value for 1 sec period which will
+ be programmed directly to calibration register
+
+Example:
+rtc: rtc@ffa60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ reg = <0x0 0xffa60000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ calibration = <0x198233>;
+};
diff --git a/dts/Bindings/serial/atmel-usart.txt b/dts/Bindings/serial/atmel-usart.txt
index 90787aa..e6e6142 100644
--- a/dts/Bindings/serial/atmel-usart.txt
+++ b/dts/Bindings/serial/atmel-usart.txt
@@ -22,6 +22,8 @@ Optional properties:
memory peripheral interface and USART DMA channel ID, FIFO configuration.
Refer to dma.txt and atmel-dma.txt for details.
- dma-names: "rx" for RX channel, "tx" for TX channel.
+- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
+ capable USARTs.
<chip> compatible description:
- at91rm9200: legacy USART support
@@ -57,4 +59,5 @@ Example:
dmas = <&dma0 2 0x3>,
<&dma0 2 0x204>;
dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
};
diff --git a/dts/Bindings/serial/axis,etraxfs-uart.txt b/dts/Bindings/serial/axis,etraxfs-uart.txt
index ebcbb62..51b3c9e 100644
--- a/dts/Bindings/serial/axis,etraxfs-uart.txt
+++ b/dts/Bindings/serial/axis,etraxfs-uart.txt
@@ -6,7 +6,7 @@ Required properties:
- interrupts: device interrupt
Optional properties:
-- {dtr,dsr,ri,cd}-gpios: specify a GPIO for DTR/DSR/RI/CD
+- {dtr,dsr,rng,dcd}-gpios: specify a GPIO for DTR/DSR/RI/DCD
line respectively.
Example:
@@ -16,4 +16,8 @@ serial@b00260000 {
reg = <0xb0026000 0x1000>;
interrupts = <68>;
status = "disabled";
+ dtr-gpios = <&sysgpio 0 GPIO_ACTIVE_LOW>;
+ dsr-gpios = <&sysgpio 1 GPIO_ACTIVE_LOW>;
+ rng-gpios = <&sysgpio 2 GPIO_ACTIVE_LOW>;
+ dcd-gpios = <&sysgpio 3 GPIO_ACTIVE_LOW>;
};
diff --git a/dts/Bindings/serial/mtk-uart.txt b/dts/Bindings/serial/mtk-uart.txt
index 8d63f1d..2d47add 100644
--- a/dts/Bindings/serial/mtk-uart.txt
+++ b/dts/Bindings/serial/mtk-uart.txt
@@ -5,10 +5,12 @@ Required properties:
* "mediatek,mt8135-uart" for MT8135 compatible UARTS
* "mediatek,mt8127-uart" for MT8127 compatible UARTS
* "mediatek,mt8173-uart" for MT8173 compatible UARTS
+ * "mediatek,mt6795-uart" for MT6795 compatible UARTS
* "mediatek,mt6589-uart" for MT6589 compatible UARTS
* "mediatek,mt6582-uart" for MT6582 compatible UARTS
- * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6589, MT6582,
- MT6577)
+ * "mediatek,mt6580-uart" for MT6580 compatible UARTS
+ * "mediatek,mt6577-uart" for all compatible UARTS (MT8173, MT6795,
+ MT6589, MT6582, MT6580, MT6577)
- reg: The base address of the UART register bank.
diff --git a/dts/Bindings/serial/omap_serial.txt b/dts/Bindings/serial/omap_serial.txt
index 54c2a15..7a71b5d 100644
--- a/dts/Bindings/serial/omap_serial.txt
+++ b/dts/Bindings/serial/omap_serial.txt
@@ -4,6 +4,9 @@ Required properties:
- compatible : should be "ti,omap2-uart" for OMAP2 controllers
- compatible : should be "ti,omap3-uart" for OMAP3 controllers
- compatible : should be "ti,omap4-uart" for OMAP4 controllers
+- compatible : should be "ti,am4372-uart" for AM437x controllers
+- compatible : should be "ti,am3352-uart" for AM335x controllers
+- compatible : should be "ti,dra742-uart" for DRA7x controllers
- reg : address and length of the register space
- interrupts or interrupts-extended : Should contain the uart interrupt
specifier or both the interrupt
diff --git a/dts/Bindings/soc/mediatek/scpsys.txt b/dts/Bindings/soc/mediatek/scpsys.txt
new file mode 100644
index 0000000..c051114
--- /dev/null
+++ b/dts/Bindings/soc/mediatek/scpsys.txt
@@ -0,0 +1,41 @@
+MediaTek SCPSYS
+===============
+
+The System Control Processor System (SCPSYS) has several power management
+related tasks in the system. The tasks include thermal measurement, dynamic
+voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
+The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
+domain control.
+
+The driver implements the Generic PM domain bindings described in
+power/power_domain.txt. It provides the power domains defined in
+include/dt-bindings/power/mt8173-power.h.
+
+Required properties:
+- compatible: Must be "mediatek,mt8173-scpsys"
+- #power-domain-cells: Must be 1
+- reg: Address range of the SCPSYS unit
+- infracfg: must contain a phandle to the infracfg controller
+- clock, clock-names: clocks according to the common clock binding.
+ The clocks needed "mm" and "mfg". These are the
+ clocks which hardware needs to be enabled before
+ enabling certain power domains.
+
+Example:
+
+ scpsys: scpsys@10006000 {
+ #power-domain-cells = <1>;
+ compatible = "mediatek,mt8173-scpsys";
+ reg = <0 0x10006000 0 0x1000>;
+ infracfg = <&infracfg>;
+ clocks = <&clk26m>,
+ <&topckgen CLK_TOP_MM_SEL>;
+ clock-names = "mfg", "mm";
+ };
+
+Example consumer:
+
+ afe: mt8173-afe-pcm@11220000 {
+ compatible = "mediatek,mt8173-afe-pcm";
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
+ };
diff --git a/dts/Bindings/soc/qcom,smd-rpm.txt b/dts/Bindings/soc/qcom,smd-rpm.txt
new file mode 100644
index 0000000..e27f5c4
--- /dev/null
+++ b/dts/Bindings/soc/qcom,smd-rpm.txt
@@ -0,0 +1,117 @@
+Qualcomm Resource Power Manager (RPM) over SMD
+
+This driver is used to interface with the Resource Power Manager (RPM) found in
+various Qualcomm platforms. The RPM allows each component in the system to vote
+for state of the system resources, such as clocks, regulators and bus
+frequencies.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,rpm-msm8974"
+
+- qcom,smd-channels:
+ Usage: required
+ Value type: <stringlist>
+ Definition: Shared Memory channel used for communication with the RPM
+
+= SUBDEVICES
+
+The RPM exposes resources to its subnodes. The below bindings specify the set
+of valid subnodes that can operate on these resources.
+
+== Regulators
+
+Regulator nodes are identified by their compatible:
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,rpm-pm8841-regulators"
+ "qcom,rpm-pm8941-regulators"
+
+- vdd_s1-supply:
+- vdd_s2-supply:
+- vdd_s3-supply:
+- vdd_s4-supply:
+- vdd_s5-supply:
+- vdd_s6-supply:
+- vdd_s7-supply:
+- vdd_s8-supply:
+ Usage: optional (pm8841 only)
+ Value type: <phandle>
+ Definition: reference to regulator supplying the input pin, as
+ described in the data sheet
+
+- vdd_s1-supply:
+- vdd_s2-supply:
+- vdd_s3-supply:
+- vdd_l1_l3-supply:
+- vdd_l2_lvs1_2_3-supply:
+- vdd_l4_l11-supply:
+- vdd_l5_l7-supply:
+- vdd_l6_l12_l14_l15-supply:
+- vdd_l8_l16_l18_l19-supply:
+- vdd_l9_l10_l17_l22-supply:
+- vdd_l13_l20_l23_l24-supply:
+- vdd_l21-supply:
+- vin_5vs-supply:
+ Usage: optional (pm8941 only)
+ Value type: <phandle>
+ Definition: reference to regulator supplying the input pin, as
+ described in the data sheet
+
+The regulator node houses sub-nodes for each regulator within the device. Each
+sub-node is identified using the node's name, with valid values listed for each
+of the pmics below.
+
+pm8841:
+ s1, s2, s3, s4, s5, s6, s7, s8
+
+pm8941:
+ s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
+ l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, lvs1, lvs2,
+ lvs3, 5vs1, 5vs2
+
+The content of each sub-node is defined by the standard binding for regulators -
+see regulator.txt.
+
+= EXAMPLE
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <0 168 1>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests {
+ compatible = "qcom,rpm-msm8974";
+ qcom,smd-channels = "rpm_requests";
+
+ pm8941-regulators {
+ compatible = "qcom,rpm-pm8941-regulators";
+ vdd_l13_l20_l23_l24-supply = <&pm8941_boost>;
+
+ pm8941_s3: s3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ pm8941_boost: s4 {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ pm8941_l20: l20 {
+ regulator-min-microvolt = <2950000>;
+ regulator-max-microvolt = <2950000>;
+ };
+ };
+ };
+ };
+ };
+
diff --git a/dts/Bindings/soc/qcom/qcom,smd.txt b/dts/Bindings/soc/qcom/qcom,smd.txt
new file mode 100644
index 0000000..97d9b3e
--- /dev/null
+++ b/dts/Bindings/soc/qcom/qcom,smd.txt
@@ -0,0 +1,85 @@
+Qualcomm Shared Memory Driver (SMD) binding
+
+This binding describes the Qualcomm Shared Memory Driver, a fifo based
+communication channel for sending data between the various subsystems in
+Qualcomm platforms.
+
+- compatible:
+ Usage: required
+ Value type: <stringlist>
+ Definition: must be "qcom,smd"
+
+= EDGES
+
+Each subnode of the SMD node represents a remote subsystem or a remote
+processor of some sort - or in SMD language an "edge". The name of the edges
+are not important.
+The edge is described by the following properties:
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the IRQ used by the remote processor to
+ signal this processor about communication related updates
+
+- qcom,ipc:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: three entries specifying the outgoing ipc bit used for
+ signaling the remote processor:
+ - phandle to a syscon node representing the apcs registers
+ - u32 representing offset to the register within the syscon
+ - u32 representing the ipc bit within the register
+
+- qcom,smd-edge:
+ Usage: required
+ Value type: <u32>
+ Definition: the identifier of the remote processor in the smd channel
+ allocation table
+
+- qcom,remote-pid:
+ Usage: optional
+ Value type: <u32>
+ Definition: the identifier for the remote processor as known by the rest
+ of the system.
+
+= SMD DEVICES
+
+In turn, subnodes of the "edges" represent devices tied to SMD channels on that
+"edge". The names of the devices are not important. The properties of these
+nodes are defined by the individual bindings for the SMD devices - but must
+contain the following property:
+
+- qcom,smd-channels:
+ Usage: required
+ Value type: <stringlist>
+ Definition: a list of channels tied to this device, used for matching
+ the device to channels
+
+= EXAMPLE
+
+The following example represents a smd node, with one edge representing the
+"rpm" subsystem. For the "rpm" subsystem we have a device tied to the
+"rpm_request" channel.
+
+ apcs: syscon@f9011000 {
+ compatible = "syscon";
+ reg = <0xf9011000 0x1000>;
+ };
+
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <0 168 1>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests {
+ compatible = "qcom,rpm-msm8974";
+ qcom,smd-channels = "rpm_requests";
+
+ ...
+ };
+ };
+ };
diff --git a/dts/Bindings/sound/cs4349.txt b/dts/Bindings/sound/cs4349.txt
new file mode 100644
index 0000000..54c117b
--- /dev/null
+++ b/dts/Bindings/sound/cs4349.txt
@@ -0,0 +1,19 @@
+CS4349 audio CODEC
+
+Required properties:
+
+ - compatible : "cirrus,cs4349"
+
+ - reg : the I2C address of the device for I2C
+
+Optional properties:
+
+ - reset-gpios : a GPIO spec for the reset pin.
+
+Example:
+
+codec: cs4349@48 {
+ compatible = "cirrus,cs4349";
+ reg = <0x48>;
+ reset-gpios = <&gpio 54 0>;
+};
diff --git a/dts/Bindings/sound/ics43432.txt b/dts/Bindings/sound/ics43432.txt
new file mode 100644
index 0000000..b02e3a6
--- /dev/null
+++ b/dts/Bindings/sound/ics43432.txt
@@ -0,0 +1,17 @@
+Invensense ICS-43432 MEMS microphone with I2S output.
+
+There are no software configuration options for this device, indeed, the only
+host connection is the I2S interface. Apart from requirements on clock
+frequency (460 kHz to 3.379 MHz according to the data sheet) there must be
+64 clock cycles in each stereo output frame; 24 of the 32 available bits
+contain audio data. A hardware pin determines if the device outputs data
+on the left or right channel of the I2S frame.
+
+Required properties:
+ - compatible : Must be "invensense,ics43432"
+
+Example:
+
+ ics43432: ics43432 {
+ compatible = "invensense,ics43432";
+ };
diff --git a/dts/Bindings/sound/max98357a.txt b/dts/Bindings/sound/max98357a.txt
index a7a149a..28645a2 100644
--- a/dts/Bindings/sound/max98357a.txt
+++ b/dts/Bindings/sound/max98357a.txt
@@ -4,7 +4,11 @@ This node models the Maxim MAX98357A DAC.
Required properties:
- compatible : "maxim,max98357a"
-- sdmode-gpios : GPIO specifier for the GPIO -> DAC SDMODE pin
+
+Optional properties:
+- sdmode-gpios : GPIO specifier for the chip's SD_MODE pin.
+ If this option is not specified then driver does not manage
+ the pin state (e.g. chip is always on).
Example:
diff --git a/dts/Bindings/sound/nvidia,tegra30-hda.txt b/dts/Bindings/sound/nvidia,tegra30-hda.txt
index 13e2ef4..275c6ea 100644
--- a/dts/Bindings/sound/nvidia,tegra30-hda.txt
+++ b/dts/Bindings/sound/nvidia,tegra30-hda.txt
@@ -8,10 +8,10 @@ Required properties:
- interrupts : The interrupt from the HDA controller.
- clocks : Must contain an entry for each required entry in clock-names.
See ../clocks/clock-bindings.txt for details.
-- clock-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi
+- clock-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x
- resets : Must contain an entry for each entry in reset-names.
See ../reset/reset.txt for details.
-- reset-names : Must include the following entries: hda, hdacodec_2x, hda2hdmi
+- reset-names : Must include the following entries: hda, hda2hdmi, hda2codec_2x
Example:
@@ -24,7 +24,7 @@ hda@0,70030000 {
<&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
clock-names = "hda", "hda2hdmi", "hda2codec_2x";
resets = <&tegra_car 125>, /* hda */
- <&tegra_car 128>; /* hda2hdmi */
- <&tegra_car 111>, /* hda2codec_2x */
+ <&tegra_car 128>, /* hda2hdmi */
+ <&tegra_car 111>; /* hda2codec_2x */
reset-names = "hda", "hda2hdmi", "hda2codec_2x";
};
diff --git a/dts/Bindings/sound/renesas,rsnd.txt b/dts/Bindings/sound/renesas,rsnd.txt
index b6b3a78..1173395 100644
--- a/dts/Bindings/sound/renesas,rsnd.txt
+++ b/dts/Bindings/sound/renesas,rsnd.txt
@@ -18,6 +18,12 @@ Required properties:
- rcar_sound,src : Should contain SRC feature.
The number of SRC subnode should be same as HW.
see below for detail.
+- rcar_sound,ctu : Should contain CTU feature.
+ The number of CTU subnode should be same as HW.
+ see below for detail.
+- rcar_sound,mix : Should contain MIX feature.
+ The number of MIX subnode should be same as HW.
+ see below for detail.
- rcar_sound,dvc : Should contain DVC feature.
The number of DVC subnode should be same as HW.
see below for detail.
@@ -90,6 +96,22 @@ rcar_sound: sound@ec500000 {
};
};
+ rcar_sound,mix {
+ mix0: mix@0 { };
+ mix1: mix@1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu@0 { };
+ ctu01: ctu@1 { };
+ ctu02: ctu@2 { };
+ ctu03: ctu@3 { };
+ ctu10: ctu@4 { };
+ ctu11: ctu@5 { };
+ ctu12: ctu@6 { };
+ ctu13: ctu@7 { };
+ };
+
rcar_sound,src {
src0: src@0 {
interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/dts/Bindings/sound/renesas,rsrc-card.txt b/dts/Bindings/sound/renesas,rsrc-card.txt
index c641550..962748a 100644
--- a/dts/Bindings/sound/renesas,rsrc-card.txt
+++ b/dts/Bindings/sound/renesas,rsrc-card.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible : "renesas,rsrc-card,<board>"
Examples with soctypes are:
+ - "renesas,rsrc-card"
- "renesas,rsrc-card,lager"
- "renesas,rsrc-card,koelsch"
Optional properties:
@@ -29,6 +30,12 @@ Optional subnode properties:
- frame-inversion : bool property. Add this if the
dai-link uses frame clock inversion.
- convert-rate : platform specified sampling rate convert
+- audio-prefix : see audio-routing
+- audio-routing : A list of the connections between audio components.
+ Each entry is a pair of strings, the first being the connection's sink,
+ the second being the connection's source. Valid names for sources.
+ use audio-prefix if some components is using same sink/sources naming.
+ it can be used if compatible was "renesas,rsrc-card";
Required CPU/CODEC subnodes properties:
diff --git a/dts/Bindings/sound/rockchip-max98090.txt b/dts/Bindings/sound/rockchip-max98090.txt
new file mode 100644
index 0000000..a805aa9
--- /dev/null
+++ b/dts/Bindings/sound/rockchip-max98090.txt
@@ -0,0 +1,19 @@
+ROCKCHIP with MAX98090 CODEC
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-max98090"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+ connected to the CODEC
+- rockchip,audio-codec: The phandle of the MAX98090 audio codec
+- rockchip,headset-codec: The phandle of Ext chip for jack detection
+
+Example:
+
+sound {
+ compatible = "rockchip,rockchip-audio-max98090";
+ rockchip,model = "ROCKCHIP-I2S";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&max98090>;
+ rockchip,headset-codec = <&headsetcodec>;
+};
diff --git a/dts/Bindings/sound/rockchip-rt5645.txt b/dts/Bindings/sound/rockchip-rt5645.txt
new file mode 100644
index 0000000..411a62b
--- /dev/null
+++ b/dts/Bindings/sound/rockchip-rt5645.txt
@@ -0,0 +1,17 @@
+ROCKCHIP with RT5645/RT5650 CODECS
+
+Required properties:
+- compatible: "rockchip,rockchip-audio-rt5645"
+- rockchip,model: The user-visible name of this sound complex
+- rockchip,i2s-controller: The phandle of the Rockchip I2S controller that's
+ connected to the CODEC
+- rockchip,audio-codec: The phandle of the RT5645/RT5650 audio codec
+
+Example:
+
+sound {
+ compatible = "rockchip,rockchip-audio-rt5645";
+ rockchip,model = "ROCKCHIP-I2S";
+ rockchip,i2s-controller = <&i2s>;
+ rockchip,audio-codec = <&rt5645>;
+};
diff --git a/dts/Bindings/sound/st,sti-asoc-card.txt b/dts/Bindings/sound/st,sti-asoc-card.txt
new file mode 100644
index 0000000..028fa1c
--- /dev/null
+++ b/dts/Bindings/sound/st,sti-asoc-card.txt
@@ -0,0 +1,155 @@
+STMicroelectronics sti ASoC cards
+
+The sti ASoC Sound Card can be used, for all sti SoCs using internal sti-sas
+codec or external codecs.
+
+sti sound drivers allows to expose sti SoC audio interface through the
+generic ASoC simple card. For details about sound card declaration please refer to
+Documentation/devicetree/bindings/sound/simple-card.txt.
+
+1) sti-uniperiph-dai: audio dai device.
+---------------------------------------
+
+Required properties:
+ - compatible: "st,sti-uni-player" or "st,sti-uni-reader"
+
+ - st,syscfg: phandle to boot-device system configuration registers
+
+ - clock-names: name of the clocks listed in clocks property in the same order
+
+ - reg: CPU DAI IP Base address and size entries, listed in same
+ order than the CPU_DAI properties.
+
+ - reg-names: names of the mapped memory regions listed in regs property in
+ the same order.
+
+ - interrupts: CPU_DAI interrupt line, listed in the same order than the
+ CPU_DAI properties.
+
+ - dma: CPU_DAI DMA controller phandle and DMA request line, listed in the same
+ order than the CPU_DAI properties.
+
+ - dma-names: identifier string for each DMA request line in the dmas property.
+ "tx" for "st,sti-uni-player" compatibility
+ "rx" for "st,sti-uni-reader" compatibility
+
+ - version: IP version integrated in SOC.
+
+ - dai-name: DAI name that describes the IP.
+
+Required properties ("st,sti-uni-player" compatibility only):
+ - clocks: CPU_DAI IP clock source, listed in the same order than the
+ CPU_DAI properties.
+
+ - uniperiph-id: internal SOC IP instance ID.
+
+ - IP mode: IP working mode depending on associated codec.
+ "HDMI" connected to HDMI codec IP and IEC HDMI formats.
+ "SPDIF"connected to SPDIF codec and support SPDIF formats.
+ "PCM" PCM standard mode for I2S or TDM bus.
+
+Optional properties:
+ - pinctrl-0: defined for CPU_DAI@1 and CPU_DAI@4 to describe I2S PIOs for
+ external codecs connection.
+
+ - pinctrl-names: should contain only one value - "default".
+
+Example:
+
+ sti_uni_player2: sti-uni-player@2 {
+ compatible = "st,sti-uni-player";
+ status = "okay";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
+ reg = <0x8D82000 0x158>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 4 0 1>;
+ dai-name = "Uni Player #1 (DAC)";
+ dma-names = "tx";
+ uniperiph-id = <2>;
+ version = <5>;
+ mode = "PCM";
+ };
+
+ sti_uni_player3: sti-uni-player@3 {
+ compatible = "st,sti-uni-player";
+ status = "okay";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ clocks = <&clk_s_d0_flexgen CLK_SPDIFF>;
+ reg = <0x8D85000 0x158>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 7 0 1>;
+ dma-names = "tx";
+ dai-name = "Uni Player #1 (PIO)";
+ uniperiph-id = <3>;
+ version = <5>;
+ mode = "SPDIF";
+ };
+
+ sti_uni_reader1: sti-uni-reader@1 {
+ compatible = "st,sti-uni-reader";
+ status = "disabled";
+ #sound-dai-cells = <0>;
+ st,syscfg = <&syscfg_core>;
+ reg = <0x8D84000 0x158>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_NONE>;
+ dmas = <&fdma0 6 0 1>;
+ dma-names = "rx";
+ dai-name = "Uni Reader #1 (HDMI RX)";
+ version = <3>;
+ };
+
+2) sti-sas-codec: internal audio codec IPs driver
+-------------------------------------------------
+
+Required properties:
+ - compatible: "st,sti<chip>-sas-codec" .
+ Should be chip "st,stih416-sas-codec" or "st,stih407-sas-codec"
+
+ - st,syscfg: phandle to boot-device system configuration registers.
+
+ - pinctrl-0: SPDIF PIO description.
+
+ - pinctrl-names: should contain only one value - "default".
+
+Example:
+ sti_sas_codec: sti-sas-codec {
+ compatible = "st,stih407-sas-codec";
+ #sound-dai-cells = <1>;
+ st,reg_audio = <&syscfg_core>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif_out >;
+ };
+
+Example of audio card declaration:
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "sti audio card";
+ status = "okay";
+
+ simple-audio-card,dai-link@0 {
+ /* DAC */
+ format = "i2s";
+ dai-tdm-slot-width = <32>;
+ cpu {
+ sound-dai = <&sti_uni_player2>;
+ };
+
+ codec {
+ sound-dai = <&sti_sasg_codec 1>;
+ };
+ };
+ simple-audio-card,dai-link@1 {
+ /* SPDIF */
+ format = "left_j";
+ cpu {
+ sound-dai = <&sti_uni_player3>;
+ };
+
+ codec {
+ sound-dai = <&sti_sasg_codec 0>;
+ };
+ };
+ };
diff --git a/dts/Bindings/spi/snps,dw-apb-ssi.txt b/dts/Bindings/spi/snps,dw-apb-ssi.txt
index bd99193..204b311 100644
--- a/dts/Bindings/spi/snps,dw-apb-ssi.txt
+++ b/dts/Bindings/spi/snps,dw-apb-ssi.txt
@@ -10,6 +10,8 @@ Required properties:
Optional properties:
- cs-gpios : Specifies the gpio pis to be used for chipselects.
- num-cs : The number of chipselects. If omitted, this will default to 4.
+- reg-io-width : The I/O register width (in bytes) implemented by this
+ device. Supported values are 2 or 4 (the default).
Child nodes as per the generic SPI binding.
diff --git a/dts/Bindings/spi/spi-davinci.txt b/dts/Bindings/spi/spi-davinci.txt
index 12ecfe9..d1e914a 100644
--- a/dts/Bindings/spi/spi-davinci.txt
+++ b/dts/Bindings/spi/spi-davinci.txt
@@ -12,6 +12,8 @@ Required properties:
- compatible:
- "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
- "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
+ - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
+ family
- reg: Offset and length of SPI controller register space
- num-cs: Number of chip selects. This includes internal as well as
GPIO chip selects.
diff --git a/dts/Bindings/spi/spi-img-spfi.txt b/dts/Bindings/spi/spi-img-spfi.txt
index e02fbf1..494db60 100644
--- a/dts/Bindings/spi/spi-img-spfi.txt
+++ b/dts/Bindings/spi/spi-img-spfi.txt
@@ -21,6 +21,7 @@ Required properties:
Optional properties:
- img,supports-quad-mode: Should be set if the interface supports quad mode
SPI transfers.
+- spfi-max-frequency: Maximum speed supported by the spfi block.
Example:
diff --git a/dts/Bindings/spi/spi-mt65xx.txt b/dts/Bindings/spi/spi-mt65xx.txt
new file mode 100644
index 0000000..dcefc43
--- /dev/null
+++ b/dts/Bindings/spi/spi-mt65xx.txt
@@ -0,0 +1,51 @@
+Binding for MTK SPI controller
+
+Required properties:
+- compatible: should be one of the following.
+ - mediatek,mt8173-spi: for mt8173 platforms
+ - mediatek,mt8135-spi: for mt8135 platforms
+ - mediatek,mt6589-spi: for mt6589 platforms
+
+- #address-cells: should be 1.
+
+- #size-cells: should be 0.
+
+- reg: Address and length of the register set for the device
+
+- interrupts: Should contain spi interrupt
+
+- clocks: phandles to input clocks.
+ The first should be <&topckgen CLK_TOP_SPI_SEL>.
+ The second should be one of the following.
+ - <&clk26m>: specify parent clock 26MHZ.
+ - <&topckgen CLK_TOP_SYSPLL3_D2>: specify parent clock 109MHZ.
+ It's the default one.
+ - <&topckgen CLK_TOP_SYSPLL4_D2>: specify parent clock 78MHZ.
+ - <&topckgen CLK_TOP_UNIVPLL2_D4>: specify parent clock 104MHZ.
+ - <&topckgen CLK_TOP_UNIVPLL1_D8>: specify parent clock 78MHZ.
+
+- clock-names: shall be "spi-clk" for the controller clock, and
+ "parent-clk" for the parent clock.
+
+Optional properties:
+- mediatek,pad-select: specify which pins group(ck/mi/mo/cs) spi
+ controller used, this value should be 0~3, only required for MT8173.
+ 0: specify GPIO69,70,71,72 for spi pins.
+ 1: specify GPIO102,103,104,105 for spi pins.
+ 2: specify GPIO128,129,130,131 for spi pins.
+ 3: specify GPIO5,6,7,8 for spi pins.
+
+Example:
+
+- SoC Specific Portion:
+spi: spi@1100a000 {
+ compatible = "mediatek,mt8173-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SPI_SEL>, <&topckgen CLK_TOP_SYSPLL3_D2>;
+ clock-names = "spi-clk", "parent-clk";
+ mediatek,pad-select = <0>;
+ status = "disabled";
+};
diff --git a/dts/Bindings/spi/spi-xlp.txt b/dts/Bindings/spi/spi-xlp.txt
new file mode 100644
index 0000000..40e82d5
--- /dev/null
+++ b/dts/Bindings/spi/spi-xlp.txt
@@ -0,0 +1,39 @@
+SPI Master controller for Netlogic XLP MIPS64 SOCs
+==================================================
+
+Currently this SPI controller driver is supported for the following
+Netlogic XLP SoCs:
+ XLP832, XLP316, XLP208, XLP980, XLP532
+
+Required properties:
+- compatible : Should be "netlogic,xlp832-spi".
+- #address-cells : Number of cells required to define a chip select address
+ on the SPI bus.
+- #size-cells : Should be zero.
+- reg : Should contain register location and length.
+- clocks : Phandle of the spi clock
+- interrupts : Interrupt number used by this controller.
+- interrupt-parent : Phandle of the parent interrupt controller.
+
+SPI slave nodes must be children of the SPI master node and can contain
+properties described in Documentation/devicetree/bindings/spi/spi-bus.txt.
+
+Example:
+
+ spi: xlp_spi@3a100 {
+ compatible = "netlogic,xlp832-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x3a100 0x100>;
+ clocks = <&spi_clk>;
+ interrupts = <34>;
+ interrupt-parent = <&pic>;
+
+ spi_nor@1 {
+ compatible = "spansion,s25sl12801";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <1>; /* Chip Select */
+ spi-max-frequency = <40000000>;
+ };
+};
diff --git a/dts/Bindings/staging/iio/adc/mxs-lradc.txt b/dts/Bindings/staging/iio/adc/mxs-lradc.txt
index 3075377..555fb11 100644
--- a/dts/Bindings/staging/iio/adc/mxs-lradc.txt
+++ b/dts/Bindings/staging/iio/adc/mxs-lradc.txt
@@ -1,4 +1,4 @@
-* Freescale i.MX28 LRADC device driver
+* Freescale MXS LRADC device driver
Required properties:
- compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc"
diff --git a/dts/Bindings/timer/img,pistachio-gptimer.txt b/dts/Bindings/timer/img,pistachio-gptimer.txt
new file mode 100644
index 0000000..7afce80
--- /dev/null
+++ b/dts/Bindings/timer/img,pistachio-gptimer.txt
@@ -0,0 +1,28 @@
+* Pistachio general-purpose timer based clocksource
+
+Required properties:
+ - compatible: "img,pistachio-gptimer".
+ - reg: Address range of the timer registers.
+ - interrupts: An interrupt for each of the four timers
+ - clocks: Should contain a clock specifier for each entry in clock-names
+ - clock-names: Should contain the following entries:
+ "sys", interface clock
+ "slow", slow counter clock
+ "fast", fast counter clock
+ - img,cr-periph: Must contain a phandle to the peripheral control
+ syscon node.
+
+Example:
+ timer: timer@18102000 {
+ compatible = "img,pistachio-gptimer";
+ reg = <0x18102000 0x100>;
+ interrupts = <GIC_SHARED 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_periph PERIPH_CLK_COUNTER_FAST>,
+ <&clk_periph PERIPH_CLK_COUNTER_SLOW>,
+ <&cr_periph SYS_CLK_TIMER>;
+ clock-names = "fast", "slow", "sys";
+ img,cr-periph = <&cr_periph>;
+ };
diff --git a/dts/Bindings/timer/mediatek,mtk-timer.txt b/dts/Bindings/timer/mediatek,mtk-timer.txt
index 7c4408f..53a3029 100644
--- a/dts/Bindings/timer/mediatek,mtk-timer.txt
+++ b/dts/Bindings/timer/mediatek,mtk-timer.txt
@@ -2,7 +2,11 @@ Mediatek MT6577, MT6572 and MT6589 Timers
---------------------------------------
Required properties:
-- compatible: Should be "mediatek,mt6577-timer"
+- compatible should contain:
+ * "mediatek,mt6589-timer" for MT6589 compatible timers
+ * "mediatek,mt6580-timer" for MT6580 compatible timers
+ * "mediatek,mt6577-timer" for all compatible timers (MT6589, MT6580,
+ MT6577)
- reg: Should contain location and length for timers register.
- clocks: Clocks driving the timer hardware. This list should include two
clocks. The order is system clock and as second clock the RTC clock.
diff --git a/dts/Bindings/timer/st,stih407-lpc b/dts/Bindings/timer/st,stih407-lpc
new file mode 100644
index 0000000..72acb48
--- /dev/null
+++ b/dts/Bindings/timer/st,stih407-lpc
@@ -0,0 +1,28 @@
+STMicroelectronics Low Power Controller (LPC) - Clocksource
+===========================================================
+
+LPC currently supports Watchdog OR Real Time Clock OR Clocksource
+functionality.
+
+[See: ../watchdog/st_lpc_wdt.txt for Watchdog options]
+[See: ../rtc/rtc-st-lpc.txt for RTC options]
+
+Required properties
+
+- compatible : Must be: "st,stih407-lpc"
+- reg : LPC registers base address + size
+- interrupts : LPC interrupt line number and associated flags
+- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
+- st,lpc-mode : The LPC can run either one of three modes:
+ ST_LPC_MODE_RTC [0]
+ ST_LPC_MODE_WDT [1]
+ ST_LPC_MODE_CLKSRC [2]
+ One (and only one) mode must be selected.
+
+Example:
+ lpc@fde05000 {
+ compatible = "st,stih407-lpc";
+ reg = <0xfde05000 0x1000>;
+ clocks = <&clk_s_d3_flexgen CLK_LPC_0>;
+ st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
+ };
diff --git a/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt b/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt
new file mode 100644
index 0000000..862cd7c
--- /dev/null
+++ b/dts/Bindings/usb/allwinner,sun4i-a10-musb.txt
@@ -0,0 +1,29 @@
+Allwinner sun4i A10 musb DRC/OTG controller
+-------------------------------------------
+
+Required properties:
+ - compatible : "allwinner,sun4i-a10-musb", "allwinner,sun6i-a31-musb"
+ or "allwinner,sun8i-a33-musb"
+ - reg : mmio address range of the musb controller
+ - clocks : clock specifier for the musb controller ahb gate clock
+ - reset : reset specifier for the ahb reset (A31 and newer only)
+ - interrupts : interrupt to which the musb controller is connected
+ - interrupt-names : must be "mc"
+ - phys : phy specifier for the otg phy
+ - phy-names : must be "usb"
+ - dr_mode : Dual-Role mode must be "host" or "otg"
+ - extcon : extcon specifier for the otg phy
+
+Example:
+
+ usb_otg: usb@01c13000 {
+ compatible = "allwinner,sun4i-a10-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ahb_gates 0>;
+ interrupts = <38>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ status = "disabled";
+ };
diff --git a/dts/Bindings/usb/ci-hdrc-usb2.txt b/dts/Bindings/usb/ci-hdrc-usb2.txt
index 553e2fa..d71ef07 100644
--- a/dts/Bindings/usb/ci-hdrc-usb2.txt
+++ b/dts/Bindings/usb/ci-hdrc-usb2.txt
@@ -30,6 +30,21 @@ Optional properties:
argument that indicate usb controller index
- disable-over-current: (FSL only) disable over current detect
- external-vbus-divider: (FSL only) enables off-chip resistor divider for Vbus
+- itc-setting: interrupt threshold control register control, the setting
+ should be aligned with ITC bits at register USBCMD.
+- ahb-burst-config: it is vendor dependent, the required value should be
+ aligned with AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This
+ property is used to change AHB burst configuration, check the chipidea
+ spec for meaning of each value. If this property is not existed, it
+ will use the reset value.
+- tx-burst-size-dword: it is vendor dependent, the tx burst size in dword
+ (4 bytes), This register represents the maximum length of a the burst
+ in 32-bit words while moving data from system memory to the USB
+ bus, changing this value takes effect only the SBUSCFG.AHBBRST is 0.
+- rx-burst-size-dword: it is vendor dependent, the rx burst size in dword
+ (4 bytes), This register represents the maximum length of a the burst
+ in 32-bit words while moving data from the USB bus to system memory,
+ changing this value takes effect only the SBUSCFG.AHBBRST is 0.
Example:
@@ -41,4 +56,9 @@ Example:
phys = <&usb_phy0>;
phy-names = "usb-phy";
vbus-supply = <&reg_usb0_vbus>;
+ gadget-itc-setting = <0x4>; /* 4 micro-frames */
+ /* Incremental burst of unspecified length */
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>; /* 64 bytes */
+ rx-burst-size-dword = <0x10>;
};
diff --git a/dts/Bindings/usb/generic.txt b/dts/Bindings/usb/generic.txt
index 477d5bb..bba8257 100644
--- a/dts/Bindings/usb/generic.txt
+++ b/dts/Bindings/usb/generic.txt
@@ -11,6 +11,19 @@ Optional properties:
"peripheral" and "otg". In case this attribute isn't
passed via DT, USB DRD controllers should default to
OTG.
+ - otg-rev: tells usb driver the release number of the OTG and EH supplement
+ with which the device and its descriptors are compliant,
+ in binary-coded decimal (i.e. 2.0 is 0200H). This
+ property is used if any real OTG features(HNP/SRP/ADP)
+ is enabled, if ADP is required, otg-rev should be
+ 0x0200 or above.
+ - hnp-disable: tells OTG controllers we want to disable OTG HNP, normally HNP
+ is the basic function of real OTG except you want it
+ to be a srp-capable only B device.
+ - srp-disable: tells OTG controllers we want to disable OTG SRP, SRP is
+ optional for OTG device.
+ - adp-disable: tells OTG controllers we want to disable OTG ADP, ADP is
+ optional for OTG device.
This is an attribute to a USB controller such as:
@@ -21,4 +34,6 @@ dwc3@4a030000 {
usb-phy = <&usb2_phy>, <&usb3,phy>;
maximum-speed = "super-speed";
dr_mode = "otg";
+ otg-rev = <0x0200>;
+ adp-disable;
};
diff --git a/dts/Bindings/usb/msm-hsusb.txt b/dts/Bindings/usb/msm-hsusb.txt
index bd8d9e7..8654a3e 100644
--- a/dts/Bindings/usb/msm-hsusb.txt
+++ b/dts/Bindings/usb/msm-hsusb.txt
@@ -52,6 +52,10 @@ Required properties:
Optional properties:
- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg"
+- switch-gpio: A phandle + gpio-specifier pair. Some boards are using Dual
+ SPDT USB Switch, witch is cotrolled by GPIO to de/multiplex
+ D+/D- USB lines between connectors.
+
- qcom,phy-init-sequence: PHY configuration sequence values. This is related to Device
Mode Eye Diagram test. Start address at which these values will be
written is ULPI_EXT_VENDOR_SPECIFIC. Value of -1 is reserved as
diff --git a/dts/Bindings/usb/qcom,usb-8x16-phy.txt b/dts/Bindings/usb/qcom,usb-8x16-phy.txt
new file mode 100644
index 0000000..2cb2168
--- /dev/null
+++ b/dts/Bindings/usb/qcom,usb-8x16-phy.txt
@@ -0,0 +1,76 @@
+Qualcomm's APQ8016/MSM8916 USB transceiver controller
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: Should contain "qcom,usb-8x16-phy".
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: USB PHY base address and length of the register map
+
+- clocks:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: See clock-bindings.txt section "consumers". List of
+ two clock specifiers for interface and core controller
+ clocks.
+
+- clock-names:
+ Usage: required
+ Value type: <string>
+ Definition: Must contain "iface" and "core" strings.
+
+- vddcx-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: phandle to the regulator VDCCX supply node.
+
+- v1p8-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: phandle to the regulator 1.8V supply node.
+
+- v3p3-supply:
+ Usage: required
+ Value type: <phandle>
+ Definition: phandle to the regulator 3.3V supply node.
+
+- resets:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: See reset.txt section "consumers". PHY reset specifier.
+
+- reset-names:
+ Usage: required
+ Value type: <string>
+ Definition: Must contain "phy" string.
+
+- switch-gpio:
+ Usage: optional
+ Value type: <prop-encoded-array>
+ Definition: Some boards are using Dual SPDT USB Switch, witch is
+ controlled by GPIO to de/multiplex D+/D- USB lines
+ between connectors.
+
+Example:
+ usb_phy: phy@78d9000 {
+ compatible = "qcom,usb-8x16-phy";
+ reg = <0x78d9000 0x400>;
+
+ vddcx-supply = <&pm8916_s1_corner>;
+ v1p8-supply = <&pm8916_l7>;
+ v3p3-supply = <&pm8916_l13>;
+
+ clocks = <&gcc GCC_USB_HS_AHB_CLK>,
+ <&gcc GCC_USB_HS_SYSTEM_CLK>;
+ clock-names = "iface", "core";
+
+ resets = <&gcc GCC_USB2A_PHY_BCR>;
+ reset-names = "phy";
+
+ // D+/D- lines: 1 - Routed to HUB, 0 - Device connector
+ switch-gpio = <&pm8916_gpios 4 GPIO_ACTIVE_HIGH>;
+ };
+
diff --git a/dts/Bindings/vendor-prefixes.txt b/dts/Bindings/vendor-prefixes.txt
index d444757..ac5f0c3 100644
--- a/dts/Bindings/vendor-prefixes.txt
+++ b/dts/Bindings/vendor-prefixes.txt
@@ -46,6 +46,7 @@ chipone ChipOne
chipspark ChipSPARK
chrp Common Hardware Reference Platform
chunghwa Chunghwa Picture Tubes Ltd.
+ciaa Computadora Industrial Abierta Argentina
cirrus Cirrus Logic, Inc.
cloudengines Cloud Engines, Inc.
cnm Chips&Media, Inc.
@@ -54,6 +55,7 @@ cortina Cortina Systems, Inc.
cosmic Cosmic Circuits
crystalfontz Crystalfontz America, Inc.
cubietech Cubietech, Ltd.
+cypress Cypress Semiconductor Corporation
dallas Maxim Integrated Products (formerly Dallas Semiconductor)
davicom DAVICOM Semiconductor, Inc.
delta Delta Electronics, Inc.
@@ -110,8 +112,10 @@ ingenic Ingenic Semiconductor
innolux Innolux Corporation
intel Intel Corporation
intercontrol Inter Control Group
+invensense InvenSense Inc.
isee ISEE 2007 S.L.
isil Intersil
+jedec JEDEC Solid State Technology Association
karo Ka-Ro electronics GmbH
keymile Keymile GmbH
kinetic Kinetic Technologies
@@ -135,21 +139,27 @@ mitsubishi Mitsubishi Electric Corporation
mosaixtech Mosaix Technologies, Inc.
moxa Moxa
mpl MPL AG
+msi Micro-Star International Co. Ltd.
mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
mundoreader Mundo Reader S.L.
murata Murata Manufacturing Co., Ltd.
mxicy Macronix International Co., Ltd.
national National Semiconductor
+nec NEC LCD Technologies, Ltd.
neonode Neonode Inc.
netgear NETGEAR
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
+netxeon Shenzhen Netxeon Technology CO., LTD
newhaven Newhaven Display International
nintendo Nintendo
nokia Nokia
+nuvoton Nuvoton Technology Corporation
nvidia NVIDIA
nxp NXP Semiconductors
+okaya Okaya Electric America, Inc.
onnn ON Semiconductor Corp.
opencores OpenCores.org
+option Option NV
ortustech Ortus Technology Co., Ltd.
ovti OmniVision Technologies
panasonic Panasonic Corporation
@@ -181,6 +191,7 @@ sbs Smart Battery System
schindler Schindler
seagate Seagate Technology PLC
semtech Semtech Corporation
+sharp Sharp Corporation
sil Silicon Image
silabs Silicon Laboratories
siliconmitus Silicon Mitus, Inc.
diff --git a/dts/Bindings/leds/leds-pm8941-wled.txt b/dts/Bindings/video/backlight/pm8941-wled.txt
index a85a964..424f844 100644
--- a/dts/Bindings/leds/leds-pm8941-wled.txt
+++ b/dts/Bindings/video/backlight/pm8941-wled.txt
@@ -5,10 +5,7 @@ Required properties:
- reg: slave address
Optional properties:
-- label: The label for this led
- See Documentation/devicetree/bindings/leds/common.txt
-- linux,default-trigger: Default trigger assigned to the LED
- See Documentation/devicetree/bindings/leds/common.txt
+- label: The name of the backlight device
- qcom,cs-out: bool; enable current sink output
- qcom,cabc: bool; enable content adaptive backlight control
- qcom,ext-gen: bool; use externally generated modulator signal to dim
diff --git a/dts/Bindings/video/fsl,dcu.txt b/dts/Bindings/video/fsl,dcu.txt
new file mode 100644
index 0000000..ebf1be9
--- /dev/null
+++ b/dts/Bindings/video/fsl,dcu.txt
@@ -0,0 +1,22 @@
+Device Tree bindings for Freescale DCU DRM Driver
+
+Required properties:
+- compatible: Should be one of
+ * "fsl,ls1021a-dcu".
+ * "fsl,vf610-dcu".
+
+- reg: Address and length of the register set for dcu.
+- clocks: From common clock binding: handle to dcu clock.
+- clock-names: From common clock binding: Shall be "dcu".
+- big-endian Boolean property, LS1021A DCU registers are big-endian.
+- fsl,panel: The phandle to panel node.
+
+Examples:
+dcu: dcu@2ce0000 {
+ compatible = "fsl,ls1021a-dcu";
+ reg = <0x0 0x2ce0000 0x0 0x10000>;
+ clocks = <&platform_clk 0>;
+ clock-names = "dcu";
+ big-endian;
+ fsl,panel = <&panel>;
+};
diff --git a/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt b/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt
new file mode 100644
index 0000000..f7cc7c0
--- /dev/null
+++ b/dts/Bindings/watchdog/atmel-sama5d4-wdt.txt
@@ -0,0 +1,35 @@
+* Atmel SAMA5D4 Watchdog Timer (WDT) Controller
+
+Required properties:
+- compatible: "atmel,sama5d4-wdt"
+- reg: base physical address and length of memory mapped region.
+
+Optional properties:
+- timeout-sec: watchdog timeout value (in seconds).
+- interrupts: interrupt number to the CPU.
+- atmel,watchdog-type: should be "hardware" or "software".
+ "hardware": enable watchdog fault reset. A watchdog fault triggers
+ watchdog reset.
+ "software": enable watchdog fault interrupt. A watchdog fault asserts
+ watchdog interrupt.
+- atmel,idle-halt: present if you want to stop the watchdog when the CPU is
+ in idle state.
+ CAUTION: This property should be used with care, it actually makes the
+ watchdog not counting when the CPU is in idle state, therefore the
+ watchdog reset time depends on mean CPU usage and will not reset at all
+ if the CPU stop working while it is in idle state, which is probably
+ not what you want.
+- atmel,dbg-halt: present if you want to stop the watchdog when the CPU is
+ in debug state.
+
+Example:
+ watchdog@fc068640 {
+ compatible = "atmel,sama5d4-wdt";
+ reg = <0xfc068640 0x10>;
+ interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
+ timeout-sec = <10>;
+ atmel,watchdog-type = "hardware";
+ atmel,dbg-halt;
+ atmel,idle-halt;
+ status = "okay";
+ };
diff --git a/dts/Bindings/watchdog/atmel-wdt.txt b/dts/Bindings/watchdog/atmel-wdt.txt
index a4d8697..86fa6de 100644
--- a/dts/Bindings/watchdog/atmel-wdt.txt
+++ b/dts/Bindings/watchdog/atmel-wdt.txt
@@ -6,6 +6,7 @@ Required properties:
- compatible: must be "atmel,at91sam9260-wdt".
- reg: physical base address of the controller and length of memory mapped
region.
+- clocks: phandle to input clock.
Optional properties:
- timeout-sec: contains the watchdog timeout in seconds.
@@ -39,6 +40,7 @@ Example:
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
timeout-sec = <15>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
diff --git a/dts/Bindings/watchdog/lpc18xx-wdt.txt b/dts/Bindings/watchdog/lpc18xx-wdt.txt
new file mode 100644
index 0000000..09f6b24
--- /dev/null
+++ b/dts/Bindings/watchdog/lpc18xx-wdt.txt
@@ -0,0 +1,19 @@
+* NXP LPC18xx Watchdog Timer (WDT)
+
+Required properties:
+- compatible: Should be "nxp,lpc1850-wwdt"
+- reg: Should contain WDT registers location and length
+- clocks: Must contain an entry for each entry in clock-names.
+- clock-names: Should contain "wdtclk" and "reg"; the watchdog counter
+ clock and register interface clock respectively.
+- interrupts: Should contain WDT interrupt
+
+Examples:
+
+watchdog@40080000 {
+ compatible = "nxp,lpc1850-wwdt";
+ reg = <0x40080000 0x24>;
+ clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
+ clock-names = "wdtclk", "reg";
+ interrupts = <49>;
+};
diff --git a/dts/Bindings/watchdog/st_lpc_wdt.txt b/dts/Bindings/watchdog/st_lpc_wdt.txt
index 388c88a..039c5ca 100644
--- a/dts/Bindings/watchdog/st_lpc_wdt.txt
+++ b/dts/Bindings/watchdog/st_lpc_wdt.txt
@@ -1,9 +1,11 @@
STMicroelectronics Low Power Controller (LPC) - Watchdog
========================================================
-LPC currently supports Watchdog OR Real Time Clock functionality.
+LPC currently supports Watchdog OR Real Time Clock OR Clocksource
+functionality.
[See: ../rtc/rtc-st-lpc.txt for RTC options]
+[See: ../timer/st,stih407-lpc for Clocksource options]
Required properties
@@ -12,9 +14,11 @@ Required properties
- reg : LPC registers base address + size
- interrupts : LPC interrupt line number and associated flags
- clocks : Clock used by LPC device (See: ../clock/clock-bindings.txt)
-- st,lpc-mode : The LPC can run either one of two modes ST_LPC_MODE_RTC [0] or
- ST_LPC_MODE_WDT [1]. One (and only one) mode must be
- selected.
+- st,lpc-mode : The LPC can run either one of three modes:
+ ST_LPC_MODE_RTC [0]
+ ST_LPC_MODE_WDT [1]
+ ST_LPC_MODE_CLKSRC [2]
+ One (and only one) mode must be selected.
Required properties [watchdog mode]
diff --git a/dts/include/dt-bindings/clock/exynos3250.h b/dts/include/dt-bindings/clock/exynos3250.h
index aab088d..63d01c1 100644
--- a/dts/include/dt-bindings/clock/exynos3250.h
+++ b/dts/include/dt-bindings/clock/exynos3250.h
@@ -31,6 +31,7 @@
#define CLK_FOUT_VPLL 4
#define CLK_FOUT_UPLL 5
#define CLK_FOUT_MPLL 6
+#define CLK_ARM_CLK 7
/* Muxes */
#define CLK_MOUT_MPLL_USER_L 16
diff --git a/dts/include/dt-bindings/clock/exynos5250.h b/dts/include/dt-bindings/clock/exynos5250.h
index 4273891..8183d1c 100644
--- a/dts/include/dt-bindings/clock/exynos5250.h
+++ b/dts/include/dt-bindings/clock/exynos5250.h
@@ -21,6 +21,7 @@
#define CLK_FOUT_CPLL 6
#define CLK_FOUT_EPLL 7
#define CLK_FOUT_VPLL 8
+#define CLK_ARM_CLK 9
/* gate for special clocks (sclk) */
#define CLK_SCLK_CAM_BAYER 128
diff --git a/dts/include/dt-bindings/clock/imx6qdl-clock.h b/dts/include/dt-bindings/clock/imx6qdl-clock.h
index 8780868..8de173f 100644
--- a/dts/include/dt-bindings/clock/imx6qdl-clock.h
+++ b/dts/include/dt-bindings/clock/imx6qdl-clock.h
@@ -251,6 +251,9 @@
#define IMX6QDL_CLK_VIDEO_27M 238
#define IMX6QDL_CLK_MIPI_CORE_CFG 239
#define IMX6QDL_CLK_MIPI_IPG 240
-#define IMX6QDL_CLK_END 241
+#define IMX6QDL_CLK_CAAM_MEM 241
+#define IMX6QDL_CLK_CAAM_ACLK 242
+#define IMX6QDL_CLK_CAAM_IPG 243
+#define IMX6QDL_CLK_END 244
#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */
diff --git a/dts/include/dt-bindings/clock/imx6ul-clock.h b/dts/include/dt-bindings/clock/imx6ul-clock.h
new file mode 100644
index 0000000..c343894
--- /dev/null
+++ b/dts/include/dt-bindings/clock/imx6ul-clock.h
@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2015 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H
+#define __DT_BINDINGS_CLOCK_IMX6UL_H
+
+#define IMX6UL_CLK_DUMMY 0
+#define IMX6UL_CLK_CKIL 1
+#define IMX6UL_CLK_CKIH 2
+#define IMX6UL_CLK_OSC 3
+#define IMX6UL_PLL1_BYPASS_SRC 4
+#define IMX6UL_PLL2_BYPASS_SRC 5
+#define IMX6UL_PLL3_BYPASS_SRC 6
+#define IMX6UL_PLL4_BYPASS_SRC 7
+#define IMX6UL_PLL5_BYPASS_SRC 8
+#define IMX6UL_PLL6_BYPASS_SRC 9
+#define IMX6UL_PLL7_BYPASS_SRC 10
+#define IMX6UL_CLK_PLL1 11
+#define IMX6UL_CLK_PLL2 12
+#define IMX6UL_CLK_PLL3 13
+#define IMX6UL_CLK_PLL4 14
+#define IMX6UL_CLK_PLL5 15
+#define IMX6UL_CLK_PLL6 16
+#define IMX6UL_CLK_PLL7 17
+#define IMX6UL_PLL1_BYPASS 18
+#define IMX6UL_PLL2_BYPASS 19
+#define IMX6UL_PLL3_BYPASS 20
+#define IMX6UL_PLL4_BYPASS 21
+#define IMX6UL_PLL5_BYPASS 22
+#define IMX6UL_PLL6_BYPASS 23
+#define IMX6UL_PLL7_BYPASS 24
+#define IMX6UL_CLK_PLL1_SYS 25
+#define IMX6UL_CLK_PLL2_BUS 26
+#define IMX6UL_CLK_PLL3_USB_OTG 27
+#define IMX6UL_CLK_PLL4_AUDIO 28
+#define IMX6UL_CLK_PLL5_VIDEO 29
+#define IMX6UL_CLK_PLL6_ENET 30
+#define IMX6UL_CLK_PLL7_USB_HOST 31
+#define IMX6UL_CLK_USBPHY1 32
+#define IMX6UL_CLK_USBPHY2 33
+#define IMX6UL_CLK_USBPHY1_GATE 34
+#define IMX6UL_CLK_USBPHY2_GATE 35
+#define IMX6UL_CLK_PLL2_PFD0 36
+#define IMX6UL_CLK_PLL2_PFD1 37
+#define IMX6UL_CLK_PLL2_PFD2 38
+#define IMX6UL_CLK_PLL2_PFD3 39
+#define IMX6UL_CLK_PLL3_PFD0 40
+#define IMX6UL_CLK_PLL3_PFD1 41
+#define IMX6UL_CLK_PLL3_PFD2 42
+#define IMX6UL_CLK_PLL3_PFD3 43
+#define IMX6UL_CLK_ENET_REF 44
+#define IMX6UL_CLK_ENET2_REF 45
+#define IMX6UL_CLK_ENET2_REF_125M 46
+#define IMX6UL_CLK_ENET_PTP_REF 47
+#define IMX6UL_CLK_ENET_PTP 48
+#define IMX6UL_CLK_PLL4_POST_DIV 49
+#define IMX6UL_CLK_PLL4_AUDIO_DIV 50
+#define IMX6UL_CLK_PLL5_POST_DIV 51
+#define IMX6UL_CLK_PLL5_VIDEO_DIV 52
+#define IMX6UL_CLK_PLL2_198M 53
+#define IMX6UL_CLK_PLL3_80M 54
+#define IMX6UL_CLK_PLL3_60M 55
+#define IMX6UL_CLK_STEP 56
+#define IMX6UL_CLK_PLL1_SW 57
+#define IMX6UL_CLK_AXI_ALT_SEL 58
+#define IMX6UL_CLK_AXI_SEL 59
+#define IMX6UL_CLK_PERIPH_PRE 60
+#define IMX6UL_CLK_PERIPH2_PRE 61
+#define IMX6UL_CLK_PERIPH_CLK2_SEL 62
+#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63
+#define IMX6UL_CLK_USDHC1_SEL 64
+#define IMX6UL_CLK_USDHC2_SEL 65
+#define IMX6UL_CLK_BCH_SEL 66
+#define IMX6UL_CLK_GPMI_SEL 67
+#define IMX6UL_CLK_EIM_SLOW_SEL 68
+#define IMX6UL_CLK_SPDIF_SEL 69
+#define IMX6UL_CLK_SAI1_SEL 70
+#define IMX6UL_CLK_SAI2_SEL 71
+#define IMX6UL_CLK_SAI3_SEL 72
+#define IMX6UL_CLK_LCDIF_PRE_SEL 73
+#define IMX6UL_CLK_SIM_PRE_SEL 74
+#define IMX6UL_CLK_LDB_DI0_SEL 75
+#define IMX6UL_CLK_LDB_DI1_SEL 76
+#define IMX6UL_CLK_ENFC_SEL 77
+#define IMX6UL_CLK_CAN_SEL 78
+#define IMX6UL_CLK_ECSPI_SEL 79
+#define IMX6UL_CLK_UART_SEL 80
+#define IMX6UL_CLK_QSPI1_SEL 81
+#define IMX6UL_CLK_PERCLK_SEL 82
+#define IMX6UL_CLK_LCDIF_SEL 83
+#define IMX6UL_CLK_SIM_SEL 84
+#define IMX6UL_CLK_PERIPH 85
+#define IMX6UL_CLK_PERIPH2 86
+#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87
+#define IMX6UL_CLK_LDB_DI0_DIV_7 88
+#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89
+#define IMX6UL_CLK_LDB_DI1_DIV_7 90
+#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91
+#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92
+#define IMX6UL_CLK_ARM 93
+#define IMX6UL_CLK_PERIPH_CLK2 94
+#define IMX6UL_CLK_PERIPH2_CLK2 95
+#define IMX6UL_CLK_AHB 96
+#define IMX6UL_CLK_MMDC_PODF 97
+#define IMX6UL_CLK_AXI_PODF 98
+#define IMX6UL_CLK_PERCLK 99
+#define IMX6UL_CLK_IPG 100
+#define IMX6UL_CLK_USDHC1_PODF 101
+#define IMX6UL_CLK_USDHC2_PODF 102
+#define IMX6UL_CLK_BCH_PODF 103
+#define IMX6UL_CLK_GPMI_PODF 104
+#define IMX6UL_CLK_EIM_SLOW_PODF 105
+#define IMX6UL_CLK_SPDIF_PRED 106
+#define IMX6UL_CLK_SPDIF_PODF 107
+#define IMX6UL_CLK_SAI1_PRED 108
+#define IMX6UL_CLK_SAI1_PODF 109
+#define IMX6UL_CLK_SAI2_PRED 110
+#define IMX6UL_CLK_SAI2_PODF 111
+#define IMX6UL_CLK_SAI3_PRED 112
+#define IMX6UL_CLK_SAI3_PODF 113
+#define IMX6UL_CLK_LCDIF_PRED 114
+#define IMX6UL_CLK_LCDIF_PODF 115
+#define IMX6UL_CLK_SIM_PODF 116
+#define IMX6UL_CLK_QSPI1_PDOF 117
+#define IMX6UL_CLK_ENFC_PRED 118
+#define IMX6UL_CLK_ENFC_PODF 119
+#define IMX6UL_CLK_CAN_PODF 120
+#define IMX6UL_CLK_ECSPI_PODF 121
+#define IMX6UL_CLK_UART_PODF 122
+#define IMX6UL_CLK_ADC1 123
+#define IMX6UL_CLK_ADC2 124
+#define IMX6UL_CLK_AIPSTZ1 125
+#define IMX6UL_CLK_AIPSTZ2 126
+#define IMX6UL_CLK_AIPSTZ3 127
+#define IMX6UL_CLK_APBHDMA 128
+#define IMX6UL_CLK_ASRC_IPG 129
+#define IMX6UL_CLK_ASRC_MEM 130
+#define IMX6UL_CLK_GPMI_BCH_APB 131
+#define IMX6UL_CLK_GPMI_BCH 132
+#define IMX6UL_CLK_GPMI_IO 133
+#define IMX6UL_CLK_GPMI_APB 134
+#define IMX6UL_CLK_CAAM_MEM 135
+#define IMX6UL_CLK_CAAM_ACLK 136
+#define IMX6UL_CLK_CAAM_IPG 137
+#define IMX6UL_CLK_CSI 138
+#define IMX6UL_CLK_ECSPI1 139
+#define IMX6UL_CLK_ECSPI2 140
+#define IMX6UL_CLK_ECSPI3 141
+#define IMX6UL_CLK_ECSPI4 142
+#define IMX6UL_CLK_EIM 143
+#define IMX6UL_CLK_ENET 144
+#define IMX6UL_CLK_ENET_AHB 145
+#define IMX6UL_CLK_EPIT1 146
+#define IMX6UL_CLK_EPIT2 147
+#define IMX6UL_CLK_CAN1_IPG 148
+#define IMX6UL_CLK_CAN1_SERIAL 149
+#define IMX6UL_CLK_CAN2_IPG 150
+#define IMX6UL_CLK_CAN2_SERIAL 151
+#define IMX6UL_CLK_GPT1_BUS 152
+#define IMX6UL_CLK_GPT1_SERIAL 153
+#define IMX6UL_CLK_GPT2_BUS 154
+#define IMX6UL_CLK_GPT2_SERIAL 155
+#define IMX6UL_CLK_I2C1 156
+#define IMX6UL_CLK_I2C2 157
+#define IMX6UL_CLK_I2C3 158
+#define IMX6UL_CLK_I2C4 159
+#define IMX6UL_CLK_IOMUXC 160
+#define IMX6UL_CLK_LCDIF_APB 161
+#define IMX6UL_CLK_LCDIF_PIX 162
+#define IMX6UL_CLK_MMDC_P0_FAST 163
+#define IMX6UL_CLK_MMDC_P0_IPG 164
+#define IMX6UL_CLK_OCOTP 165
+#define IMX6UL_CLK_OCRAM 166
+#define IMX6UL_CLK_PWM1 167
+#define IMX6UL_CLK_PWM2 168
+#define IMX6UL_CLK_PWM3 169
+#define IMX6UL_CLK_PWM4 170
+#define IMX6UL_CLK_PWM5 171
+#define IMX6UL_CLK_PWM6 172
+#define IMX6UL_CLK_PWM7 173
+#define IMX6UL_CLK_PWM8 174
+#define IMX6UL_CLK_PXP 175
+#define IMX6UL_CLK_QSPI 176
+#define IMX6UL_CLK_ROM 177
+#define IMX6UL_CLK_SAI1 178
+#define IMX6UL_CLK_SAI1_IPG 179
+#define IMX6UL_CLK_SAI2 180
+#define IMX6UL_CLK_SAI2_IPG 181
+#define IMX6UL_CLK_SAI3 182
+#define IMX6UL_CLK_SAI3_IPG 183
+#define IMX6UL_CLK_SDMA 184
+#define IMX6UL_CLK_SIM 185
+#define IMX6UL_CLK_SIM_S 186
+#define IMX6UL_CLK_SPBA 187
+#define IMX6UL_CLK_SPDIF 188
+#define IMX6UL_CLK_UART1_IPG 189
+#define IMX6UL_CLK_UART1_SERIAL 190
+#define IMX6UL_CLK_UART2_IPG 191
+#define IMX6UL_CLK_UART2_SERIAL 192
+#define IMX6UL_CLK_UART3_IPG 193
+#define IMX6UL_CLK_UART3_SERIAL 194
+#define IMX6UL_CLK_UART4_IPG 195
+#define IMX6UL_CLK_UART4_SERIAL 196
+#define IMX6UL_CLK_UART5_IPG 197
+#define IMX6UL_CLK_UART5_SERIAL 198
+#define IMX6UL_CLK_UART6_IPG 199
+#define IMX6UL_CLK_UART6_SERIAL 200
+#define IMX6UL_CLK_UART7_IPG 201
+#define IMX6UL_CLK_UART7_SERIAL 202
+#define IMX6UL_CLK_UART8_IPG 203
+#define IMX6UL_CLK_UART8_SERIAL 204
+#define IMX6UL_CLK_USBOH3 205
+#define IMX6UL_CLK_USDHC1 206
+#define IMX6UL_CLK_USDHC2 207
+#define IMX6UL_CLK_WDOG1 208
+#define IMX6UL_CLK_WDOG2 209
+#define IMX6UL_CLK_WDOG3 210
+#define IMX6UL_CLK_LDB_DI0 211
+#define IMX6UL_CLK_AXI 212
+#define IMX6UL_CLK_SPDIF_GCLK 213
+#define IMX6UL_CLK_GPT_3M 214
+#define IMX6UL_CLK_SIM2 215
+#define IMX6UL_CLK_SIM1 216
+#define IMX6UL_CLK_IPP_DI0 217
+#define IMX6UL_CLK_IPP_DI1 218
+#define IMX6UL_CA7_SECONDARY_SEL 219
+#define IMX6UL_CLK_PER_BCH 220
+#define IMX6UL_CLK_CSI_SEL 221
+#define IMX6UL_CLK_CSI_PODF 222
+#define IMX6UL_CLK_PLL3_120M 223
+
+#define IMX6UL_CLK_END 224
+
+#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */
diff --git a/dts/include/dt-bindings/clock/r8a7790-clock.h b/dts/include/dt-bindings/clock/r8a7790-clock.h
index ff7ca35..7b1ad89 100644
--- a/dts/include/dt-bindings/clock/r8a7790-clock.h
+++ b/dts/include/dt-bindings/clock/r8a7790-clock.h
@@ -108,6 +108,7 @@
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
#define R8A7790_CLK_VIN0 11
+#define R8A7790_CLK_ETHERAVB 12
#define R8A7790_CLK_ETHER 13
#define R8A7790_CLK_SATA1 14
#define R8A7790_CLK_SATA0 15
@@ -143,6 +144,8 @@
#define R8A7790_CLK_SCU_ALL 17
#define R8A7790_CLK_SCU_DVC1 18
#define R8A7790_CLK_SCU_DVC0 19
+#define R8A7790_CLK_SCU_CTU1_MIX1 20
+#define R8A7790_CLK_SCU_CTU0_MIX0 21
#define R8A7790_CLK_SCU_SRC9 22
#define R8A7790_CLK_SCU_SRC8 23
#define R8A7790_CLK_SCU_SRC7 24
diff --git a/dts/include/dt-bindings/clock/r8a7791-clock.h b/dts/include/dt-bindings/clock/r8a7791-clock.h
index 4022683..dd09b73 100644
--- a/dts/include/dt-bindings/clock/r8a7791-clock.h
+++ b/dts/include/dt-bindings/clock/r8a7791-clock.h
@@ -141,6 +141,8 @@
#define R8A7791_CLK_SCU_ALL 17
#define R8A7791_CLK_SCU_DVC1 18
#define R8A7791_CLK_SCU_DVC0 19
+#define R8A7791_CLK_SCU_CTU1_MIX1 20
+#define R8A7791_CLK_SCU_CTU0_MIX0 21
#define R8A7791_CLK_SCU_SRC9 22
#define R8A7791_CLK_SCU_SRC8 23
#define R8A7791_CLK_SCU_SRC7 24
diff --git a/dts/include/dt-bindings/clock/r8a7793-clock.h b/dts/include/dt-bindings/clock/r8a7793-clock.h
new file mode 100644
index 0000000..1579e07
--- /dev/null
+++ b/dts/include/dt-bindings/clock/r8a7793-clock.h
@@ -0,0 +1,164 @@
+/*
+ * r8a7793 clock definition
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7793_H__
+#define __DT_BINDINGS_CLOCK_R8A7793_H__
+
+/* CPG */
+#define R8A7793_CLK_MAIN 0
+#define R8A7793_CLK_PLL0 1
+#define R8A7793_CLK_PLL1 2
+#define R8A7793_CLK_PLL3 3
+#define R8A7793_CLK_LB 4
+#define R8A7793_CLK_QSPI 5
+#define R8A7793_CLK_SDH 6
+#define R8A7793_CLK_SD0 7
+#define R8A7793_CLK_Z 8
+#define R8A7793_CLK_RCAN 9
+#define R8A7793_CLK_ADSP 10
+
+/* MSTP0 */
+#define R8A7793_CLK_MSIOF0 0
+
+/* MSTP1 */
+#define R8A7793_CLK_VCP0 1
+#define R8A7793_CLK_VPC0 3
+#define R8A7793_CLK_SSP1 9
+#define R8A7793_CLK_TMU1 11
+#define R8A7793_CLK_3DG 12
+#define R8A7793_CLK_2DDMAC 15
+#define R8A7793_CLK_FDP1_1 18
+#define R8A7793_CLK_FDP1_0 19
+#define R8A7793_CLK_TMU3 21
+#define R8A7793_CLK_TMU2 22
+#define R8A7793_CLK_CMT0 24
+#define R8A7793_CLK_TMU0 25
+#define R8A7793_CLK_VSP1_DU1 27
+#define R8A7793_CLK_VSP1_DU0 28
+#define R8A7793_CLK_VSP1_S 31
+
+/* MSTP2 */
+#define R8A7793_CLK_SCIFA2 2
+#define R8A7793_CLK_SCIFA1 3
+#define R8A7793_CLK_SCIFA0 4
+#define R8A7793_CLK_MSIOF2 5
+#define R8A7793_CLK_SCIFB0 6
+#define R8A7793_CLK_SCIFB1 7
+#define R8A7793_CLK_MSIOF1 8
+#define R8A7793_CLK_SCIFB2 16
+#define R8A7793_CLK_SYS_DMAC1 18
+#define R8A7793_CLK_SYS_DMAC0 19
+
+/* MSTP3 */
+#define R8A7793_CLK_TPU0 4
+#define R8A7793_CLK_SDHI2 11
+#define R8A7793_CLK_SDHI1 12
+#define R8A7793_CLK_SDHI0 14
+#define R8A7793_CLK_MMCIF0 15
+#define R8A7793_CLK_IIC0 18
+#define R8A7793_CLK_PCIEC 19
+#define R8A7793_CLK_IIC1 23
+#define R8A7793_CLK_SSUSB 28
+#define R8A7793_CLK_CMT1 29
+#define R8A7793_CLK_USBDMAC0 30
+#define R8A7793_CLK_USBDMAC1 31
+
+/* MSTP4 */
+#define R8A7793_CLK_IRQC 7
+
+/* MSTP5 */
+#define R8A7793_CLK_AUDIO_DMAC1 1
+#define R8A7793_CLK_AUDIO_DMAC0 2
+#define R8A7793_CLK_ADSP_MOD 6
+#define R8A7793_CLK_THERMAL 22
+#define R8A7793_CLK_PWM 23
+
+/* MSTP7 */
+#define R8A7793_CLK_EHCI 3
+#define R8A7793_CLK_HSUSB 4
+#define R8A7793_CLK_HSCIF2 13
+#define R8A7793_CLK_SCIF5 14
+#define R8A7793_CLK_SCIF4 15
+#define R8A7793_CLK_HSCIF1 16
+#define R8A7793_CLK_HSCIF0 17
+#define R8A7793_CLK_SCIF3 18
+#define R8A7793_CLK_SCIF2 19
+#define R8A7793_CLK_SCIF1 20
+#define R8A7793_CLK_SCIF0 21
+#define R8A7793_CLK_DU1 23
+#define R8A7793_CLK_DU0 24
+#define R8A7793_CLK_LVDS0 26
+
+/* MSTP8 */
+#define R8A7793_CLK_IPMMU_SGX 0
+#define R8A7793_CLK_VIN2 9
+#define R8A7793_CLK_VIN1 10
+#define R8A7793_CLK_VIN0 11
+#define R8A7793_CLK_ETHER 13
+#define R8A7793_CLK_SATA1 14
+#define R8A7793_CLK_SATA0 15
+
+/* MSTP9 */
+#define R8A7793_CLK_GPIO7 4
+#define R8A7793_CLK_GPIO6 5
+#define R8A7793_CLK_GPIO5 7
+#define R8A7793_CLK_GPIO4 8
+#define R8A7793_CLK_GPIO3 9
+#define R8A7793_CLK_GPIO2 10
+#define R8A7793_CLK_GPIO1 11
+#define R8A7793_CLK_GPIO0 12
+#define R8A7793_CLK_RCAN1 15
+#define R8A7793_CLK_RCAN0 16
+#define R8A7793_CLK_QSPI_MOD 17
+#define R8A7793_CLK_I2C5 25
+#define R8A7793_CLK_IICDVFS 26
+#define R8A7793_CLK_I2C4 27
+#define R8A7793_CLK_I2C3 28
+#define R8A7793_CLK_I2C2 29
+#define R8A7793_CLK_I2C1 30
+#define R8A7793_CLK_I2C0 31
+
+/* MSTP10 */
+#define R8A7793_CLK_SSI_ALL 5
+#define R8A7793_CLK_SSI9 6
+#define R8A7793_CLK_SSI8 7
+#define R8A7793_CLK_SSI7 8
+#define R8A7793_CLK_SSI6 9
+#define R8A7793_CLK_SSI5 10
+#define R8A7793_CLK_SSI4 11
+#define R8A7793_CLK_SSI3 12
+#define R8A7793_CLK_SSI2 13
+#define R8A7793_CLK_SSI1 14
+#define R8A7793_CLK_SSI0 15
+#define R8A7793_CLK_SCU_ALL 17
+#define R8A7793_CLK_SCU_DVC1 18
+#define R8A7793_CLK_SCU_DVC0 19
+#define R8A7793_CLK_SCU_SRC9 22
+#define R8A7793_CLK_SCU_SRC8 23
+#define R8A7793_CLK_SCU_SRC7 24
+#define R8A7793_CLK_SCU_SRC6 25
+#define R8A7793_CLK_SCU_SRC5 26
+#define R8A7793_CLK_SCU_SRC4 27
+#define R8A7793_CLK_SCU_SRC3 28
+#define R8A7793_CLK_SCU_SRC2 29
+#define R8A7793_CLK_SCU_SRC1 30
+#define R8A7793_CLK_SCU_SRC0 31
+
+/* MSTP11 */
+#define R8A7793_CLK_SCIFA3 6
+#define R8A7793_CLK_SCIFA4 7
+#define R8A7793_CLK_SCIFA5 8
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7793_H__ */
diff --git a/dts/include/dt-bindings/clock/rk3066a-cru.h b/dts/include/dt-bindings/clock/rk3066a-cru.h
index bc1ed1d..d3a9824 100644
--- a/dts/include/dt-bindings/clock/rk3066a-cru.h
+++ b/dts/include/dt-bindings/clock/rk3066a-cru.h
@@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3066A_H
+
#include <dt-bindings/clock/rk3188-cru-common.h>
/* soft-reset indices */
@@ -33,3 +36,5 @@
#define SRST_HDMI 96
#define SRST_HDMI_APB 97
#define SRST_CIF1 111
+
+#endif
diff --git a/dts/include/dt-bindings/clock/rk3188-cru-common.h b/dts/include/dt-bindings/clock/rk3188-cru-common.h
index 6a37050..8df77a7 100644
--- a/dts/include/dt-bindings/clock/rk3188-cru-common.h
+++ b/dts/include/dt-bindings/clock/rk3188-cru-common.h
@@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H
+
/* core clocks from */
#define PLL_APLL 1
#define PLL_DPLL 2
@@ -248,3 +251,5 @@
#define SRST_PTM1_ATB 141
#define SRST_CTM 142
#define SRST_TS 143
+
+#endif
diff --git a/dts/include/dt-bindings/clock/rk3188-cru.h b/dts/include/dt-bindings/clock/rk3188-cru.h
index 9fac8ed..9f2e631 100644
--- a/dts/include/dt-bindings/clock/rk3188-cru.h
+++ b/dts/include/dt-bindings/clock/rk3188-cru.h
@@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_H
+
#include <dt-bindings/clock/rk3188-cru-common.h>
/* soft-reset indices */
@@ -49,3 +52,5 @@
#define SRST_GPU_BRIDGE 121
#define SRST_CTI3 123
#define SRST_CTI3_APB 124
+
+#endif
diff --git a/dts/include/dt-bindings/clock/rk3288-cru.h b/dts/include/dt-bindings/clock/rk3288-cru.h
index dea4197..c719aac 100644
--- a/dts/include/dt-bindings/clock/rk3288-cru.h
+++ b/dts/include/dt-bindings/clock/rk3288-cru.h
@@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H
+
/* core clocks */
#define PLL_APLL 1
#define PLL_DPLL 2
@@ -376,3 +379,5 @@
#define SRST_TSP_CLKIN0 189
#define SRST_TSP_CLKIN1 190
#define SRST_TSP_27M 191
+
+#endif
diff --git a/dts/include/dt-bindings/clock/rk3368-cru.h b/dts/include/dt-bindings/clock/rk3368-cru.h
new file mode 100644
index 0000000..9c5dd9b
--- /dev/null
+++ b/dts/include/dt-bindings/clock/rk3368-cru.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H
+
+/* core clocks */
+#define PLL_APLLB 1
+#define PLL_APLLL 2
+#define PLL_DPLL 3
+#define PLL_CPLL 4
+#define PLL_GPLL 5
+#define PLL_NPLL 6
+#define ARMCLKB 7
+#define ARMCLKL 8
+
+/* sclk gates (special clocks) */
+#define SCLK_GPU_CORE 64
+#define SCLK_SPI0 65
+#define SCLK_SPI1 66
+#define SCLK_SPI2 67
+#define SCLK_SDMMC 68
+#define SCLK_SDIO0 69
+#define SCLK_EMMC 71
+#define SCLK_TSADC 72
+#define SCLK_SARADC 73
+#define SCLK_NANDC0 75
+#define SCLK_UART0 77
+#define SCLK_UART1 78
+#define SCLK_UART2 79
+#define SCLK_UART3 80
+#define SCLK_UART4 81
+#define SCLK_I2S_8CH 82
+#define SCLK_SPDIF_8CH 83
+#define SCLK_I2S_2CH 84
+#define SCLK_TIMER0 85
+#define SCLK_TIMER1 86
+#define SCLK_TIMER2 87
+#define SCLK_TIMER3 88
+#define SCLK_TIMER4 89
+#define SCLK_TIMER5 90
+#define SCLK_TIMER6 91
+#define SCLK_OTGPHY0 93
+#define SCLK_OTG_ADP 96
+#define SCLK_HSICPHY480M 97
+#define SCLK_HSICPHY12M 98
+#define SCLK_MACREF 99
+#define SCLK_VOP0_PWM 100
+#define SCLK_MAC_RX 102
+#define SCLK_MAC_TX 103
+#define SCLK_EDP_24M 104
+#define SCLK_EDP 105
+#define SCLK_RGA 106
+#define SCLK_ISP 107
+#define SCLK_HDCP 108
+#define SCLK_HDMI_HDCP 109
+#define SCLK_HDMI_CEC 110
+#define SCLK_HEVC_CABAC 111
+#define SCLK_HEVC_CORE 112
+#define SCLK_I2S_8CH_OUT 113
+#define SCLK_SDMMC_DRV 114
+#define SCLK_SDIO0_DRV 115
+#define SCLK_EMMC_DRV 117
+#define SCLK_SDMMC_SAMPLE 118
+#define SCLK_SDIO0_SAMPLE 119
+#define SCLK_EMMC_SAMPLE 121
+#define SCLK_USBPHY480M 122
+#define SCLK_PVTM_CORE 123
+#define SCLK_PVTM_GPU 124
+#define SCLK_PVTM_PMU 125
+#define SCLK_SFC 126
+#define SCLK_MAC 127
+#define SCLK_MACREF_OUT 128
+
+#define DCLK_VOP 190
+#define MCLK_CRYPTO 191
+
+/* aclk gates */
+#define ACLK_GPU_MEM 192
+#define ACLK_GPU_CFG 193
+#define ACLK_DMAC_BUS 194
+#define ACLK_DMAC_PERI 195
+#define ACLK_PERI_MMU 196
+#define ACLK_GMAC 197
+#define ACLK_VOP 198
+#define ACLK_VOP_IEP 199
+#define ACLK_RGA 200
+#define ACLK_HDCP 201
+#define ACLK_IEP 202
+#define ACLK_VIO0_NOC 203
+#define ACLK_VIP 204
+#define ACLK_ISP 205
+#define ACLK_VIO1_NOC 206
+#define ACLK_VIDEO 208
+#define ACLK_BUS 209
+#define ACLK_PERI 210
+
+/* pclk gates */
+#define PCLK_GPIO0 320
+#define PCLK_GPIO1 321
+#define PCLK_GPIO2 322
+#define PCLK_GPIO3 323
+#define PCLK_PMUGRF 324
+#define PCLK_MAILBOX 325
+#define PCLK_GRF 329
+#define PCLK_SGRF 330
+#define PCLK_PMU 331
+#define PCLK_I2C0 332
+#define PCLK_I2C1 333
+#define PCLK_I2C2 334
+#define PCLK_I2C3 335
+#define PCLK_I2C4 336
+#define PCLK_I2C5 337
+#define PCLK_SPI0 338
+#define PCLK_SPI1 339
+#define PCLK_SPI2 340
+#define PCLK_UART0 341
+#define PCLK_UART1 342
+#define PCLK_UART2 343
+#define PCLK_UART3 344
+#define PCLK_UART4 345
+#define PCLK_TSADC 346
+#define PCLK_SARADC 347
+#define PCLK_SIM 348
+#define PCLK_GMAC 349
+#define PCLK_PWM0 350
+#define PCLK_PWM1 351
+#define PCLK_TIMER0 353
+#define PCLK_TIMER1 354
+#define PCLK_EDP_CTRL 355
+#define PCLK_MIPI_DSI0 356
+#define PCLK_MIPI_CSI 358
+#define PCLK_HDCP 359
+#define PCLK_HDMI_CTRL 360
+#define PCLK_VIO_H2P 361
+#define PCLK_BUS 362
+#define PCLK_PERI 363
+#define PCLK_DDRUPCTL 364
+#define PCLK_DDRPHY 365
+#define PCLK_ISP 366
+#define PCLK_VIP 367
+#define PCLK_WDT 368
+
+/* hclk gates */
+#define HCLK_SFC 448
+#define HCLK_OTG0 449
+#define HCLK_HOST0 450
+#define HCLK_HOST1 451
+#define HCLK_HSIC 452
+#define HCLK_NANDC0 453
+#define HCLK_TSP 455
+#define HCLK_SDMMC 456
+#define HCLK_SDIO0 457
+#define HCLK_EMMC 459
+#define HCLK_HSADC 460
+#define HCLK_CRYPTO 461
+#define HCLK_I2S_2CH 462
+#define HCLK_I2S_8CH 463
+#define HCLK_SPDIF 464
+#define HCLK_VOP 465
+#define HCLK_ROM 467
+#define HCLK_IEP 468
+#define HCLK_ISP 469
+#define HCLK_RGA 470
+#define HCLK_VIO_AHB_ARBI 471
+#define HCLK_VIO_NOC 472
+#define HCLK_VIP 473
+#define HCLK_VIO_H2P 474
+#define HCLK_VIO_HDCPMMU 475
+#define HCLK_VIDEO 476
+#define HCLK_BUS 477
+#define HCLK_PERI 478
+
+#define CLK_NR_CLKS (HCLK_PERI + 1)
+
+/* soft-reset indices */
+#define SRST_CORE_B0 0
+#define SRST_CORE_B1 1
+#define SRST_CORE_B2 2
+#define SRST_CORE_B3 3
+#define SRST_CORE_B0_PO 4
+#define SRST_CORE_B1_PO 5
+#define SRST_CORE_B2_PO 6
+#define SRST_CORE_B3_PO 7
+#define SRST_L2_B 8
+#define SRST_ADB_B 9
+#define SRST_PD_CORE_B_NIU 10
+#define SRST_PDBUS_STRSYS 11
+#define SRST_SOCDBG_B 14
+#define SRST_CORE_B_DBG 15
+
+#define SRST_DMAC1 18
+#define SRST_INTMEM 19
+#define SRST_ROM 20
+#define SRST_SPDIF8CH 21
+#define SRST_I2S8CH 23
+#define SRST_MAILBOX 24
+#define SRST_I2S2CH 25
+#define SRST_EFUSE_256 26
+#define SRST_MCU_SYS 28
+#define SRST_MCU_PO 29
+#define SRST_MCU_NOC 30
+#define SRST_EFUSE 31
+
+#define SRST_GPIO0 32
+#define SRST_GPIO1 33
+#define SRST_GPIO2 34
+#define SRST_GPIO3 35
+#define SRST_GPIO4 36
+#define SRST_PMUGRF 41
+#define SRST_I2C0 42
+#define SRST_I2C1 43
+#define SRST_I2C2 44
+#define SRST_I2C3 45
+#define SRST_I2C4 46
+#define SRST_I2C5 47
+
+#define SRST_DWPWM 48
+#define SRST_MMC_PERI 49
+#define SRST_PERIPH_MMU 50
+#define SRST_GRF 55
+#define SRST_PMU 56
+#define SRST_PERIPH_AXI 57
+#define SRST_PERIPH_AHB 58
+#define SRST_PERIPH_APB 59
+#define SRST_PERIPH_NIU 60
+#define SRST_PDPERI_AHB_ARBI 61
+#define SRST_EMEM 62
+#define SRST_USB_PERI 63
+
+#define SRST_DMAC2 64
+#define SRST_MAC 66
+#define SRST_GPS 67
+#define SRST_RKPWM 69
+#define SRST_USBHOST0 72
+#define SRST_HSIC 73
+#define SRST_HSIC_AUX 74
+#define SRST_HSIC_PHY 75
+#define SRST_HSADC 76
+#define SRST_NANDC0 77
+#define SRST_SFC 79
+
+#define SRST_SPI0 83
+#define SRST_SPI1 84
+#define SRST_SPI2 85
+#define SRST_SARADC 87
+#define SRST_PDALIVE_NIU 88
+#define SRST_PDPMU_INTMEM 89
+#define SRST_PDPMU_NIU 90
+#define SRST_SGRF 91
+
+#define SRST_VIO_ARBI 96
+#define SRST_RGA_NIU 97
+#define SRST_VIO0_NIU_AXI 98
+#define SRST_VIO_NIU_AHB 99
+#define SRST_LCDC0_AXI 100
+#define SRST_LCDC0_AHB 101
+#define SRST_LCDC0_DCLK 102
+#define SRST_VIP 104
+#define SRST_RGA_CORE 105
+#define SRST_IEP_AXI 106
+#define SRST_IEP_AHB 107
+#define SRST_RGA_AXI 108
+#define SRST_RGA_AHB 109
+#define SRST_ISP 110
+#define SRST_EDP_24M 111
+
+#define SRST_VIDEO_AXI 112
+#define SRST_VIDEO_AHB 113
+#define SRST_MIPIDPHYTX 114
+#define SRST_MIPIDSI0 115
+#define SRST_MIPIDPHYRX 116
+#define SRST_MIPICSI 117
+#define SRST_GPU 120
+#define SRST_HDMI 121
+#define SRST_EDP 122
+#define SRST_PMU_PVTM 123
+#define SRST_CORE_PVTM 124
+#define SRST_GPU_PVTM 125
+#define SRST_GPU_SYS 126
+#define SRST_GPU_MEM_NIU 127
+
+#define SRST_MMC0 128
+#define SRST_SDIO0 129
+#define SRST_EMMC 131
+#define SRST_USBOTG_AHB 132
+#define SRST_USBOTG_PHY 133
+#define SRST_USBOTG_CON 134
+#define SRST_USBHOST0_AHB 135
+#define SRST_USBHOST0_PHY 136
+#define SRST_USBHOST0_CON 137
+#define SRST_USBOTG_UTMI 138
+#define SRST_USBHOST1_UTMI 139
+#define SRST_USB_ADP 141
+
+#define SRST_CORESIGHT 144
+#define SRST_PD_CORE_AHB_NOC 145
+#define SRST_PD_CORE_APB_NOC 146
+#define SRST_GIC 148
+#define SRST_LCDC_PWM0 149
+#define SRST_RGA_H2P_BRG 153
+#define SRST_VIDEO 154
+#define SRST_GPU_CFG_NIU 157
+#define SRST_TSADC 159
+
+#define SRST_DDRPHY0 160
+#define SRST_DDRPHY0_APB 161
+#define SRST_DDRCTRL0 162
+#define SRST_DDRCTRL0_APB 163
+#define SRST_VIDEO_NIU 165
+#define SRST_VIDEO_NIU_AHB 167
+#define SRST_DDRMSCH0 170
+#define SRST_PDBUS_AHB 173
+#define SRST_CRYPTO 174
+
+#define SRST_UART0 179
+#define SRST_UART1 180
+#define SRST_UART2 181
+#define SRST_UART3 182
+#define SRST_UART4 183
+#define SRST_SIMC 186
+#define SRST_TSP 188
+#define SRST_TSP_CLKIN0 189
+
+#define SRST_CORE_L0 192
+#define SRST_CORE_L1 193
+#define SRST_CORE_L2 194
+#define SRST_CORE_L3 195
+#define SRST_CORE_L0_PO 195
+#define SRST_CORE_L1_PO 197
+#define SRST_CORE_L2_PO 198
+#define SRST_CORE_L3_PO 199
+#define SRST_L2_L 200
+#define SRST_ADB_L 201
+#define SRST_PD_CORE_L_NIU 202
+#define SRST_CCI_SYS 203
+#define SRST_CCI_DDR 204
+#define SRST_CCI 205
+#define SRST_SOCDBG_L 206
+#define SRST_CORE_L_DBG 207
+
+#define SRST_CORE_B0_NC 208
+#define SRST_CORE_B0_PO_NC 209
+#define SRST_L2_B_NC 210
+#define SRST_ADB_B_NC 211
+#define SRST_PD_CORE_B_NIU_NC 212
+#define SRST_PDBUS_STRSYS_NC 213
+#define SRST_CORE_L0_NC 214
+#define SRST_CORE_L0_PO_NC 215
+#define SRST_L2_L_NC 216
+#define SRST_ADB_L_NC 217
+#define SRST_PD_CORE_L_NIU_NC 218
+#define SRST_CCI_SYS_NC 219
+#define SRST_CCI_DDR_NC 220
+#define SRST_CCI_NC 221
+#define SRST_TRACE_NC 222
+
+#define SRST_TIMER00 224
+#define SRST_TIMER01 225
+#define SRST_TIMER02 226
+#define SRST_TIMER03 227
+#define SRST_TIMER04 228
+#define SRST_TIMER05 229
+#define SRST_TIMER10 230
+#define SRST_TIMER11 231
+#define SRST_TIMER12 232
+#define SRST_TIMER13 233
+#define SRST_TIMER14 234
+#define SRST_TIMER15 235
+#define SRST_TIMER0_APB 236
+#define SRST_TIMER1_APB 237
+
+#endif
diff --git a/dts/include/dt-bindings/clock/zx296702-clock.h b/dts/include/dt-bindings/clock/zx296702-clock.h
index e683dbb..26ee564 100644
--- a/dts/include/dt-bindings/clock/zx296702-clock.h
+++ b/dts/include/dt-bindings/clock/zx296702-clock.h
@@ -153,7 +153,16 @@
#define ZX296702_I2S0_WCLK 9
#define ZX296702_I2S0_PCLK 10
#define ZX296702_I2S0_DIV 11
-#define ZX296702_LSP0CLK_END 12
+#define ZX296702_I2S1_WCLK_MUX 12
+#define ZX296702_I2S1_WCLK 13
+#define ZX296702_I2S1_PCLK 14
+#define ZX296702_I2S1_DIV 15
+#define ZX296702_I2S2_WCLK_MUX 16
+#define ZX296702_I2S2_WCLK 17
+#define ZX296702_I2S2_PCLK 18
+#define ZX296702_I2S2_DIV 19
+#define ZX296702_GPIO_CLK 20
+#define ZX296702_LSP0CLK_END 21
#define ZX296702_UART0_WCLK_MUX 0
#define ZX296702_UART0_WCLK 1
@@ -165,6 +174,10 @@
#define ZX296702_SDMMC0_WCLK_DIV 7
#define ZX296702_SDMMC0_WCLK 8
#define ZX296702_SDMMC0_PCLK 9
-#define ZX296702_LSP1CLK_END 10
+#define ZX296702_SPDIF1_WCLK_MUX 10
+#define ZX296702_SPDIF1_WCLK 11
+#define ZX296702_SPDIF1_PCLK 12
+#define ZX296702_SPDIF1_DIV 13
+#define ZX296702_LSP1CLK_END 14
#endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
diff --git a/dts/include/dt-bindings/dma/axi-dmac.h b/dts/include/dt-bindings/dma/axi-dmac.h
new file mode 100644
index 0000000..ad9e6ec
--- /dev/null
+++ b/dts/include/dt-bindings/dma/axi-dmac.h
@@ -0,0 +1,48 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __DT_BINDINGS_DMA_AXI_DMAC_H__
+#define __DT_BINDINGS_DMA_AXI_DMAC_H__
+
+#define AXI_DMAC_BUS_TYPE_AXI_MM 0
+#define AXI_DMAC_BUS_TYPE_AXI_STREAM 1
+#define AXI_DMAC_BUS_TYPE_FIFO 2
+
+#endif
diff --git a/dts/include/dt-bindings/dma/jz4780-dma.h b/dts/include/dt-bindings/dma/jz4780-dma.h
deleted file mode 100644
index df017fd..0000000
--- a/dts/include/dt-bindings/dma/jz4780-dma.h
+++ /dev/null
@@ -1,49 +0,0 @@
-#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
-#define __DT_BINDINGS_DMA_JZ4780_DMA_H__
-
-/*
- * Request type numbers for the JZ4780 DMA controller (written to the DRTn
- * register for the channel).
- */
-#define JZ4780_DMA_I2S1_TX 0x4
-#define JZ4780_DMA_I2S1_RX 0x5
-#define JZ4780_DMA_I2S0_TX 0x6
-#define JZ4780_DMA_I2S0_RX 0x7
-#define JZ4780_DMA_AUTO 0x8
-#define JZ4780_DMA_SADC_RX 0x9
-#define JZ4780_DMA_UART4_TX 0xc
-#define JZ4780_DMA_UART4_RX 0xd
-#define JZ4780_DMA_UART3_TX 0xe
-#define JZ4780_DMA_UART3_RX 0xf
-#define JZ4780_DMA_UART2_TX 0x10
-#define JZ4780_DMA_UART2_RX 0x11
-#define JZ4780_DMA_UART1_TX 0x12
-#define JZ4780_DMA_UART1_RX 0x13
-#define JZ4780_DMA_UART0_TX 0x14
-#define JZ4780_DMA_UART0_RX 0x15
-#define JZ4780_DMA_SSI0_TX 0x16
-#define JZ4780_DMA_SSI0_RX 0x17
-#define JZ4780_DMA_SSI1_TX 0x18
-#define JZ4780_DMA_SSI1_RX 0x19
-#define JZ4780_DMA_MSC0_TX 0x1a
-#define JZ4780_DMA_MSC0_RX 0x1b
-#define JZ4780_DMA_MSC1_TX 0x1c
-#define JZ4780_DMA_MSC1_RX 0x1d
-#define JZ4780_DMA_MSC2_TX 0x1e
-#define JZ4780_DMA_MSC2_RX 0x1f
-#define JZ4780_DMA_PCM0_TX 0x20
-#define JZ4780_DMA_PCM0_RX 0x21
-#define JZ4780_DMA_SMB0_TX 0x24
-#define JZ4780_DMA_SMB0_RX 0x25
-#define JZ4780_DMA_SMB1_TX 0x26
-#define JZ4780_DMA_SMB1_RX 0x27
-#define JZ4780_DMA_SMB2_TX 0x28
-#define JZ4780_DMA_SMB2_RX 0x29
-#define JZ4780_DMA_SMB3_TX 0x2a
-#define JZ4780_DMA_SMB3_RX 0x2b
-#define JZ4780_DMA_SMB4_TX 0x2c
-#define JZ4780_DMA_SMB4_RX 0x2d
-#define JZ4780_DMA_DES_TX 0x2e
-#define JZ4780_DMA_DES_RX 0x2f
-
-#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */
diff --git a/dts/include/dt-bindings/i2c/i2c.h b/dts/include/dt-bindings/i2c/i2c.h
new file mode 100644
index 0000000..1d5da81
--- /dev/null
+++ b/dts/include/dt-bindings/i2c/i2c.h
@@ -0,0 +1,18 @@
+/*
+ * This header provides constants for I2C bindings
+ *
+ * Copyright (C) 2015 by Sang Engineering
+ * Copyright (C) 2015 by Renesas Electronics Corporation
+ *
+ * Wolfram Sang <wsa@sang-engineering.com>
+ *
+ * GPLv2 only
+ */
+
+#ifndef _DT_BINDINGS_I2C_I2C_H
+#define _DT_BINDINGS_I2C_I2C_H
+
+#define I2C_TEN_BIT_ADDRESS (1 << 31)
+#define I2C_OWN_SLAVE_ADDRESS (1 << 30)
+
+#endif
diff --git a/dts/include/dt-bindings/leds/leds-ns2.h b/dts/include/dt-bindings/leds/leds-ns2.h
new file mode 100644
index 0000000..491c5f9
--- /dev/null
+++ b/dts/include/dt-bindings/leds/leds-ns2.h
@@ -0,0 +1,8 @@
+#ifndef _DT_BINDINGS_LEDS_NS2_H
+#define _DT_BINDINGS_LEDS_NS2_H
+
+#define NS_V2_LED_OFF 0
+#define NS_V2_LED_ON 1
+#define NS_V2_LED_SATA 2
+
+#endif
diff --git a/dts/include/dt-bindings/media/c8sectpfe.h b/dts/include/dt-bindings/media/c8sectpfe.h
new file mode 100644
index 0000000..a0b5c7b
--- /dev/null
+++ b/dts/include/dt-bindings/media/c8sectpfe.h
@@ -0,0 +1,12 @@
+#ifndef __DT_C8SECTPFE_H
+#define __DT_C8SECTPFE_H
+
+#define STV0367_TDA18212_NIMA_1 0
+#define STV0367_TDA18212_NIMA_2 1
+#define STV0367_TDA18212_NIMB_1 2
+#define STV0367_TDA18212_NIMB_2 3
+
+#define STV0903_6110_LNB24_NIMA 4
+#define STV0903_6110_LNB24_NIMB 5
+
+#endif /* __DT_C8SECTPFE_H */
diff --git a/dts/include/dt-bindings/memory/tegra210-mc.h b/dts/include/dt-bindings/memory/tegra210-mc.h
new file mode 100644
index 0000000..d1731bc
--- /dev/null
+++ b/dts/include/dt-bindings/memory/tegra210-mc.h
@@ -0,0 +1,36 @@
+#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
+#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
+
+#define TEGRA_SWGROUP_PTC 0
+#define TEGRA_SWGROUP_DC 1
+#define TEGRA_SWGROUP_DCB 2
+#define TEGRA_SWGROUP_AFI 3
+#define TEGRA_SWGROUP_AVPC 4
+#define TEGRA_SWGROUP_HDA 5
+#define TEGRA_SWGROUP_HC 6
+#define TEGRA_SWGROUP_NVENC 7
+#define TEGRA_SWGROUP_PPCS 8
+#define TEGRA_SWGROUP_SATA 9
+#define TEGRA_SWGROUP_MPCORE 10
+#define TEGRA_SWGROUP_ISP2 11
+#define TEGRA_SWGROUP_XUSB_HOST 12
+#define TEGRA_SWGROUP_XUSB_DEV 13
+#define TEGRA_SWGROUP_ISP2B 14
+#define TEGRA_SWGROUP_TSEC 15
+#define TEGRA_SWGROUP_A9AVP 16
+#define TEGRA_SWGROUP_GPU 17
+#define TEGRA_SWGROUP_SDMMC1A 18
+#define TEGRA_SWGROUP_SDMMC2A 19
+#define TEGRA_SWGROUP_SDMMC3A 20
+#define TEGRA_SWGROUP_SDMMC4A 21
+#define TEGRA_SWGROUP_VIC 22
+#define TEGRA_SWGROUP_VI 23
+#define TEGRA_SWGROUP_NVDEC 24
+#define TEGRA_SWGROUP_APE 25
+#define TEGRA_SWGROUP_NVJPG 26
+#define TEGRA_SWGROUP_SE 27
+#define TEGRA_SWGROUP_AXIAP 28
+#define TEGRA_SWGROUP_ETR 29
+#define TEGRA_SWGROUP_TSECB 30
+
+#endif
diff --git a/dts/include/dt-bindings/mfd/st-lpc.h b/dts/include/dt-bindings/mfd/st-lpc.h
index e3e6c75..d05894a 100644
--- a/dts/include/dt-bindings/mfd/st-lpc.h
+++ b/dts/include/dt-bindings/mfd/st-lpc.h
@@ -11,5 +11,6 @@
#define ST_LPC_MODE_RTC 0
#define ST_LPC_MODE_WDT 1
+#define ST_LPC_MODE_CLKSRC 2
#endif /* __DT_BINDINGS_ST_LPC_H__ */
diff --git a/dts/include/dt-bindings/pinctrl/am43xx.h b/dts/include/dt-bindings/pinctrl/am43xx.h
index b00bbc9..774dc1e 100644
--- a/dts/include/dt-bindings/pinctrl/am43xx.h
+++ b/dts/include/dt-bindings/pinctrl/am43xx.h
@@ -14,6 +14,7 @@
#define MUX_MODE6 6
#define MUX_MODE7 7
#define MUX_MODE8 8
+#define MUX_MODE9 9
#define PULL_DISABLE (1 << 16)
#define PULL_UP (1 << 17)
diff --git a/dts/include/dt-bindings/pinctrl/dra.h b/dts/include/dt-bindings/pinctrl/dra.h
index 7448edf..4379e29 100644
--- a/dts/include/dt-bindings/pinctrl/dra.h
+++ b/dts/include/dt-bindings/pinctrl/dra.h
@@ -30,6 +30,26 @@
#define MUX_MODE14 0xe
#define MUX_MODE15 0xf
+/* Certain pins need virtual mode, but note: they may glitch */
+#define MUX_VIRTUAL_MODE0 (MODE_SELECT | (0x0 << 4))
+#define MUX_VIRTUAL_MODE1 (MODE_SELECT | (0x1 << 4))
+#define MUX_VIRTUAL_MODE2 (MODE_SELECT | (0x2 << 4))
+#define MUX_VIRTUAL_MODE3 (MODE_SELECT | (0x3 << 4))
+#define MUX_VIRTUAL_MODE4 (MODE_SELECT | (0x4 << 4))
+#define MUX_VIRTUAL_MODE5 (MODE_SELECT | (0x5 << 4))
+#define MUX_VIRTUAL_MODE6 (MODE_SELECT | (0x6 << 4))
+#define MUX_VIRTUAL_MODE7 (MODE_SELECT | (0x7 << 4))
+#define MUX_VIRTUAL_MODE8 (MODE_SELECT | (0x8 << 4))
+#define MUX_VIRTUAL_MODE9 (MODE_SELECT | (0x9 << 4))
+#define MUX_VIRTUAL_MODE10 (MODE_SELECT | (0xa << 4))
+#define MUX_VIRTUAL_MODE11 (MODE_SELECT | (0xb << 4))
+#define MUX_VIRTUAL_MODE12 (MODE_SELECT | (0xc << 4))
+#define MUX_VIRTUAL_MODE13 (MODE_SELECT | (0xd << 4))
+#define MUX_VIRTUAL_MODE14 (MODE_SELECT | (0xe << 4))
+#define MUX_VIRTUAL_MODE15 (MODE_SELECT | (0xf << 4))
+
+#define MODE_SELECT (1 << 8)
+
#define PULL_ENA (0 << 16)
#define PULL_DIS (1 << 16)
#define PULL_UP (1 << 17)
diff --git a/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h b/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
index c102054..a15c170 100644
--- a/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
+++ b/dts/include/dt-bindings/pinctrl/qcom,pmic-mpp.h
@@ -7,6 +7,47 @@
#define _DT_BINDINGS_PINCTRL_QCOM_PMIC_MPP_H
/* power-source */
+
+/* Digital Input/Output: level [PM8058] */
+#define PM8058_MPP_VPH 0
+#define PM8058_MPP_S3 1
+#define PM8058_MPP_L2 2
+#define PM8058_MPP_L3 3
+
+/* Digital Input/Output: level [PM8901] */
+#define PM8901_MPP_MSMIO 0
+#define PM8901_MPP_DIG 1
+#define PM8901_MPP_L5 2
+#define PM8901_MPP_S4 3
+#define PM8901_MPP_VPH 4
+
+/* Digital Input/Output: level [PM8921] */
+#define PM8921_MPP_S4 1
+#define PM8921_MPP_L15 3
+#define PM8921_MPP_L17 4
+#define PM8921_MPP_VPH 7
+
+/* Digital Input/Output: level [PM8821] */
+#define PM8821_MPP_1P8 0
+#define PM8821_MPP_VPH 7
+
+/* Digital Input/Output: level [PM8018] */
+#define PM8018_MPP_L4 0
+#define PM8018_MPP_L14 1
+#define PM8018_MPP_S3 2
+#define PM8018_MPP_L6 3
+#define PM8018_MPP_L2 4
+#define PM8018_MPP_L5 5
+#define PM8018_MPP_VPH 7
+
+/* Digital Input/Output: level [PM8038] */
+#define PM8038_MPP_L20 0
+#define PM8038_MPP_L11 1
+#define PM8038_MPP_L5 2
+#define PM8038_MPP_L15 3
+#define PM8038_MPP_L17 4
+#define PM8038_MPP_VPH 7
+
#define PM8841_MPP_VPH 0
#define PM8841_MPP_S3 2
@@ -37,6 +78,16 @@
#define PMIC_MPP_AMUX_ROUTE_ABUS3 6
#define PMIC_MPP_AMUX_ROUTE_ABUS4 7
+/* Analog Output: level */
+#define PMIC_MPP_AOUT_LVL_1V25 0
+#define PMIC_MPP_AOUT_LVL_1V25_2 1
+#define PMIC_MPP_AOUT_LVL_0V625 2
+#define PMIC_MPP_AOUT_LVL_0V3125 3
+#define PMIC_MPP_AOUT_LVL_MPP 4
+#define PMIC_MPP_AOUT_LVL_ABUS1 5
+#define PMIC_MPP_AOUT_LVL_ABUS2 6
+#define PMIC_MPP_AOUT_LVL_ABUS3 7
+
/* To be used with "function" */
#define PMIC_MPP_FUNC_NORMAL "normal"
#define PMIC_MPP_FUNC_PAIRED "paired"
diff --git a/dts/include/dt-bindings/power/mt8173-power.h b/dts/include/dt-bindings/power/mt8173-power.h
new file mode 100644
index 0000000..b34cee9
--- /dev/null
+++ b/dts/include/dt-bindings/power/mt8173-power.h
@@ -0,0 +1,15 @@
+#ifndef _DT_BINDINGS_POWER_MT8183_POWER_H
+#define _DT_BINDINGS_POWER_MT8183_POWER_H
+
+#define MT8173_POWER_DOMAIN_VDEC 0
+#define MT8173_POWER_DOMAIN_VENC 1
+#define MT8173_POWER_DOMAIN_ISP 2
+#define MT8173_POWER_DOMAIN_MM 3
+#define MT8173_POWER_DOMAIN_VENC_LT 4
+#define MT8173_POWER_DOMAIN_AUDIO 5
+#define MT8173_POWER_DOMAIN_USB 6
+#define MT8173_POWER_DOMAIN_MFG_ASYNC 7
+#define MT8173_POWER_DOMAIN_MFG_2D 8
+#define MT8173_POWER_DOMAIN_MFG 9
+
+#endif /* _DT_BINDINGS_POWER_MT8183_POWER_H */
diff --git a/dts/include/dt-bindings/reset/altr,rst-mgr-a10.h b/dts/include/dt-bindings/reset/altr,rst-mgr-a10.h
new file mode 100644
index 0000000..acb0bbf
--- /dev/null
+++ b/dts/include/dt-bindings/reset/altr,rst-mgr-a10.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014, Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+#define _DT_BINDINGS_RESET_ALTR_RST_MGR_A10_H
+
+/* MPUMODRST */
+#define CPU0_RESET 0
+#define CPU1_RESET 1
+#define WDS_RESET 2
+#define SCUPER_RESET 3
+
+/* PER0MODRST */
+#define EMAC0_RESET 32
+#define EMAC1_RESET 33
+#define EMAC2_RESET 34
+#define USB0_RESET 35
+#define USB1_RESET 36
+#define NAND_RESET 37
+#define QSPI_RESET 38
+#define SDMMC_RESET 39
+#define EMAC0_OCP_RESET 40
+#define EMAC1_OCP_RESET 41
+#define EMAC2_OCP_RESET 42
+#define USB0_OCP_RESET 43
+#define USB1_OCP_RESET 44
+#define NAND_OCP_RESET 45
+#define QSPI_OCP_RESET 46
+#define SDMMC_OCP_RESET 47
+#define DMA_RESET 48
+#define SPIM0_RESET 49
+#define SPIM1_RESET 50
+#define SPIS0_RESET 51
+#define SPIS1_RESET 52
+#define DMA_OCP_RESET 53
+#define EMAC_PTP_RESET 54
+/* 55 is empty*/
+#define DMAIF0_RESET 56
+#define DMAIF1_RESET 57
+#define DMAIF2_RESET 58
+#define DMAIF3_RESET 59
+#define DMAIF4_RESET 60
+#define DMAIF5_RESET 61
+#define DMAIF6_RESET 62
+#define DMAIF7_RESET 63
+
+/* PER1MODRST */
+#define L4WD0_RESET 64
+#define L4WD1_RESET 65
+#define L4SYSTIMER0_RESET 66
+#define L4SYSTIMER1_RESET 67
+#define SPTIMER0_RESET 68
+#define SPTIMER1_RESET 69
+/* 70-71 is reserved */
+#define I2C0_RESET 72
+#define I2C1_RESET 73
+#define I2C2_RESET 74
+#define I2C3_RESET 75
+#define I2C4_RESET 76
+/* 77-79 is reserved */
+#define UART0_RESET 80
+#define UART1_RESET 81
+/* 82-87 is reserved */
+#define GPIO0_RESET 88
+#define GPIO1_RESET 89
+#define GPIO2_RESET 90
+
+/* BRGMODRST */
+#define HPS2FPGA_RESET 96
+#define LWHPS2FPGA_RESET 97
+#define FPGA2HPS_RESET 98
+#define F2SSDRAM0_RESET 99
+#define F2SSDRAM1_RESET 100
+#define F2SSDRAM2_RESET 101
+#define DDRSCH_RESET 102
+
+/* SYSMODRST*/
+#define ROM_RESET 128
+#define OCRAM_RESET 129
+/* 130 is reserved */
+#define FPGAMGR_RESET 131
+#define S2F_RESET 132
+#define SYSDBG_RESET 133
+#define OCRAM_OCP_RESET 134
+
+/* COLDMODRST */
+#define CLKMGRCOLD_RESET 160
+/* 161-162 is reserved */
+#define S2FCOLD_RESET 163
+#define TIMESTAMPCOLD_RESET 164
+#define TAPCOLD_RESET 165
+#define HMCCOLD_RESET 166
+#define IOMGRCOLD_RESET 167
+
+/* NRSTMODRST */
+#define NRSTPINOE_RESET 192
+
+/* DBGMODRST */
+#define DBG_RESET 224
+#endif
diff --git a/dts/include/dt-bindings/reset-controller/stih407-resets.h b/dts/include/dt-bindings/reset/stih407-resets.h
index 02d4328..02d4328 100644
--- a/dts/include/dt-bindings/reset-controller/stih407-resets.h
+++ b/dts/include/dt-bindings/reset/stih407-resets.h
diff --git a/dts/include/dt-bindings/reset-controller/stih415-resets.h b/dts/include/dt-bindings/reset/stih415-resets.h
index c2329fe..c2329fe 100644
--- a/dts/include/dt-bindings/reset-controller/stih415-resets.h
+++ b/dts/include/dt-bindings/reset/stih415-resets.h
diff --git a/dts/include/dt-bindings/reset-controller/stih416-resets.h b/dts/include/dt-bindings/reset/stih416-resets.h
index fcf9af1..fcf9af1 100644
--- a/dts/include/dt-bindings/reset-controller/stih416-resets.h
+++ b/dts/include/dt-bindings/reset/stih416-resets.h
diff --git a/dts/include/dt-bindings/reset/tegra124-car.h b/dts/include/dt-bindings/reset/tegra124-car.h
new file mode 100644
index 0000000..070e4f6
--- /dev/null
+++ b/dts/include/dt-bindings/reset/tegra124-car.h
@@ -0,0 +1,12 @@
+/*
+ * This header provides Tegra124-specific constants for binding
+ * nvidia,tegra124-car.
+ */
+
+#ifndef _DT_BINDINGS_RESET_TEGRA124_CAR_H
+#define _DT_BINDINGS_RESET_TEGRA124_CAR_H
+
+#define TEGRA124_RESET(x) (6 * 32 + (x))
+#define TEGRA124_RST_DFLL_DVCO TEGRA124_RESET(0)
+
+#endif /* _DT_BINDINGS_RESET_TEGRA124_CAR_H */
diff --git a/dts/src/arc/axc003.dtsi b/dts/src/arc/axc003.dtsi
index 1cd5e82..846481f 100644
--- a/dts/src/arc/axc003.dtsi
+++ b/dts/src/arc/axc003.dtsi
@@ -72,12 +72,13 @@
};
/*
- * This INTC is actually connected to DW APB GPIO
- * which acts as a wire between MB INTC and CPU INTC.
- * GPIO INTC is configured in platform init code
- * and here we mimic direct connection from MB INTC to
- * CPU INTC, thus we set "interrupts = <7>" instead of
- * "interrupts = <12>"
+ * The DW APB ICTL intc on MB is connected to CPU intc via a
+ * DT "invisible" DW APB GPIO block, configured to simply pass thru
+ * interrupts - setup accordinly in platform init (plat-axs10x/ax10x.c)
+ *
+ * So here we mimic a direct connection betwen them, ignoring the
+ * ABPG GPIO. Thus set "interrupts = <24>" (DW APB GPIO to core)
+ * instead of "interrupts = <12>" (DW APB ICTL to DW APB GPIO)
*
* This intc actually resides on MB, but we move it here to
* avoid duplicating the MB dtsi file given that IRQ from
diff --git a/dts/src/arm/am335x-boneblack.dts b/dts/src/arm/am335x-boneblack.dts
index 5c42d25..eadbba3 100644
--- a/dts/src/arm/am335x-boneblack.dts
+++ b/dts/src/arm/am335x-boneblack.dts
@@ -68,16 +68,26 @@
&lcdc {
status = "okay";
+ port {
+ lcdc_0: endpoint@0 {
+ remote-endpoint = <&hdmi_0>;
+ };
+ };
};
-/ {
- hdmi {
- compatible = "ti,tilcdc,slave";
- i2c = <&i2c0>;
+&i2c0 {
+ tda19988 {
+ compatible = "nxp,tda998x";
+ reg = <0x70>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
- status = "okay";
+
+ port {
+ hdmi_0: endpoint@0 {
+ remote-endpoint = <&lcdc_0>;
+ };
+ };
};
};
diff --git a/dts/src/arm/am335x-evm.dts b/dts/src/arm/am335x-evm.dts
index 765be27..1942a5c 100644
--- a/dts/src/arm/am335x-evm.dts
+++ b/dts/src/arm/am335x-evm.dts
@@ -136,16 +136,29 @@
};
sound {
- compatible = "ti,da830-evm-audio";
- ti,model = "AM335x-EVM";
- ti,audio-codec = <&tlv320aic3106>;
- ti,mcasp-controller = <&mcasp1>;
- ti,codec-clock-rate = <12000000>;
- ti,audio-routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT",
- "LINE1L", "Line In",
- "LINE1R", "Line In";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM335x-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <12000000>;
+ };
};
};
@@ -342,7 +355,7 @@
>;
};
- am335x_evm_audio_pins: am335x_evm_audio_pins {
+ mcasp1_pins: mcasp1_pins {
pinctrl-single,pins = <
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
@@ -351,6 +364,15 @@
>;
};
+ mcasp1_pins_sleep: mcasp1_pins_sleep {
+ pinctrl-single,pins = <
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
dcan1_pins_default: dcan1_pins_default {
pinctrl-single,pins = <
0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
@@ -460,6 +482,7 @@
};
tlv320aic3106: tlv320aic3106@1b {
+ #sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
@@ -575,19 +598,21 @@
#include "tps65910.dtsi"
&mcasp1 {
- pinctrl-names = "default";
- pinctrl-0 = <&am335x_evm_audio_pins>;
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_pins_sleep>;
- status = "okay";
+ status = "okay";
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- /* 4 serializers */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 0 0 1 2
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 1 2
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
};
&tps {
diff --git a/dts/src/arm/am335x-evmsk.dts b/dts/src/arm/am335x-evmsk.dts
index 156d05e..315bb02 100644
--- a/dts/src/arm/am335x-evmsk.dts
+++ b/dts/src/arm/am335x-evmsk.dts
@@ -141,14 +141,26 @@
};
sound {
- compatible = "ti,da830-evm-audio";
- ti,model = "AM335x-EVMSK";
- ti,audio-codec = <&tlv320aic3106>;
- ti,mcasp-controller = <&mcasp1>;
- ti,codec-clock-rate = <24000000>;
- ti,audio-routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM335x-EVMSK";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <24000000>;
+ };
};
panel {
@@ -396,6 +408,15 @@
>;
};
+ mcasp1_pins_sleep: mcasp1_pins_sleep {
+ pinctrl-single,pins = <
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
mmc2_pins: pinmux_mmc2_pins {
pinctrl-single,pins = <
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
@@ -462,6 +483,7 @@
};
tlv320aic3106: tlv320aic3106@1b {
+ #sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
@@ -661,19 +683,21 @@
};
&mcasp1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcasp1_pins>;
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_pins_sleep>;
- status = "okay";
+ status = "okay";
- op-mode = <0>; /* MCASP_IIS_MODE */
- tdm-slots = <2>;
- /* 4 serializers */
- serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
- 0 0 1 2
- >;
- tx-num-evt = <32>;
- rx-num-evt = <32>;
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 1 2
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
};
&tscadc {
diff --git a/dts/src/arm/am335x-phycore-som.dtsi b/dts/src/arm/am335x-phycore-som.dtsi
new file mode 100644
index 0000000..4d28fc3
--- /dev/null
+++ b/dts/src/arm/am335x-phycore-som.dtsi
@@ -0,0 +1,368 @@
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "am33xx.dtsi"
+
+/ {
+ model = "Phytec AM335x phyCORE";
+ compatible = "phytec,am335x-phycore-som", "ti,am33xx";
+
+ aliases {
+ rtc0 = &i2c_rtc;
+ rtc1 = &rtc;
+ };
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&vdd1_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ };
+};
+
+/* Crypto Module */
+&aes {
+ status = "okay";
+};
+
+&sham {
+ status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+ ethernet0_pins: pinmux_ethernet0 {
+ pinctrl-single,pins = <
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
+ 0x114 (PIN_OUTPUT | MUX_MODE1) /* mii1_txen.rmii1_txen */
+ 0x124 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
+ 0x128 (PIN_OUTPUT | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
+ >;
+ };
+
+ mdio_pins: pinmux_mdio {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "rmii";
+ dual_emac_res_vlan = <1>;
+};
+
+&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+ status = "okay";
+};
+
+&mac {
+ slaves = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ethernet0_pins>;
+ status = "okay";
+};
+
+&phy_sel {
+ rmii-clock-ext;
+};
+
+/* I2C Busses */
+&am33xx_pinmux {
+ i2c0_pins: pinmux_i2c0 {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ tps: pmic@2d {
+ reg = <0x2d>;
+ };
+
+ i2c_eeprom: eeprom@52 {
+ compatible = "atmel,24c32";
+ pagesize = <32>;
+ reg = <0x52>;
+ status = "disabled";
+ };
+
+ i2c_rtc: rtc@68 {
+ compatible = "rv4162";
+ reg = <0x68>;
+ status = "disabled";
+ };
+};
+
+/* NAND memory */
+&am33xx_pinmux {
+ nandflash_pins: pinmux_nandflash {
+ pinctrl-single,pins = <
+ 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
+ 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
+ 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
+ 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
+ 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
+ 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
+ 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
+ 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
+ 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
+ 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
+ >;
+ };
+};
+
+&elm {
+ status = "okay";
+};
+
+&gpmc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nandflash_pins>;
+ ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
+ nandflash: nand@0,0 {
+ reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
+ nand-bus-width = <8>;
+ ti,nand-ecc-opt = "bch8";
+ gpmc,device-nand = "true";
+ gpmc,device-width = <1>;
+ gpmc,sync-clk-ps = <0>;
+ gpmc,cs-on-ns = <0>;
+ gpmc,cs-rd-off-ns = <30>;
+ gpmc,cs-wr-off-ns = <30>;
+ gpmc,adv-on-ns = <0>;
+ gpmc,adv-rd-off-ns = <30>;
+ gpmc,adv-wr-off-ns = <30>;
+ gpmc,we-on-ns = <0>;
+ gpmc,we-off-ns = <20>;
+ gpmc,oe-on-ns = <10>;
+ gpmc,oe-off-ns = <30>;
+ gpmc,access-ns = <30>;
+ gpmc,rd-cycle-ns = <30>;
+ gpmc,wr-cycle-ns = <30>;
+ gpmc,wait-on-read = "true";
+ gpmc,wait-on-write = "true";
+ gpmc,bus-turnaround-ns = <0>;
+ gpmc,cycle2cycle-delay-ns = <50>;
+ gpmc,cycle2cycle-diffcsen;
+ gpmc,clk-activation-ns = <0>;
+ gpmc,wait-monitoring-ns = <0>;
+ gpmc,wr-access-ns = <30>;
+ gpmc,wr-data-mux-bus-ns = <0>;
+
+ elm_id = <&elm>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "xload";
+ reg = <0x0 0x20000>;
+ };
+ partition@1 {
+ label = "xload_backup1";
+ reg = <0x20000 0x20000>;
+ };
+ partition@2 {
+ label = "xload_backup2";
+ reg = <0x40000 0x20000>;
+ };
+ partition@3 {
+ label = "xload_backup3";
+ reg = <0x60000 0x20000>;
+ };
+ partition@4 {
+ label = "barebox";
+ reg = <0x80000 0x80000>;
+ };
+ partition@5 {
+ label = "bareboxenv";
+ reg = <0x100000 0x40000>;
+ };
+ partition@6 {
+ label = "oftree";
+ reg = <0x140000 0x40000>;
+ };
+ partition@7 {
+ label = "kernel";
+ reg = <0x180000 0x800000>;
+ };
+ partition@8 {
+ label = "root";
+ reg = <0x980000 0x0>;
+ };
+ };
+};
+
+/* Power */
+#include "tps65910.dtsi"
+
+&tps {
+ vcc1-supply = <&vbat>;
+ vcc2-supply = <&vbat>;
+ vcc3-supply = <&vbat>;
+ vcc4-supply = <&vbat>;
+ vcc5-supply = <&vbat>;
+ vcc6-supply = <&vbat>;
+ vcc7-supply = <&vbat>;
+ vccio-supply = <&vbat>;
+
+ regulators {
+ vrtc_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ vio_reg: regulator@1 {
+ regulator-always-on;
+ };
+
+ vdd1_reg: regulator@2 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1312500>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd2_reg: regulator@3 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <912500>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vdd3_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ vdig1_reg: regulator@5 {
+ regulator-name = "vdig1_1p8v";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vdig2_reg: regulator@6 {
+ regulator-always-on;
+ };
+
+ vpll_reg: regulator@7 {
+ regulator-always-on;
+ };
+
+ vdac_reg: regulator@8 {
+ regulator-always-on;
+ };
+
+ vaux1_reg: regulator@9 {
+ regulator-always-on;
+ };
+
+ vaux2_reg: regulator@10 {
+ regulator-always-on;
+ };
+
+ vaux33_reg: regulator@11 {
+ regulator-always-on;
+ };
+
+ vmmc_reg: regulator@12 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+};
+
+&vbat {
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+};
+
+/* SPI Busses */
+&am33xx_pinmux {
+ spi0_pins: pinmux_spi0 {
+ pinctrl-single,pins = <
+ 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_clk.spi0_clk */
+ 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* spi0_d0.spi0_d0 */
+ 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
+ 0x15c (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
+ >;
+ };
+};
+
+&spi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ status = "okay";
+
+ serial_flash: m25p80@0 {
+ compatible = "m25p80";
+ spi-max-frequency = <48000000>;
+ reg = <0x0>;
+ m25p,fast-read;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "xload";
+ reg = <0x0 0x20000>;
+ };
+ partition@1 {
+ label = "barebox";
+ reg = <0x20000 0x80000>;
+ };
+ partition@2 {
+ label = "bareboxenv";
+ reg = <0xa0000 0x20000>;
+ };
+ partition@3 {
+ label = "oftree";
+ reg = <0xc0000 0x20000>;
+ };
+ partition@4 {
+ label = "kernel";
+ reg = <0xe0000 0x0>;
+ };
+ };
+};
diff --git a/dts/src/arm/am335x-wega-rdk.dts b/dts/src/arm/am335x-wega-rdk.dts
new file mode 100644
index 0000000..6431b7d
--- /dev/null
+++ b/dts/src/arm/am335x-wega-rdk.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-wega.dtsi"
+
+/* SoM */
+&i2c_eeprom {
+ status = "okay";
+};
+
+&i2c_rtc {
+ status = "okay";
+};
diff --git a/dts/src/arm/am335x-wega.dtsi b/dts/src/arm/am335x-wega.dtsi
new file mode 100644
index 0000000..5e541bd
--- /dev/null
+++ b/dts/src/arm/am335x-wega.dtsi
@@ -0,0 +1,151 @@
+/*
+ * Copyright (C) 2015 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ model = "Phytec AM335x phyBOARD-WEGA";
+ compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
+
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+ dcan1_pins: pinmux_dcan1 {
+ pinctrl-single,pins = <
+ 0x168 (PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
+ 0x16c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
+ >;
+ };
+};
+
+&dcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dcan1_pins>;
+ status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+ ethernet1_pins: pinmux_ethernet1 {
+ pinctrl-single,pins = <
+ 0x40 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a0.mii2_txen */
+ 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a1.mii2_rxdv */
+ 0x48 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a2.mii2_txd3 */
+ 0x4c (PIN_OUTPUT | MUX_MODE1) /* gpmc_a3.mii2_txd2 */
+ 0x50 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a4.mii2_txd1 */
+ 0x54 (PIN_OUTPUT | MUX_MODE1) /* gpmc_a5.mii2_txd0 */
+ 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a6.mii2_txclk */
+ 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a7.mii2_rxclk */
+ 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
+ 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
+ 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
+ 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
+ 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
+ 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* gpmc_ben1.mii2_col */
+ >;
+ };
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+ dual_emac_res_vlan = <2>;
+};
+
+&mac {
+ slaves = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
+ dual_emac = <1>;
+};
+
+/* MMC */
+&am33xx_pinmux {
+ mmc1_pins: pinmux_mmc1 {
+ pinctrl-single,pins = <
+ 0x0F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
+ 0x0F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
+ 0x0F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
+ 0x0FC (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
+ 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
+ 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
+ 0x160 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
+ >;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&vmmc_reg>;
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+/* UARTs */
+&am33xx_pinmux {
+ uart0_pins: pinmux_uart0 {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ uart1_pins: pinmux_uart1_pins {
+ pinctrl-single,pins = <
+ 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
+ 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
+ 0x178 (PIN_INPUT | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
+ 0x17c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
+ >;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+/* USB */
+&cppi41dma {
+ status = "okay";
+};
+
+&usb_ctrl_mod {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&usb0 {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usb0_phy {
+ status = "okay";
+};
+
+&usb1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb1_phy {
+ status = "okay";
+};
diff --git a/dts/src/arm/am33xx.dtsi b/dts/src/arm/am33xx.dtsi
index 21fcc44..d23e252 100644
--- a/dts/src/arm/am33xx.dtsi
+++ b/dts/src/arm/am33xx.dtsi
@@ -103,6 +103,15 @@
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
+ wkup_m3: wkup_m3@100000 {
+ compatible = "ti,am3352-wkup-m3";
+ reg = <0x100000 0x4000>,
+ <0x180000 0x2000>;
+ reg-names = "umem", "dmem";
+ ti,hwmods = "wkup_m3";
+ ti,pm-firmware = "am335x-pm-firmware.elf";
+ };
+
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
reg = <0x200000 0x4000>;
@@ -144,6 +153,14 @@
};
};
+ wkup_m3_ipc: wkup_m3_ipc@1324 {
+ compatible = "ti,am3352-wkup-m3-ipc";
+ reg = <0x1324 0x24>;
+ interrupts = <78>;
+ ti,rproc = <&wkup_m3>;
+ mboxes = <&mailbox &mbox_wkupm3>;
+ };
+
scm_clockdomains: clockdomains {
};
};
@@ -210,7 +227,7 @@
};
uart0: serial@44e09000 {
- compatible = "ti,omap3-uart";
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
@@ -221,7 +238,7 @@
};
uart1: serial@48022000 {
- compatible = "ti,omap3-uart";
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
@@ -232,7 +249,7 @@
};
uart2: serial@48024000 {
- compatible = "ti,omap3-uart";
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
@@ -243,7 +260,7 @@
};
uart3: serial@481a6000 {
- compatible = "ti,omap3-uart";
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
@@ -252,7 +269,7 @@
};
uart4: serial@481a8000 {
- compatible = "ti,omap3-uart";
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
@@ -261,7 +278,7 @@
};
uart5: serial@481aa000 {
- compatible = "ti,omap3-uart";
+ compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
@@ -700,7 +717,7 @@
};
mac: ethernet@4a100000 {
- compatible = "ti,cpsw";
+ compatible = "ti,am335x-cpsw","ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
@@ -762,14 +779,6 @@
reg = <0x40300000 0x10000>; /* 64k */
};
- wkup_m3: wkup_m3@44d00000 {
- compatible = "ti,am3353-wkup-m3";
- reg = <0x44d00000 0x4000 /* M3 UMEM */
- 0x44d80000 0x2000>; /* M3 DMEM */
- ti,hwmods = "wkup_m3";
- ti,no-reset-on-init;
- };
-
elm: elm@48080000 {
compatible = "ti,am3352-elm";
reg = <0x48080000 0x2000>;
diff --git a/dts/src/arm/am4372.dtsi b/dts/src/arm/am4372.dtsi
index ade28c7..0447c04 100644
--- a/dts/src/arm/am4372.dtsi
+++ b/dts/src/arm/am4372.dtsi
@@ -23,6 +23,11 @@
i2c1 = &i2c1;
i2c2 = &i2c2;
serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
};
@@ -59,6 +64,27 @@
interrupt-parent = <&gic>;
};
+ scu: scu@48240000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x48240000 0x100>;
+ };
+
+ global_timer: timer@48240200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x48240200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ local_timer: timer@48240600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x48240600 0x100>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
l2-cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
@@ -83,9 +109,19 @@
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
+ wkup_m3: wkup_m3@100000 {
+ compatible = "ti,am4372-wkup-m3";
+ reg = <0x100000 0x4000>,
+ <0x180000 0x2000>;
+ reg-names = "umem", "dmem";
+ ti,hwmods = "wkup_m3";
+ ti,pm-firmware = "am335x-pm-firmware.elf";
+ };
+
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
reg = <0x1f0000 0x11000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prcm_clocks: clocks {
#address-cells = <1>;
@@ -127,6 +163,14 @@
};
};
+ wkup_m3_ipc: wkup_m3_ipc@1324 {
+ compatible = "ti,am4372-wkup-m3-ipc";
+ reg = <0x1324 0x44>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ ti,rproc = <&wkup_m3>;
+ mboxes = <&mailbox &mbox_wkupm3>;
+ };
+
scm_clockdomains: clockdomains {
};
};
@@ -308,11 +352,14 @@
};
rtc: rtc@44e3e000 {
- compatible = "ti,am4372-rtc","ti,da830-rtc";
+ compatible = "ti,am4372-rtc", "ti,am3352-rtc",
+ "ti,da830-rtc";
reg = <0x44e3e000 0x1000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "rtc";
+ clocks = <&clk_32768_ck>;
+ clock-names = "int-clk";
status = "disabled";
};
@@ -527,8 +574,11 @@
#address-cells = <1>;
#size-cells = <1>;
ti,hwmods = "cpgmac0";
- clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
- clock-names = "fck", "cpts";
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
+ <&dpll_clksel_mac_clk>;
+ clock-names = "fck", "cpts", "50mclk";
+ assigned-clocks = <&dpll_clksel_mac_clk>;
+ assigned-clock-rates = <50000000>;
status = "disabled";
cpdma_channels = <8>;
ale_entries = <1024>;
@@ -865,7 +915,12 @@
usb1: usb@48390000 {
compatible = "synopsys,dwc3";
reg = <0x48390000 0x10000>;
- interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy1>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
@@ -889,7 +944,12 @@
usb2: usb@483d0000 {
compatible = "synopsys,dwc3";
reg = <0x483d0000 0x10000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "peripheral",
+ "host",
+ "otg";
phys = <&usb2_phy2>;
phy-names = "usb2-phy";
maximum-speed = "high-speed";
diff --git a/dts/src/arm/am437x-gp-evm.dts b/dts/src/arm/am437x-gp-evm.dts
index 84aa30c..22038f2 100644
--- a/dts/src/arm/am437x-gp-evm.dts
+++ b/dts/src/arm/am437x-gp-evm.dts
@@ -21,12 +21,11 @@
aliases {
display0 = &lcd0;
- serial3 = &uart3;
};
- vmmcsd_fixed: fixedregulator-sd {
+ evm_v3_3d: fixedregulator-v3_3d {
compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
+ regulator-name = "evm_v3_3d";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
@@ -83,17 +82,6 @@
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
-
- /*
- * SelLCDorHDMI, LOW to select HDMI. This is not really the
- * panel's enable GPIO, but we don't have HDMI driver support nor
- * support to switch between two displays, so using this gpio as
- * panel's enable should be safe.
- */
- enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
-
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
@@ -124,6 +112,39 @@
clock-frequency = <12000000>;
};
+ /* fixed 32k external oscillator clock */
+ clk_32k_rtc: clk_32k_rtc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ sound0: sound@0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM437x-GP-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ system-clock-frequency = <12000000>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <12000000>;
+ };
+ };
};
&am43xx_pinmux {
@@ -217,7 +238,6 @@
nand_flash_x8: nand_flash_x8 {
pinctrl-single,pins = <
- 0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
@@ -270,7 +290,7 @@
>;
};
- lcd_pins: lcd_pins {
+ display_mux_pins: display_mux_pins {
pinctrl-single,pins = <
/* GPIO 5_8 to select LCD / HDMI */
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
@@ -409,6 +429,60 @@
0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart3_rtsn.uart3_rtsn */
>;
};
+
+ mcasp1_pins: mcasp1_pins {
+ pinctrl-single,pins = <
+ 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
+ >;
+ };
+
+ mcasp1_sleep_pins: mcasp1_sleep_pins {
+ pinctrl-single,pins = <
+ 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ gpio0_pins: gpio0_pins {
+ pinctrl-single,pins = <
+ 0x26c (PIN_OUTPUT | MUX_MODE9) /* spi2_cs0.gpio0_23 SEL_eMMCorNANDn */
+ >;
+ };
+
+ emmc_pins_default: emmc_pins_default {
+ pinctrl-single,pins = <
+ 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
+ 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
+ 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
+ 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
+ 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
+ 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
+ 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
+ 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
+ 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
+ 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
+ >;
+ };
+
+ emmc_pins_sleep: emmc_pins_sleep {
+ pinctrl-single,pins = <
+ 0x00 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad0.gpio1_0 */
+ 0x04 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad1.gpio1_1 */
+ 0x08 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad2.gpio1_2 */
+ 0x0c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad3.gpio1_3 */
+ 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
+ 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
+ 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
+ 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
+ 0x80 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn1.gpio1_30 */
+ 0x84 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn2.gpio1_31 */
+ >;
+ };
};
&i2c0 {
@@ -455,6 +529,8 @@
regulator-name = "v1_0bat";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
};
dcdc6: regulator-dcdc6 {
@@ -462,6 +538,8 @@
regulator-name = "v1_8bat";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
};
ldo1: regulator-ldo1 {
@@ -521,6 +599,19 @@
};
};
};
+
+ tlv320aic3106: tlv320aic3106@1b {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3106";
+ reg = <0x1b>;
+ status = "okay";
+
+ /* Regulators */
+ IOVDD-supply = <&evm_v3_3d>; /* V3_3D -> <tps63031> EN: V1_8D -> VBAT */
+ AVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
+ DRVDD-supply = <&evm_v3_3d>; /* v3_3AUD -> V3_3D -> ... */
+ DVDD-supply = <&ldo1>; /* V1_8D -> LDO1 */
+ };
};
&epwmss0 {
@@ -542,7 +633,23 @@
};
&gpio0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_pins>;
status = "okay";
+
+ p23 {
+ gpio-hog;
+ gpios = <23 GPIO_ACTIVE_HIGH>;
+ /* SelEMMCorNAND selects between eMMC and NAND:
+ * Low: NAND
+ * High: eMMC
+ * When changing this line make sure the newly
+ * selected device node is enabled and the previously
+ * selected device node is disabled.
+ */
+ output-low;
+ line-name = "SelEMMCorNAND";
+ };
};
&gpio1 {
@@ -558,19 +665,48 @@
};
&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_mux_pins>;
status = "okay";
ti,no-reset-on-init;
+
+ p8 {
+ /*
+ * SelLCDorHDMI selects between display and audio paths:
+ * Low: HDMI display with audio via HDMI
+ * High: LCD display with analog audio via aic3111 codec
+ */
+ gpio-hog;
+ gpios = <8 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SelLCDorHDMI";
+ };
};
&mmc1 {
status = "okay";
- vmmc-supply = <&vmmcsd_fixed>;
+ vmmc-supply = <&evm_v3_3d>;
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
};
+/* eMMC sits on mmc2 */
+&mmc2 {
+ /*
+ * When enabling eMMC, disable GPMC/NAND and set
+ * SelEMMCorNAND to output-high
+ */
+ status = "disabled";
+ vmmc-supply = <&evm_v3_3d>;
+ bus-width = <8>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&emmc_pins_default>;
+ pinctrl-1 = <&emmc_pins_sleep>;
+ ti,non-removable;
+};
+
&mmc3 {
status = "okay";
/* these are on the crossbar and are outlined in the
@@ -651,6 +787,10 @@
};
&gpmc {
+ /*
+ * When enabling GPMC, disable eMMC and set
+ * SelEMMCorNAND to output-low
+ */
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
@@ -790,3 +930,27 @@
};
};
};
+
+&mcasp1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_sleep_pins>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializers */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 0 0 1 2
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
+
+&rtc {
+ clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+ clock-names = "ext-clk", "int-clk";
+ status = "okay";
+};
diff --git a/dts/src/arm/am437x-idk-evm.dts b/dts/src/arm/am437x-idk-evm.dts
index 3783442..af25801 100644
--- a/dts/src/arm/am437x-idk-evm.dts
+++ b/dts/src/arm/am437x-idk-evm.dts
@@ -110,6 +110,13 @@
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
};
};
+
+ /* fixed 32k external oscillator clock */
+ clk_32k_rtc: clk_32k_rtc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
};
&am43xx_pinmux {
@@ -394,6 +401,8 @@
};
&rtc {
+ clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+ clock-names = "ext-clk", "int-clk";
status = "okay";
};
diff --git a/dts/src/arm/am437x-sk-evm.dts b/dts/src/arm/am437x-sk-evm.dts
index c17097d..7da7c2d 100644
--- a/dts/src/arm/am437x-sk-evm.dts
+++ b/dts/src/arm/am437x-sk-evm.dts
@@ -24,6 +24,13 @@
display0 = &lcd0;
};
+ /* fixed 32k external oscillator clock */
+ clk_32k_rtc: clk_32k_rtc {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
@@ -32,14 +39,29 @@
};
sound {
- compatible = "ti,da830-evm-audio";
- ti,model = "AM437x-SK-EVM";
- ti,audio-codec = <&tlv320aic3106>;
- ti,mcasp-controller = <&mcasp1>;
- ti,codec-clock-rate = <24000000>;
- ti,audio-routing =
- "Headphone Jack", "HPLOUT",
- "Headphone Jack", "HPROUT";
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM437x-SK-EVM";
+ simple-audio-card,widgets =
+ "Headphone", "Headphone Jack",
+ "Line", "Line In";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPLOUT",
+ "Headphone Jack", "HPROUT",
+ "LINE1L", "Line In",
+ "LINE1R", "Line In";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound_master>;
+ simple-audio-card,frame-master = <&sound_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ };
+
+ sound_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3106>;
+ system-clock-frequency = <24000000>;
+ };
};
matrix_keypad: matrix_keypad@0 {
@@ -364,6 +386,15 @@
>;
};
+ mcasp1_pins_sleep: mcasp1_pins_sleep {
+ pinctrl-single,pins = <
+ 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
lcd_pins: lcd_pins {
pinctrl-single,pins = <
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
@@ -480,6 +511,7 @@
};
tlv320aic3106: tlv320aic3106@1b {
+ #sound-dai-cells = <0>;
compatible = "ti,tlv320aic3106";
reg = <0x1b>;
status = "okay";
@@ -640,8 +672,10 @@
};
&mcasp1 {
- pinctrl-names = "default";
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_pins_sleep>;
status = "okay";
@@ -670,6 +704,8 @@
};
&rtc {
+ clocks = <&clk_32k_rtc>, <&clk_32768_ck>;
+ clock-names = "ext-clk", "int-clk";
status = "okay";
};
diff --git a/dts/src/arm/am43x-epos-evm.dts b/dts/src/arm/am43x-epos-evm.dts
index 795d68a..86c2dfb 100644
--- a/dts/src/arm/am43x-epos-evm.dts
+++ b/dts/src/arm/am43x-epos-evm.dts
@@ -14,6 +14,7 @@
#include <dt-bindings/pinctrl/am43xx.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/sound/tlv320aic31xx-micbias.h>
/ {
model = "TI AM43x EPOS EVM";
@@ -31,21 +32,18 @@
enable-active-high;
};
+ vbat: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-boot-on;
+ };
+
lcd0: display {
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
label = "lcd";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
-
- /*
- * SelLCDorHDMI, LOW to select HDMI. This is not really the
- * panel's enable GPIO, but we don't have HDMI driver support nor
- * support to switch between two displays, so using this gpio as
- * panel's enable should be safe.
- */
- enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
-
panel-timing {
clock-frequency = <33000000>;
hactive = <800>;
@@ -108,6 +106,38 @@
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
+
+ sound0: sound@0 {
+ compatible = "simple-audio-card";
+ simple-audio-card,name = "AM43-EPOS-EVM";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker";
+ simple-audio-card,routing =
+ "MIC1LP", "Microphone Jack",
+ "MIC1RP", "Microphone Jack",
+ "MIC1LP", "MICBIAS",
+ "MIC1RP", "MICBIAS",
+ "Headphone Jack", "HPL",
+ "Headphone Jack", "HPR",
+ "Speaker", "SPL",
+ "Speaker", "SPR";
+ simple-audio-card,format = "dsp_b";
+ simple-audio-card,bitclock-master = <&sound0_master>;
+ simple-audio-card,frame-master = <&sound0_master>;
+ simple-audio-card,bitclock-inversion;
+
+ simple-audio-card,cpu {
+ sound-dai = <&mcasp1>;
+ system-clock-frequency = <12000000>;
+ };
+
+ sound0_master: simple-audio-card,codec {
+ sound-dai = <&tlv320aic3111>;
+ system-clock-frequency = <12000000>;
+ };
+ };
};
&am43xx_pinmux {
@@ -278,7 +308,7 @@
>;
};
- lcd_pins: lcd_pins {
+ display_mux_pins: display_mux_pins {
pinctrl-single,pins = <
/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
@@ -320,6 +350,24 @@
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
+
+ mcasp1_pins: mcasp1_pins {
+ pinctrl-single,pins = <
+ 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */
+ 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */
+ 0x1a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */
+ 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */
+ >;
+ };
+
+ mcasp1_sleep_pins: mcasp1_sleep_pins {
+ pinctrl-single,pins = <
+ 0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
};
&mmc1 {
@@ -399,6 +447,15 @@
regulator-always-on;
};
+ dcdc4: regulator-dcdc4 {
+ compatible = "ti,tps65218-dcdc4";
+ regulator-name = "vdcdc4";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
dcdc5: regulator-dcdc5 {
compatible = "ti,tps65218-dcdc5";
regulator-name = "v1_0bat";
@@ -441,6 +498,23 @@
touchscreen-size-x = <1024>;
touchscreen-size-y = <600>;
};
+
+ tlv320aic3111: tlv320aic3111@18 {
+ #sound-dai-cells = <0>;
+ compatible = "ti,tlv320aic3111";
+ reg = <0x18>;
+ status = "okay";
+
+ ai31xx-micbias-vg = <MICBIAS_2_0V>;
+
+ /* Regulators */
+ HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+ SPRVDD-supply = <&vbat>; /* vbat */
+ SPLVDD-supply = <&vbat>; /* vbat */
+ AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */
+ IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
+ DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
+ };
};
&i2c2 {
@@ -458,7 +532,21 @@
};
&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&display_mux_pins>;
status = "okay";
+
+ p1 {
+ /*
+ * SelLCDorHDMI selects between display and audio paths:
+ * Low: HDMI display with audio via HDMI
+ * High: LCD display with analog audio via aic3111 codec
+ */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "SelLCDorHDMI";
+ };
};
&gpio3 {
@@ -686,3 +774,21 @@
};
};
};
+
+&mcasp1 {
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mcasp1_pins>;
+ pinctrl-1 = <&mcasp1_sleep_pins>;
+
+ status = "okay";
+
+ op-mode = <0>; /* MCASP_IIS_MODE */
+ tdm-slots = <2>;
+ /* 4 serializer */
+ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
+ 1 2 0 0
+ >;
+ tx-num-evt = <32>;
+ rx-num-evt = <32>;
+};
diff --git a/dts/src/arm/am43xx-clocks.dtsi b/dts/src/arm/am43xx-clocks.dtsi
index d0c0dfa..cc88728 100644
--- a/dts/src/arm/am43xx-clocks.dtsi
+++ b/dts/src/arm/am43xx-clocks.dtsi
@@ -486,6 +486,15 @@
reg = <0x4238>;
};
+ dpll_clksel_mac_clk: dpll_clksel_mac_clk {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_core_m5_ck>;
+ reg = <0x4234>;
+ ti,bit-shift = <2>;
+ ti,dividers = <2>, <5>;
+ };
+
clk_32k_mosc_ck: clk_32k_mosc_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
diff --git a/dts/src/arm/am57xx-beagle-x15.dts b/dts/src/arm/am57xx-beagle-x15.dts
index a63bf78..3a05b94 100644
--- a/dts/src/arm/am57xx-beagle-x15.dts
+++ b/dts/src/arm/am57xx-beagle-x15.dts
@@ -580,7 +580,6 @@
vmmc-supply = <&ldo1_reg>;
vmmc_aux-supply = <&vdd_3v3>;
- pbias-supply = <&pbias_mmc_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
};
@@ -693,3 +692,7 @@
};
};
};
+
+&pcie1 {
+ gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
+};
diff --git a/dts/src/arm/armada-375.dtsi b/dts/src/arm/armada-375.dtsi
index 67a0ab0..e9a3817 100644
--- a/dts/src/arm/armada-375.dtsi
+++ b/dts/src/arm/armada-375.dtsi
@@ -176,6 +176,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
+ arm,double-linefill-incr = <1>;
+ arm,double-linefill-wrap = <0>;
+ arm,double-linefill = <1>;
+ prefetch-data = <1>;
};
scu@c000 {
diff --git a/dts/src/arm/armada-388-gp.dts b/dts/src/arm/armada-388-gp.dts
index fd4f6fd..353c925 100644
--- a/dts/src/arm/armada-388-gp.dts
+++ b/dts/src/arm/armada-388-gp.dts
@@ -81,10 +81,6 @@
pinctrl-0 = <&i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
- /*
- * The EEPROM located at adresse 54 is needed
- * for the boot - DO NOT ERASE IT -
- */
expander0: pca9555@20 {
compatible = "nxp,pca9555";
@@ -111,6 +107,10 @@
reg = <0x21>;
};
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
};
serial@12000 {
@@ -301,9 +301,11 @@
reg_sata0: pwr-sata0 {
compatible = "regulator-fixed";
regulator-name = "pwr_en_sata0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
enable-active-high;
regulator-always-on;
-
+ gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
};
reg_5v_sata0: v5-sata0 {
diff --git a/dts/src/arm/armada-38x.dtsi b/dts/src/arm/armada-38x.dtsi
index 04ecfe6..f9f2347 100644
--- a/dts/src/arm/armada-38x.dtsi
+++ b/dts/src/arm/armada-38x.dtsi
@@ -143,6 +143,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
+ arm,double-linefill-incr = <1>;
+ arm,double-linefill-wrap = <0>;
+ arm,double-linefill = <1>;
+ prefetch-data = <1>;
};
scu@c000 {
@@ -450,7 +454,7 @@
};
xor@60800 {
- compatible = "marvell,orion-xor";
+ compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
@@ -470,7 +474,7 @@
};
xor@60900 {
- compatible = "marvell,orion-xor";
+ compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
diff --git a/dts/src/arm/armada-39x.dtsi b/dts/src/arm/armada-39x.dtsi
index fc9864f..dc6efd3 100644
--- a/dts/src/arm/armada-39x.dtsi
+++ b/dts/src/arm/armada-39x.dtsi
@@ -104,6 +104,10 @@
reg = <0x8000 0x1000>;
cache-unified;
cache-level = <2>;
+ arm,double-linefill-incr = <1>;
+ arm,double-linefill-wrap = <0>;
+ arm,double-linefill = <1>;
+ prefetch-data = <1>;
};
scu@c000 {
@@ -325,7 +329,7 @@
};
xor@60800 {
- compatible = "marvell,orion-xor";
+ compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60800 0x100
0x60a00 0x100>;
clocks = <&gateclk 22>;
@@ -345,7 +349,7 @@
};
xor@60900 {
- compatible = "marvell,orion-xor";
+ compatible = "marvell,armada-380-xor", "marvell,orion-xor";
reg = <0x60900 0x100
0x60b00 0x100>;
clocks = <&gateclk 28>;
diff --git a/dts/src/arm/at91-sama5d2_xplained.dts b/dts/src/arm/at91-sama5d2_xplained.dts
new file mode 100644
index 0000000..e8d63af
--- /dev/null
+++ b/dts/src/arm/at91-sama5d2_xplained.dts
@@ -0,0 +1,134 @@
+/*
+ * at91-sama5d2_xplained.dts - Device Tree file for SAMA5D2 Xplained board
+ *
+ * Copyright (C) 2015 Atmel,
+ * 2015 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+
+/ {
+ model = "Atmel SAMA5D2 Xplained";
+ compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x20000000 0x80000>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ main_clock: clock@0 {
+ compatible = "atmel,osc", "fixed-clock";
+ clock-frequency = <12000000>;
+ };
+
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <12000000>;
+ };
+ };
+
+ ahb {
+ usb0: gadget@00300000 {
+ status = "okay";
+ };
+
+ usb1: ohci@00400000 {
+ num-ports = <3>;
+ status = "okay";
+ };
+
+ usb2: ehci@00500000 {
+ status = "okay";
+ };
+
+ apb {
+ spi0: spi@f8000000 {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "atmel,at25df321a";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ macb0: ethernet@f8008000 {
+ phy-mode = "rmii";
+ status = "okay";
+ };
+
+ uart1: serial@f8020000 {
+ status = "okay";
+ };
+
+ i2c0: i2c@f8028000 {
+ dmas = <0>, <0>;
+ status = "okay";
+ };
+
+ uart3: serial@fc008000 {
+ status = "okay";
+ };
+
+ i2c1: i2c@fc028000 {
+ dmas = <0>, <0>;
+ status = "okay";
+
+ at24@54 {
+ compatible = "atmel,24c02";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+ };
+ };
+ };
+};
diff --git a/dts/src/arm/at91-sama5d4_xplained.dts b/dts/src/arm/at91-sama5d4_xplained.dts
index 22ad7c9..07f4696 100644
--- a/dts/src/arm/at91-sama5d4_xplained.dts
+++ b/dts/src/arm/at91-sama5d4_xplained.dts
@@ -131,6 +131,15 @@
};
adc0: adc@fc034000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* external trigger conflicts with USBA_VBUS */
+ &pinctrl_adc0_ad0
+ &pinctrl_adc0_ad1
+ &pinctrl_adc0_ad2
+ &pinctrl_adc0_ad3
+ &pinctrl_adc0_ad4
+ >;
atmel,adc-vref = <3300>;
status = "okay";
};
diff --git a/dts/src/arm/at91-sama5d4ek.dts b/dts/src/arm/at91-sama5d4ek.dts
index d782f29..49a59c7 100644
--- a/dts/src/arm/at91-sama5d4ek.dts
+++ b/dts/src/arm/at91-sama5d4ek.dts
@@ -100,6 +100,15 @@
};
adc0: adc@fc034000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ /* external trigger conflicts with USBA_VBUS */
+ &pinctrl_adc0_ad0
+ &pinctrl_adc0_ad1
+ &pinctrl_adc0_ad2
+ &pinctrl_adc0_ad3
+ &pinctrl_adc0_ad4
+ >;
/* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
atmel,adc-vref = <3300>;
/*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
diff --git a/dts/src/arm/at91rm9200.dtsi b/dts/src/arm/at91rm9200.dtsi
index e3cfb99..60edd8b 100644
--- a/dts/src/arm/at91rm9200.dtsi
+++ b/dts/src/arm/at91rm9200.dtsi
@@ -359,6 +359,7 @@
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
reg = <0xfffffd00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
watchdog {
compatible = "atmel,at91rm9200-wdt";
@@ -369,6 +370,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
status = "disabled";
};
@@ -378,8 +380,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
tcb1: timer@fffa4000 {
@@ -388,8 +390,8 @@
interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
21 IRQ_TYPE_LEVEL_HIGH 0
22 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
i2c0: i2c@fffb8000 {
diff --git a/dts/src/arm/at91sam9260.dtsi b/dts/src/arm/at91sam9260.dtsi
index 4bc3475..be9c027 100644
--- a/dts/src/arm/at91sam9260.dtsi
+++ b/dts/src/arm/at91sam9260.dtsi
@@ -359,11 +359,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffd30 {
@@ -379,8 +381,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
18 IRQ_TYPE_LEVEL_HIGH 0
19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
tcb1: timer@fffdc000 {
@@ -389,8 +391,8 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
27 IRQ_TYPE_LEVEL_HIGH 0
28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
pinctrl@fffff400 {
@@ -973,6 +975,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
diff --git a/dts/src/arm/at91sam9261.dtsi b/dts/src/arm/at91sam9261.dtsi
index b2c44a0..ce1e3e9 100644
--- a/dts/src/arm/at91sam9261.dtsi
+++ b/dts/src/arm/at91sam9261.dtsi
@@ -119,8 +119,8 @@
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>,
<19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
usb1: gadget@fffa4000 {
@@ -820,11 +820,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&slow_xtal>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&slow_xtal>;
};
pit: timer@fffffd30 {
@@ -846,6 +848,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
status = "disabled";
};
diff --git a/dts/src/arm/at91sam9263.dtsi b/dts/src/arm/at91sam9263.dtsi
index e36d966..f1f5fa3 100644
--- a/dts/src/arm/at91sam9263.dtsi
+++ b/dts/src/arm/at91sam9263.dtsi
@@ -377,18 +377,20 @@
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>;
- clock-names = "t0_clk";
+ clocks = <&tcb_clk>, <&slow_xtal>;
+ clock-names = "t0_clk", "slow_clk";
};
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&slow_xtal>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&slow_xtal>;
};
pinctrl@fffff200 {
@@ -902,6 +904,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&slow_xtal>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
diff --git a/dts/src/arm/at91sam9g15.dtsi b/dts/src/arm/at91sam9g15.dtsi
index cfd7044..27de7dc 100644
--- a/dts/src/arm/at91sam9g15.dtsi
+++ b/dts/src/arm/at91sam9g15.dtsi
@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_lcd.dtsi"
/ {
model = "Atmel AT91SAM9G15 SoC";
diff --git a/dts/src/arm/at91sam9g15ek.dts b/dts/src/arm/at91sam9g15ek.dts
index 26b0444..d1d2b40 100644
--- a/dts/src/arm/at91sam9g15ek.dts
+++ b/dts/src/arm/at91sam9g15ek.dts
@@ -8,9 +8,34 @@
*/
/dts-v1/;
#include "at91sam9g15.dtsi"
+#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"
/ {
model = "Atmel AT91SAM9G15-EK";
compatible = "atmel,at91sam9g15ek", "atmel,at91sam9x5ek", "atmel,at91sam9x5", "atmel,at91sam9";
+
+ ahb {
+ apb {
+ hlcdc: hlcdc@f8038000 {
+ status = "okay";
+ };
+ };
+ };
+
+ backlight: backlight {
+ status = "okay";
+ };
+
+ bl_reg: backlight_regulator {
+ status = "okay";
+ };
+
+ panel: panel {
+ status = "okay";
+ };
+
+ panel_reg: panel_regulator {
+ status = "okay";
+ };
};
diff --git a/dts/src/arm/at91sam9g35.dtsi b/dts/src/arm/at91sam9g35.dtsi
index e35c2fc..ff41158 100644
--- a/dts/src/arm/at91sam9g35.dtsi
+++ b/dts/src/arm/at91sam9g35.dtsi
@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_lcd.dtsi"
#include "at91sam9x5_macb0.dtsi"
/ {
diff --git a/dts/src/arm/at91sam9g35ek.dts b/dts/src/arm/at91sam9g35ek.dts
index 641a9bf..23ec8b1 100644
--- a/dts/src/arm/at91sam9g35ek.dts
+++ b/dts/src/arm/at91sam9g35ek.dts
@@ -8,6 +8,7 @@
*/
/dts-v1/;
#include "at91sam9g35.dtsi"
+#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"
/ {
@@ -20,6 +21,26 @@
phy-mode = "rmii";
status = "okay";
};
+
+ hlcdc: hlcdc@f8038000 {
+ status = "okay";
+ };
};
};
+
+ backlight: backlight {
+ status = "okay";
+ };
+
+ bl_reg: backlight_regulator {
+ status = "okay";
+ };
+
+ panel: panel {
+ status = "okay";
+ };
+
+ panel_reg: panel_regulator {
+ status = "okay";
+ };
};
diff --git a/dts/src/arm/at91sam9g45.dtsi b/dts/src/arm/at91sam9g45.dtsi
index 18177f5..18b8b9e 100644
--- a/dts/src/arm/at91sam9g45.dtsi
+++ b/dts/src/arm/at91sam9g45.dtsi
@@ -387,6 +387,7 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffd30 {
@@ -400,22 +401,23 @@
shdwc@fffffd10 {
compatible = "atmel,at91sam9rl-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
tcb0: timer@fff7c000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfff7c000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
tcb1: timer@fffd4000 {
compatible = "atmel,at91rm9200-tcb";
reg = <0xfffd4000 0x100>;
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
dma: dma-controller@ffffec00 {
@@ -498,23 +500,31 @@
};
isi {
- pinctrl_isi: isi-0 {
- atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
- AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
- AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
- AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
- AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
- AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
- AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
- AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
- AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
- AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
- AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
- AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
- AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
- AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
- AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
- AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
+ pinctrl_isi_data_0_7: isi-0-data-0-7 {
+ atmel,pins =
+ <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
+ AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
+ AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
+ AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
+ AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
+ AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
+ AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
+ AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
+ AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
+ AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
+ AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
+ };
+
+ pinctrl_isi_data_8_9: isi-0-data-8-9 {
+ atmel,pins =
+ <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
+ AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D9 */
+ };
+
+ pinctrl_isi_data_10_11: isi-0-data-10-11 {
+ atmel,pins =
+ <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
+ AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* D11 */
};
};
@@ -1067,9 +1077,11 @@
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&isi_clk>;
clock-names = "isi_clk";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_isi>;
status = "disabled";
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
};
pwm0: pwm@fffb8000 {
@@ -1113,6 +1125,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1247,6 +1260,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffdb0 0x30>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
diff --git a/dts/src/arm/at91sam9m10g45ek.dts b/dts/src/arm/at91sam9m10g45ek.dts
index 1375d33..d1ae60a 100644
--- a/dts/src/arm/at91sam9m10g45ek.dts
+++ b/dts/src/arm/at91sam9m10g45ek.dts
@@ -63,6 +63,25 @@
i2c0: i2c@fff84000 {
status = "okay";
+ ov2640: camera@30 {
+ compatible = "ovti,ov2640";
+ reg = <0x30>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pck1_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
+ resetb-gpios = <&pioD 12 GPIO_ACTIVE_LOW>;
+ pwdn-gpios = <&pioD 13 GPIO_ACTIVE_HIGH>;
+ clocks = <&pck1>;
+ clock-names = "xvclk";
+ assigned-clocks = <&pck1>;
+ assigned-clock-rates = <25000000>;
+
+ port {
+ ov2640_0: endpoint {
+ remote-endpoint = <&isi_0>;
+ bus-width = <8>;
+ };
+ };
+ };
};
i2c1: i2c@fff88000 {
@@ -101,6 +120,22 @@
};
pinctrl@fffff200 {
+ camera_sensor {
+ pinctrl_pck1_as_isi_mck: pck1_as_isi_mck-0 {
+ atmel,pins =
+ <AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_sensor_reset: sensor_reset-0 {
+ atmel,pins =
+ <AT91_PIOD 12 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+
+ pinctrl_sensor_power: sensor_power-0 {
+ atmel,pins =
+ <AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+ };
+ };
mmc0 {
pinctrl_board_mmc0: mmc0-board {
atmel,pins =
@@ -155,6 +190,18 @@
status = "okay";
};
+ isi@fffb4000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_isi_data_0_7>;
+ status = "okay";
+ port {
+ isi_0: endpoint {
+ remote-endpoint = <&ov2640_0>;
+ bus-width = <8>;
+ };
+ };
+ };
+
pwm0: pwm@fffb8000 {
status = "okay";
diff --git a/dts/src/arm/at91sam9n12.dtsi b/dts/src/arm/at91sam9n12.dtsi
index 5c2a8c8..32bc9a1 100644
--- a/dts/src/arm/at91sam9n12.dtsi
+++ b/dts/src/arm/at91sam9n12.dtsi
@@ -376,6 +376,7 @@
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffe30 {
@@ -388,6 +389,7 @@
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k>;
};
sckc@fffffe50 {
@@ -431,16 +433,44 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>;
- clock-names = "t0_clk";
+ clocks = <&tcb_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb_clk>;
- clock-names = "t0_clk";
+ clocks = <&tcb_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
+ };
+
+ hlcdc: hlcdc@f8038000 {
+ compatible = "atmel,at91sam9n12-hlcdc";
+ reg = <0xf8038000 0x2000>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clock-names = "periph_clk", "sys_clk", "slow_clk";
+ status = "disabled";
+
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-display-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ };
+
+ hlcdc_pwm: hlcdc-pwm {
+ compatible = "atmel,hlcdc-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_pwm>;
+ #pwm-cells = <3>;
+ };
};
dma: dma-controller@ffffec00 {
@@ -475,6 +505,49 @@
};
};
+ lcd {
+ pinctrl_lcd_base: lcd-base-0 {
+ atmel,pins =
+ <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
+ AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
+ AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
+ AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
+ };
+
+ pinctrl_lcd_pwm: lcd-pwm-0 {
+ atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
+ };
+
+ pinctrl_lcd_rgb888: lcd-rgb-3 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
+ AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
+ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
+ AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
+ AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
+ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
+ AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
+ AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
+ AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
+ AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
+ AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+ };
+ };
+
usart0 {
pinctrl_usart0: usart0-0 {
atmel,pins =
@@ -891,6 +964,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -901,6 +975,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
diff --git a/dts/src/arm/at91sam9n12ek.dts b/dts/src/arm/at91sam9n12ek.dts
index eab17fc..efa7506 100644
--- a/dts/src/arm/at91sam9n12ek.dts
+++ b/dts/src/arm/at91sam9n12ek.dts
@@ -128,6 +128,22 @@
};
};
+ hlcdc: hlcdc@f8038000 {
+ status = "okay";
+
+ hlcdc-display-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
+
+ port@0 {
+ hlcdc_panel_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
usb1: gadget@f803c000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_vbus_sense>;
@@ -161,6 +177,23 @@
};
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&hlcdc_pwm 0 50000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ power-supply = <&bl_reg>;
+ status = "okay";
+ };
+
+ bl_reg: backlight_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight-power-supply";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ status = "okay";
+ };
+
leds {
compatible = "gpio-leds";
@@ -194,6 +227,34 @@
};
};
+ panel: panel {
+ compatible = "qd,qd43003c0-40", "simple-panel";
+ backlight = <&backlight>;
+ power-supply = <&panel_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hlcdc_panel_output>;
+ };
+ };
+ };
+
+ panel_reg: panel_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-power-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
+ };
+
sound {
compatible = "atmel,asoc-wm8904";
pinctrl-names = "default";
diff --git a/dts/src/arm/at91sam9rl.dtsi b/dts/src/arm/at91sam9rl.dtsi
index c9920c6..a0b90ae 100644
--- a/dts/src/arm/at91sam9rl.dtsi
+++ b/dts/src/arm/at91sam9rl.dtsi
@@ -121,8 +121,8 @@
interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
<17 IRQ_TYPE_LEVEL_HIGH 0>,
<18 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
- clock-names = "t0_clk", "t1_clk", "t2_clk";
+ clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
+ clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
};
mmc0: mmc@fffa4000 {
@@ -1018,11 +1018,13 @@
rstc@fffffd00 {
compatible = "atmel,at91sam9260-rstc";
reg = <0xfffffd00 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fffffd10 {
compatible = "atmel,at91sam9260-shdwc";
reg = <0xfffffd10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffd30 {
@@ -1036,6 +1038,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffd40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
@@ -1083,6 +1086,7 @@
compatible = "atmel,at91rm9200-rtc";
reg = <0xfffffe00 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
diff --git a/dts/src/arm/at91sam9x35.dtsi b/dts/src/arm/at91sam9x35.dtsi
index 499cdc8..d9054e8 100644
--- a/dts/src/arm/at91sam9x35.dtsi
+++ b/dts/src/arm/at91sam9x35.dtsi
@@ -7,6 +7,7 @@
*/
#include "at91sam9x5.dtsi"
+#include "at91sam9x5_lcd.dtsi"
#include "at91sam9x5_macb0.dtsi"
#include "at91sam9x5_can.dtsi"
diff --git a/dts/src/arm/at91sam9x35ek.dts b/dts/src/arm/at91sam9x35ek.dts
index 343d328..fcb6718 100644
--- a/dts/src/arm/at91sam9x35ek.dts
+++ b/dts/src/arm/at91sam9x35ek.dts
@@ -8,6 +8,7 @@
*/
/dts-v1/;
#include "at91sam9x35.dtsi"
+#include "at91sam9x5dm.dtsi"
#include "at91sam9x5ek.dtsi"
/ {
@@ -20,6 +21,25 @@
phy-mode = "rmii";
status = "okay";
};
+ hlcdc: hlcdc@f8038000 {
+ status = "okay";
+ };
};
};
+
+ backlight: backlight {
+ status = "okay";
+ };
+
+ bl_reg: backlight_regulator {
+ status = "okay";
+ };
+
+ panel: panel {
+ status = "okay";
+ };
+
+ panel_reg: panel_regulator {
+ status = "okay";
+ };
};
diff --git a/dts/src/arm/at91sam9x5.dtsi b/dts/src/arm/at91sam9x5.dtsi
index b6c8df8..747d8f0 100644
--- a/dts/src/arm/at91sam9x5.dtsi
+++ b/dts/src/arm/at91sam9x5.dtsi
@@ -376,11 +376,13 @@
rstc@fffffe00 {
compatible = "atmel,at91sam9g45-rstc";
reg = <0xfffffe00 0x10>;
+ clocks = <&clk32k>;
};
shdwc@fffffe10 {
compatible = "atmel,at91sam9x5-shdwc";
reg = <0xfffffe10 0x10>;
+ clocks = <&clk32k>;
};
pit: timer@fffffe30 {
@@ -418,16 +420,16 @@
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf8008000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>;
- clock-names = "t0_clk";
+ clocks = <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
};
tcb1: timer@f800c000 {
compatible = "atmel,at91sam9x5-tcb";
reg = <0xf800c000 0x100>;
interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&tcb0_clk>;
- clock-names = "t0_clk";
+ clocks = <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
};
dma0: dma-controller@ffffec00 {
@@ -1173,6 +1175,7 @@
compatible = "atmel,at91sam9260-wdt";
reg = <0xfffffe40 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
atmel,watchdog-type = "hardware";
atmel,reset-type = "all";
atmel,dbg-halt;
@@ -1183,6 +1186,7 @@
compatible = "atmel,at91sam9x5-rtc";
reg = <0xfffffeb0 0x40>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&clk32k>;
status = "disabled";
};
diff --git a/dts/src/arm/at91sam9x5_lcd.dtsi b/dts/src/arm/at91sam9x5_lcd.dtsi
index 485302e..1629db9 100644
--- a/dts/src/arm/at91sam9x5_lcd.dtsi
+++ b/dts/src/arm/at91sam9x5_lcd.dtsi
@@ -13,6 +13,137 @@
/ {
ahb {
apb {
+ hlcdc: hlcdc@f8038000 {
+ compatible = "atmel,at91sam9x5-hlcdc";
+ reg = <0xf8038000 0x4000>;
+ interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
+ clock-names = "periph_clk","sys_clk", "slow_clk";
+ status = "disabled";
+
+ hlcdc-display-controller {
+ compatible = "atmel,hlcdc-display-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+ };
+
+ hlcdc_pwm: hlcdc-pwm {
+ compatible = "atmel,hlcdc-pwm";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_pwm>;
+ #pwm-cells = <3>;
+ };
+ };
+
+ pinctrl@fffff400 {
+ lcd {
+ pinctrl_lcd_base: lcd-base-0 {
+ atmel,pins =
+ <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */
+ AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */
+ AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDISP */
+ AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */
+ AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
+ };
+
+ pinctrl_lcd_pwm: lcd-pwm-0 {
+ atmel,pins = <AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */
+ };
+
+ pinctrl_lcd_rgb444: lcd-rgb-0 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
+ };
+
+ pinctrl_lcd_rgb565: lcd-rgb-1 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
+ AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
+ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
+ };
+
+ pinctrl_lcd_rgb666: lcd-rgb-2 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
+ AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
+ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
+ AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
+ AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD17 pin */
+ };
+
+ pinctrl_lcd_rgb888: lcd-rgb-3 {
+ atmel,pins =
+ <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */
+ AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */
+ AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */
+ AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */
+ AT91_PIOC 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */
+ AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */
+ AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */
+ AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */
+ AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */
+ AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */
+ AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */
+ AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */
+ AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */
+ AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */
+ AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */
+ AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */
+ AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */
+ AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */
+ AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */
+ AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */
+ AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */
+ AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */
+ AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */
+ AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
+ };
+ };
+ };
+
pmc: pmc@fffffc00 {
periphck {
lcdc_clk: lcdc_clk {
@@ -20,6 +151,14 @@
reg = <25>;
};
};
+
+ systemck {
+ lcdck: lcdck {
+ #clock-cells = <0>;
+ reg = <3>;
+ clocks = <&mck>;
+ };
+ };
};
};
};
diff --git a/dts/src/arm/at91sam9x5dm.dtsi b/dts/src/arm/at91sam9x5dm.dtsi
new file mode 100644
index 0000000..34c089f
--- /dev/null
+++ b/dts/src/arm/at91sam9x5dm.dtsi
@@ -0,0 +1,101 @@
+/*
+ * at91sam9x5dm.dtsi - Device Tree file for SAM9x5 display module
+ *
+ * Copyright (C) 2014 Atmel,
+ * 2014 Free Electrons
+ *
+ * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+ ahb {
+ apb {
+ i2c0: i2c@f8010000 {
+ qt1070: keyboard@1b {
+ compatible = "qt1070";
+ reg = <0x1b>;
+ interrupt-parent = <&pioA>;
+ interrupts = <7 0x0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qt1070_irq>;
+ wakeup-source;
+ };
+ };
+
+ hlcdc: hlcdc@f8038000 {
+ hlcdc-display-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_rgb888>;
+
+ port@0 {
+ hlcdc_panel_output: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+ };
+
+ adc0: adc@f804c000 {
+ atmel,adc-ts-wires = <4>;
+ atmel,adc-ts-pressure-threshold = <10000>;
+ status = "okay";
+ };
+
+ pinctrl@fffff400 {
+ board {
+ pinctrl_qt1070_irq: qt1070_irq {
+ atmel,pins =
+ <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+ };
+ };
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&hlcdc_pwm 0 50000 0>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ power-supply = <&bl_reg>;
+ status = "disabled";
+ };
+
+ bl_reg: backlight_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "backlight-power-supply";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ status = "disabled";
+ };
+
+ panel: panel {
+ compatible = "foxlink,fl500wvr00-a0t", "simple-panel";
+ backlight = <&backlight>;
+ power-supply = <&panel_reg>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel_input: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hlcdc_panel_output>;
+ };
+ };
+ };
+
+ panel_reg: panel_regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-power-supply";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "disabled";
+ };
+};
diff --git a/dts/src/arm/atlas7-evb.dts b/dts/src/arm/atlas7-evb.dts
index 49cf59a..1e9cd1a 100644
--- a/dts/src/arm/atlas7-evb.dts
+++ b/dts/src/arm/atlas7-evb.dts
@@ -10,6 +10,9 @@
/include/ "atlas7.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
/ {
model = "CSR SiRFatlas7 Evaluation Board";
compatible = "sirf,atlas7-cb", "sirf,atlas7";
@@ -106,5 +109,20 @@
};
};
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rearview_key {
+ label = "rearview key";
+ linux,code = <KEY_CAMERA>;
+ gpios = <&gpio_1 3 GPIO_ACTIVE_LOW>;
+ debounce_interval = <100>;
+ };
+ };
+
};
};
diff --git a/dts/src/arm/atlas7.dtsi b/dts/src/arm/atlas7.dtsi
index 3e21311..83449b3 100644
--- a/dts/src/arm/atlas7.dtsi
+++ b/dts/src/arm/atlas7.dtsi
@@ -21,6 +21,10 @@
serial5 = &uart5;
serial6 = &uart6;
serial9 = &usp2;
+ spi1 = &spi1;
+ spi2 = &usp1;
+ spi3 = &usp2;
+ spi4 = &usp3;
};
cpus {
#address-cells = <1>;
@@ -53,6 +57,11 @@
};
};
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <0 29 4>, <0 82 4>;
+ };
+
noc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -1205,7 +1214,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x18641000 0x18641000 0x3000>,
- <0x18620000 0x18620000 0x1000>;
+ <0x18620000 0x18620000 0x1000>,
+ <0x18630000 0x18630000 0x10000>;
cgum@18641000 {
compatible = "sirf,nocfw-cgum";
@@ -1218,6 +1228,15 @@
#clock-cells = <1>;
#reset-cells = <1>;
};
+ pwm: pwm@18630000 {
+ compatible = "sirf,prima2-pwm";
+ #pwm-cells = <2>;
+ reg = <0x18630000 0x10000>;
+ clocks = <&car 138>, <&car 139>, <&car 237>,
+ <&car 240>, <&car 140>, <&car 246>;
+ clock-names = "pwmc", "sigsrc0", "sigsrc1",
+ "sigsrc2", "sigsrc3", "sigsrc4";
+ };
};
gnssm {
@@ -1231,6 +1250,7 @@
<0x18040000 0x18040000 0x1000>,
<0x18050000 0x18050000 0x1000>,
<0x18060000 0x18060000 0x1000>,
+ <0x180b0000 0x180b0000 0x4000>,
<0x18100000 0x18100000 0x3000>,
<0x18250000 0x18250000 0x10000>,
<0x18200000 0x18200000 0x1000>;
@@ -1314,6 +1334,18 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ gmac: eth@180b0000 {
+ compatible = "snps, dwc-eth-qos";
+ reg = <0x180b0000 0x4000>;
+ interrupts = <0 59 0>, <0 70 0>;
+ interrupt-names = "macirq", "macpmt";
+ clocks = <&car 39>, <&car 45>,
+ <&car 86>, <&car 87>;
+ clock-names = "gnssm_rgmii", "gnssm_gmac",
+ "rgmii", "gmac";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-mode = "rgmii";
+ };
dspub@18250000 {
compatible = "dx,cc44p";
reg = <0x18250000 0x10000>;
@@ -1338,18 +1370,51 @@
compatible = "arteris, flexnoc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x13000000 0x13000000 0x3000>;
+ ranges = <0x13000000 0x13000000 0x3000>,
+ <0x13010000 0x13010000 0x1400>,
+ <0x13010800 0x13010800 0x100>,
+ <0x13011000 0x13011000 0x100>;
gpum@0x13000000 {
compatible = "sirf,nocfw-gpum";
reg = <0x13000000 0x3000>;
};
+ dmacsdrr: dma-controller@13010800 {
+ cell-index = <5>;
+ compatible = "sirf,atlas7-dmac-v2";
+ reg = <0x13010800 0x100>;
+ interrupts = <0 8 0>;
+ clocks = <&car 127>;
+ #dma-cells = <1>;
+ #dma-channels = <1>;
+ };
+ dmacsdrw: dma-controller@13011000 {
+ cell-index = <6>;
+ compatible = "sirf,atlas7-dmac-v2";
+ reg = <0x13011000 0x100>;
+ interrupts = <0 9 0>;
+ clocks = <&car 127>;
+ #dma-cells = <1>;
+ #dma-channels = <1>;
+ };
+ sdr@0x13010000 {
+ compatible = "sirf,atlas7-sdr";
+ reg = <0x13010000 0x1400>;
+ interrupts = <0 7 0>,
+ <0 8 0>,
+ <0 9 0>;
+ clocks = <&car 127>;
+ dmas = <&dmacsdrr 0>, <&dmacsdrw 0>;
+ dma-names = "tx", "rx";
+ };
};
mediam {
compatible = "arteris, flexnoc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x16000000 0x16000000 0x00200000>,
+ ranges = <0x15000000 0x15000000 0x00600000>,
+ <0x16000000 0x16000000 0x00200000>,
+ <0x17000000 0x17000000 0x10000>,
<0x17020000 0x17020000 0x1000>,
<0x17030000 0x17030000 0x1000>,
<0x17040000 0x17040000 0x1000>,
@@ -1360,6 +1425,13 @@
<0x17070200 0x17070200 0x100>,
<0x170A0000 0x170A0000 0x3000>;
+ multimedia@15000000 {
+ compatible = "sirf,atlas7-video-codec";
+ reg = <0x15000000 0x10000>;
+ interrupts = <0 5 0>;
+ clocks = <&car 102>;
+ };
+
mediam@170A0000 {
compatible = "sirf,nocfw-mediam";
reg = <0x170A0000 0x3000>;
@@ -1386,6 +1458,8 @@
nand@17050000 {
compatible = "sirf,atlas7-nand";
reg = <0x17050000 0x10000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&nd_df_pmx>;
interrupts = <0 41 0>;
clocks = <&car 108>, <&car 112>;
clock-names = "nand_io", "nand_nand";
@@ -1416,6 +1490,14 @@
bus-width = <8>;
};
+ jpeg@17000000 {
+ compatible = "sirf,atlas7-jpeg";
+ reg = <0x17000000 0x10000>;
+ interrupts = <0 72 0>,
+ <0 73 0>;
+ clocks = <&car 103>;
+ };
+
usb0: usb@17060000 {
cell-index = <0>;
compatible = "sirf,atlas7-usb";
@@ -1826,7 +1908,8 @@
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x13100000 0x13100000 0x20000>,
- <0x10e10000 0x10e10000 0x10000>;
+ <0x10e10000 0x10e10000 0x10000>,
+ <0x17010000 0x17010000 0x10000>;
lcd@13100000 {
compatible = "sirf,atlas7-lcdc";
@@ -1848,6 +1931,12 @@
clocks = <&car 54>;
resets = <&car 29>;
};
+ g2d@17010000 {
+ compatible = "sirf, atlas7-g2d";
+ reg = <0x17010000 0x10000>;
+ interrupts = <0 61 0>;
+ clocks = <&car 104>;
+ };
};
diff --git a/dts/src/arm/axp152.dtsi b/dts/src/arm/axp152.dtsi
new file mode 100644
index 0000000..f90ad6c
--- /dev/null
+++ b/dts/src/arm/axp152.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+&axp152 {
+ compatible = "x-powers,axp152";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+};
diff --git a/dts/src/arm/bcm-cygnus-clock.dtsi b/dts/src/arm/bcm-cygnus-clock.dtsi
index 60d8389..32bcd45 100644
--- a/dts/src/arm/bcm-cygnus-clock.dtsi
+++ b/dts/src/arm/bcm-cygnus-clock.dtsi
@@ -36,56 +36,89 @@ clocks {
ranges;
osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
- #clock-cells = <1>;
clock-frequency = <25000000>;
};
- apb_clk: apb_clk {
- compatible = "fixed-clock";
+ /* Cygnus ARM PLL */
+ armpll: armpll {
#clock-cells = <0>;
- clock-frequency = <1000000000>;
+ compatible = "brcm,cygnus-armpll";
+ clocks = <&osc>;
+ reg = <0x19000000 0x1000>;
};
- periph_clk: periph_clk {
- compatible = "fixed-clock";
+ /* peripheral clock for system timer */
+ periph_clk: arm_periph_clk {
#clock-cells = <0>;
- clock-frequency = <500000000>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
- sdio_clk: lcpll_ch2 {
- compatible = "fixed-clock";
+ /* APB bus clock */
+ apb_clk: apb_clk {
#clock-cells = <0>;
- clock-frequency = <200000000>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
- axi81_clk: axi81_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
+ genpll: genpll {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-genpll";
+ reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
+ "enet_sw", "audio_125", "can";
};
- keypad_clk: keypad_clk {
- compatible = "fixed-clock";
+ /* always 1/2 of the axi21 clock */
+ axi41_clk: axi41_clk {
#clock-cells = <0>;
- clock-frequency = <31806>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll 1>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
- adc_clk: adc_clk {
- compatible = "fixed-clock";
+ /* always 1/4 of the axi21 clock */
+ axi81_clk: axi81_clk {
#clock-cells = <0>;
- clock-frequency = <1562500>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll 1>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
- pwm_clk: pwm_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1000000>;
+ lcpll0: lcpll0 {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-lcpll0";
+ reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll0", "pcie_phy", "ddr_phy", "sdio",
+ "usb_phy", "smart_card", "ch5";
};
- lcd_clk: mipipll_ch1 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
+ mipipll: mipipll {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-mipipll";
+ reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
+ clocks = <&osc>;
+ clock-output-names = "mipipll", "ch0_unused", "ch1_lcd",
+ "ch2_v3d", "ch3_unused", "ch4_unused",
+ "ch5_unused";
+ };
+
+ asiu_clks: asiu_clks {
+ #clock-cells = <1>;
+ compatible = "brcm,cygnus-asiu-clk";
+ reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
+
+ clocks = <&osc>;
+ clock-output-names = "keypad", "adc/touch", "pwm";
};
};
diff --git a/dts/src/arm/bcm2835-rpi.dtsi b/dts/src/arm/bcm2835-rpi.dtsi
index 46780bb..ab5474e 100644
--- a/dts/src/arm/bcm2835-rpi.dtsi
+++ b/dts/src/arm/bcm2835-rpi.dtsi
@@ -14,6 +14,13 @@
linux,default-trigger = "heartbeat";
};
};
+
+ soc {
+ firmware: firmware {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+ };
+ };
};
&gpio {
diff --git a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
index 24f0ab5..42dcdfb 100644
--- a/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/dts/src/arm/bcm4708-buffalo-wzr-1750dhp.dts
@@ -135,3 +135,7 @@
};
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm4708-luxul-xwc-1000.dts b/dts/src/arm/bcm4708-luxul-xwc-1000.dts
index f039393..f18e80e 100644
--- a/dts/src/arm/bcm4708-luxul-xwc-1000.dts
+++ b/dts/src/arm/bcm4708-luxul-xwc-1000.dts
@@ -55,3 +55,7 @@
};
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm4708-netgear-r6250.dts b/dts/src/arm/bcm4708-netgear-r6250.dts
index 326ce8f..64b8d10 100644
--- a/dts/src/arm/bcm4708-netgear-r6250.dts
+++ b/dts/src/arm/bcm4708-netgear-r6250.dts
@@ -24,16 +24,6 @@
reg = <0x00000000 0x08000000>;
};
- chipcommonA {
- uart0: serial@0300 {
- status = "okay";
- };
-
- uart1: serial@0400 {
- status = "okay";
- };
- };
-
leds {
compatible = "gpio-leds";
@@ -92,3 +82,7 @@
};
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm4708-smartrg-sr400ac.dts b/dts/src/arm/bcm4708-smartrg-sr400ac.dts
index d6a033b..64a5e8a 100644
--- a/dts/src/arm/bcm4708-smartrg-sr400ac.dts
+++ b/dts/src/arm/bcm4708-smartrg-sr400ac.dts
@@ -118,3 +118,7 @@
};
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
index bb0cb0b..38f0c00 100644
--- a/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
+++ b/dts/src/arm/bcm47081-buffalo-wzr-600dhp2.dts
@@ -122,3 +122,7 @@
};
};
};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/dts/src/arm/bcm5301x.dtsi b/dts/src/arm/bcm5301x.dtsi
index 21fefd4..6f50f67 100644
--- a/dts/src/arm/bcm5301x.dtsi
+++ b/dts/src/arm/bcm5301x.dtsi
@@ -78,10 +78,20 @@
compatible = "arm,pl310-cache";
reg = <0x2000 0x1000>;
cache-unified;
+ arm,shared-override;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
cache-level = <2>;
};
};
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts =
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/dts/src/arm/bcm7445.dtsi b/dts/src/arm/bcm7445.dtsi
index 58dcd66..3b6b175 100644
--- a/dts/src/arm/bcm7445.dtsi
+++ b/dts/src/arm/bcm7445.dtsi
@@ -109,6 +109,20 @@
brcm,int-fwd-mask = <0x70000>;
};
+ irq0_aon_intc: interrupt-controller@417280 {
+ compatible = "brcm,bcm7120-l2-intc";
+ reg = <0x417280 0x8>;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 0x46 0x0>,
+ <GIC_SPI 0x44 0x0>,
+ <GIC_SPI 0x49 0x0>;
+ brcm,int-map-mask = <0x1e3 0x18000000 0x100000>;
+ brcm,int-fwd-mask = <0x0>;
+ brcm,irq-can-wake;
+ };
+
hif_intr2_intc: interrupt-controller@3e1000 {
compatible = "brcm,l2-intc";
reg = <0x3e1000 0x30>;
@@ -119,6 +133,16 @@
interrupt-names = "hif";
};
+ aon_pm_l2_intc: interrupt-controller@410640 {
+ compatible = "brcm,l2-intc";
+ reg = <0x410640 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 0x40 0x0>;
+ interrupt-parent = <&gic>;
+ brcm,irq-can-wake;
+ };
+
nand: nand@3e2800 {
status = "disabled";
#address-cells = <1>;
@@ -167,6 +191,32 @@
#phy-cells = <0>;
};
};
+
+ upg_gio: gpio@40a700 {
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ reg = <0x40a700 0x80>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ interrupt-parent = <&irq0_intc>;
+ interrupts = <6>;
+ brcm,gpio-bank-widths = <32 32 32 24>;
+ };
+
+ upg_gio_aon: gpio@4172c0 {
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ reg = <0x4172c0 0x40>;
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ interrupt-controller;
+ interrupts-extended = <&irq0_aon_intc 0x6>,
+ <&aon_pm_l2_intc 0x5>;
+ wakeup-source;
+ brcm,gpio-bank-widths = <18 4>;
+ };
+
};
smpboot {
diff --git a/dts/src/arm/cros-ec-sbs.dtsi b/dts/src/arm/cros-ec-sbs.dtsi
new file mode 100644
index 0000000..71f5c5e
--- /dev/null
+++ b/dts/src/arm/cros-ec-sbs.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Smart battery dts fragment for devices that use cros-ec-sbs
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+&i2c_tunnel {
+ battery: sbs-battery@b {
+ compatible = "sbs,sbs-battery";
+ reg = <0xb>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <1>;
+ };
+};
diff --git a/dts/src/arm/cx92755.dtsi b/dts/src/arm/cx92755.dtsi
index af33326..df4c6f1 100644
--- a/dts/src/arm/cx92755.dtsi
+++ b/dts/src/arm/cx92755.dtsi
@@ -88,6 +88,13 @@
interrupts = <25>;
};
+ watchdog@f0000fc0 {
+ compatible = "cnxt,cx92755-wdt";
+ reg = <0xf0000fc0 0x8>;
+ clocks = <&main_clk>;
+ timeout-sec = <15>;
+ };
+
uc_regs: syscon@f00003a0 {
compatible = "cnxt,cx92755-uc", "syscon";
reg = <0xf00003a0 0x10>;
diff --git a/dts/src/arm/cx92755_equinox.dts b/dts/src/arm/cx92755_equinox.dts
index 90d52cc..5da0080 100644
--- a/dts/src/arm/cx92755_equinox.dts
+++ b/dts/src/arm/cx92755_equinox.dts
@@ -64,8 +64,7 @@
};
chosen {
- bootargs = "console=ttyS0,115200";
- stdout-path = &uart0;
+ stdout-path = "serial0:115200n8";
};
};
diff --git a/dts/src/arm/dm8148-evm.dts b/dts/src/arm/dm8148-evm.dts
new file mode 100644
index 0000000..92bacd3
--- /dev/null
+++ b/dts/src/arm/dm8148-evm.dts
@@ -0,0 +1,28 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dm814x.dtsi"
+
+/ {
+ model = "DM8148 EVM";
+ compatible = "ti,dm8148-evm", "ti,dm8148";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+};
diff --git a/dts/src/arm/dm8148-t410.dts b/dts/src/arm/dm8148-t410.dts
new file mode 100644
index 0000000..8c4bbc7
--- /dev/null
+++ b/dts/src/arm/dm8148-t410.dts
@@ -0,0 +1,28 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "dm814x.dtsi"
+
+/ {
+ model = "DM8148 EVM";
+ compatible = "hp,t410", "ti,dm8148";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x40000000>; /* 1 GB */
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+};
diff --git a/dts/src/arm/dm814x-clocks.dtsi b/dts/src/arm/dm814x-clocks.dtsi
new file mode 100644
index 0000000..ef1e8e7
--- /dev/null
+++ b/dts/src/arm/dm814x-clocks.dtsi
@@ -0,0 +1,109 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&scm_clocks {
+
+ tclkin_ck: tclkin_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ devosc_ck: devosc_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
+ /* Optional auxosc, 20 - 30 MHz range, assume 27 MHz by default */
+ auxosc_ck: auxosc_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <27000000>;
+ };
+
+ mpu_ck: mpu_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <1000000000>;
+ };
+
+ sysclk4_ck: sysclk4_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <222000000>;
+ };
+
+ sysclk6_ck: sysclk6_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+
+ sysclk10_ck: sysclk10_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ };
+
+ sysclk18_ck: sysclk18_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ cpsw_125mhz_gclk: cpsw_125mhz_gclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ };
+
+ cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <250000000>;
+ };
+
+};
+
+&pllss_clocks {
+
+ aud_clkin0_ck: aud_clkin0_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
+ aud_clkin1_ck: aud_clkin1_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
+ aud_clkin2_ck: aud_clkin2_ck {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <20000000>;
+ };
+
+ timer1_mux_ck: timer1_mux_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
+ &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
+ ti,bit-shift = <3>;
+ reg = <0x2e0>;
+ };
+
+ timer2_mux_ck: timer2_mux_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sysclk18_ck &aud_clkin0_ck &aud_clkin1_ck
+ &aud_clkin2_ck &devosc_ck &auxosc_ck &tclkin_ck>;
+ ti,bit-shift = <6>;
+ reg = <0x2e0>;
+ };
+};
diff --git a/dts/src/arm/dm814x.dtsi b/dts/src/arm/dm814x.dtsi
new file mode 100644
index 0000000..972c9c9
--- /dev/null
+++ b/dts/src/arm/dm814x.dtsi
@@ -0,0 +1,333 @@
+/*
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/omap.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "ti,dm814";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ i2c0 = &i2c1;
+ i2c1 = &i2c2;
+ serial0 = &uart1;
+ serial1 = &uart2;
+ serial2 = &uart3;
+ ethernet0 = &cpsw_emac0;
+ ethernet1 = &cpsw_emac1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a8-pmu";
+ interrupts = <3>;
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is used for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ ocp {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ /*
+ * See TRM "Table 1-317. L4LS Instance Summary", just deduct
+ * 0x1000 from the 1-317 addresses to get the device address
+ */
+ l4ls: l4ls@48000000 {
+ compatible = "ti,dm814-l4ls", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48000000 0x2000000>;
+
+ i2c1: i2c@28000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ reg = <0x28000 0x1000>;
+ interrupts = <70>;
+ };
+
+ elm: elm@80000 {
+ compatible = "ti,814-elm";
+ ti,hwmods = "elm";
+ reg = <0x80000 0x2000>;
+ interrupts = <4>;
+ };
+
+ gpio1: gpio@32000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio1";
+ ti,gpio-always-on;
+ reg = <0x32000 0x2000>;
+ interrupts = <96>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@4c000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio2";
+ ti,gpio-always-on;
+ reg = <0x4c000 0x2000>;
+ interrupts = <98>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2c2: i2c@2a000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ reg = <0x2a000 0x1000>;
+ interrupts = <71>;
+ };
+
+ mcspi1: spi@30000 {
+ compatible = "ti,omap4-mcspi";
+ reg = <0x30000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <65>;
+ ti,spi-num-cs = <4>;
+ ti,hwmods = "mcspi1";
+ dmas = <&edma 16 &edma 17
+ &edma 18 &edma 19>;
+ dma-names = "tx0", "rx0", "tx1", "rx1";
+ };
+
+ timer1: timer@2e000 {
+ compatible = "ti,dm814-timer";
+ reg = <0x2e000 0x2000>;
+ interrupts = <67>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ uart1: uart@20000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart1";
+ reg = <0x20000 0x2000>;
+ clock-frequency = <48000000>;
+ interrupts = <72>;
+ dmas = <&edma 26 &edma 27>;
+ dma-names = "tx", "rx";
+ };
+
+ uart2: uart@22000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart2";
+ reg = <0x22000 0x2000>;
+ clock-frequency = <48000000>;
+ interrupts = <73>;
+ dmas = <&edma 28 &edma 29>;
+ dma-names = "tx", "rx";
+ };
+
+ uart3: uart@24000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart3";
+ reg = <0x24000 0x2000>;
+ clock-frequency = <48000000>;
+ interrupts = <74>;
+ dmas = <&edma 30 &edma 31>;
+ dma-names = "tx", "rx";
+ };
+
+ timer2: timer@40000 {
+ compatible = "ti,dm814-timer";
+ reg = <0x40000 0x2000>;
+ interrupts = <68>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@42000 {
+ compatible = "ti,dm814-timer";
+ reg = <0x42000 0x2000>;
+ interrupts = <69>;
+ ti,hwmods = "timer3";
+ };
+
+ control: control@160000 {
+ compatible = "ti,dm814-scm", "simple-bus";
+ reg = <0x160000 0x16d000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x160000 0x16d000>;
+
+ scm_conf: scm_conf@0 {
+ compatible = "syscon";
+ reg = <0x0 0x800>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ scm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ scm_clockdomains: clockdomains {
+ };
+ };
+
+ pincntl: pinmux@800 {
+ compatible = "pinctrl-single";
+ reg = <0x800 0xc38>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x300ff>;
+ };
+ };
+
+ prcm: prcm@180000 {
+ compatible = "ti,dm814-prcm", "simple-bus";
+ reg = <0x180000 0x4000>;
+
+ prcm_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ prcm_clockdomains: clockdomains {
+ };
+ };
+
+ pllss: pllss@1c5000 {
+ compatible = "ti,dm814-pllss", "simple-bus";
+ reg = <0x1c5000 0x2000>;
+
+ pllss_clocks: clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ pllss_clockdomains: clockdomains {
+ };
+ };
+
+ wdt1: wdt@1c7000 {
+ compatible = "ti,omap3-wdt";
+ ti,hwmods = "wd_timer";
+ reg = <0x1c7000 0x1000>;
+ interrupts = <91>;
+ };
+ };
+
+ intc: interrupt-controller@48200000 {
+ compatible = "ti,dm814-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x48200000 0x1000>;
+ };
+
+ edma: edma@49000000 {
+ compatible = "ti,edma3";
+ ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
+ reg = <0x49000000 0x10000>,
+ <0x44e10f90 0x40>;
+ interrupts = <12 13 14>;
+ #dma-cells = <1>;
+ };
+
+ /* See TRM "Table 1-318. L4HS Instance Summary" */
+ l4hs: l4hs@4a000000 {
+ compatible = "ti,dm814-l4hs", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4a000000 0x1b4040>;
+ };
+
+ /* REVISIT: Move to live under l4hs once driver is fixed */
+ mac: ethernet@4a100000 {
+ compatible = "ti,cpsw";
+ ti,hwmods = "cpgmac0";
+ clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
+ clock-names = "fck", "cpts";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ no_bd_ram = <0>;
+ rx_descs = <64>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ reg = <0x4a100000 0x800
+ 0x4a100900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ /*
+ * c0_rx_thresh_pend
+ * c0_rx_pend
+ * c0_tx_pend
+ * c0_misc_pend
+ */
+ interrupts = <40 41 42 43>;
+ ranges;
+ syscon = <&scm_conf>;
+
+ davinci_mdio: mdio@4a100800 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ reg = <0x4a100800 0x100>;
+ };
+
+ cpsw_emac0: slave@4a100200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@4a100300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ phy_sel: cpsw-phy-sel@0x48160650 {
+ compatible = "ti,am3352-cpsw-phy-sel";
+ reg= <0x48160650 0x4>;
+ reg-names = "gmii-sel";
+ };
+ };
+ };
+};
+
+#include "dm814x-clocks.dtsi"
diff --git a/dts/src/arm/dm816x.dtsi b/dts/src/arm/dm816x.dtsi
index 289806a..3c99cfa 100644
--- a/dts/src/arm/dm816x.dtsi
+++ b/dts/src/arm/dm816x.dtsi
@@ -58,7 +58,7 @@
* the whole bus hierarchy.
*/
ocp {
- compatible = "ti,omap3-l3-smx", "simple-bus";
+ compatible = "simple-bus";
reg = <0x44000000 0x10000>;
interrupts = <9 10>;
#address-cells = <1>;
diff --git a/dts/src/arm/dove.dtsi b/dts/src/arm/dove.dtsi
index 38b1f7e..1791216 100644
--- a/dts/src/arm/dove.dtsi
+++ b/dts/src/arm/dove.dtsi
@@ -419,293 +419,325 @@
status = "disabled";
};
- thermal: thermal-diode@d001c {
- compatible = "marvell,dove-thermal";
- reg = <0xd001c 0x0c>, <0xd005c 0x08>;
- };
-
- gate_clk: clock-gating-ctrl@d0038 {
- compatible = "marvell,dove-gating-clock";
- reg = <0xd0038 0x4>;
- clocks = <&core_clk 0>;
- #clock-cells = <1>;
- };
-
- pinctrl: pin-ctrl@d0200 {
- compatible = "marvell,dove-pinctrl";
- reg = <0xd0200 0x14>,
- <0xd0440 0x04>;
- clocks = <&gate_clk 22>;
-
- pmx_gpio_0: pmx-gpio-0 {
- marvell,pins = "mpp0";
- marvell,function = "gpio";
- };
-
- pmx_gpio_1: pmx-gpio-1 {
- marvell,pins = "mpp1";
- marvell,function = "gpio";
- };
-
- pmx_gpio_2: pmx-gpio-2 {
- marvell,pins = "mpp2";
- marvell,function = "gpio";
- };
-
- pmx_gpio_3: pmx-gpio-3 {
- marvell,pins = "mpp3";
- marvell,function = "gpio";
- };
-
- pmx_gpio_4: pmx-gpio-4 {
- marvell,pins = "mpp4";
- marvell,function = "gpio";
- };
-
- pmx_gpio_5: pmx-gpio-5 {
- marvell,pins = "mpp5";
- marvell,function = "gpio";
- };
-
- pmx_gpio_6: pmx-gpio-6 {
- marvell,pins = "mpp6";
- marvell,function = "gpio";
- };
-
- pmx_gpio_7: pmx-gpio-7 {
- marvell,pins = "mpp7";
- marvell,function = "gpio";
- };
-
- pmx_gpio_8: pmx-gpio-8 {
- marvell,pins = "mpp8";
- marvell,function = "gpio";
- };
-
- pmx_gpio_9: pmx-gpio-9 {
- marvell,pins = "mpp9";
- marvell,function = "gpio";
- };
-
- pmx_pcie1_clkreq: pmx-pcie1-clkreq {
- marvell,pins = "mpp9";
- marvell,function = "pex1";
- };
-
- pmx_gpio_10: pmx-gpio-10 {
- marvell,pins = "mpp10";
- marvell,function = "gpio";
- };
-
- pmx_gpio_11: pmx-gpio-11 {
- marvell,pins = "mpp11";
- marvell,function = "gpio";
- };
-
- pmx_pcie0_clkreq: pmx-pcie0-clkreq {
- marvell,pins = "mpp11";
- marvell,function = "pex0";
- };
-
- pmx_gpio_12: pmx-gpio-12 {
- marvell,pins = "mpp12";
- marvell,function = "gpio";
- };
-
- pmx_gpio_13: pmx-gpio-13 {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
-
- pmx_audio1_extclk: pmx-audio1-extclk {
- marvell,pins = "mpp13";
- marvell,function = "audio1";
- };
-
- pmx_gpio_14: pmx-gpio-14 {
- marvell,pins = "mpp14";
- marvell,function = "gpio";
- };
-
- pmx_gpio_15: pmx-gpio-15 {
- marvell,pins = "mpp15";
- marvell,function = "gpio";
- };
-
- pmx_gpio_16: pmx-gpio-16 {
- marvell,pins = "mpp16";
- marvell,function = "gpio";
- };
-
- pmx_gpio_17: pmx-gpio-17 {
- marvell,pins = "mpp17";
- marvell,function = "gpio";
- };
-
- pmx_gpio_18: pmx-gpio-18 {
- marvell,pins = "mpp18";
- marvell,function = "gpio";
- };
-
- pmx_gpio_19: pmx-gpio-19 {
- marvell,pins = "mpp19";
- marvell,function = "gpio";
- };
-
- pmx_gpio_20: pmx-gpio-20 {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
-
- pmx_gpio_21: pmx-gpio-21 {
- marvell,pins = "mpp21";
- marvell,function = "gpio";
- };
-
- pmx_camera: pmx-camera {
- marvell,pins = "mpp_camera";
- marvell,function = "camera";
- };
-
- pmx_camera_gpio: pmx-camera-gpio {
- marvell,pins = "mpp_camera";
- marvell,function = "gpio";
- };
-
- pmx_sdio0: pmx-sdio0 {
- marvell,pins = "mpp_sdio0";
- marvell,function = "sdio0";
- };
-
- pmx_sdio0_gpio: pmx-sdio0-gpio {
- marvell,pins = "mpp_sdio0";
- marvell,function = "gpio";
- };
-
- pmx_sdio1: pmx-sdio1 {
- marvell,pins = "mpp_sdio1";
- marvell,function = "sdio1";
- };
-
- pmx_sdio1_gpio: pmx-sdio1-gpio {
- marvell,pins = "mpp_sdio1";
- marvell,function = "gpio";
- };
-
- pmx_audio1_gpio: pmx-audio1-gpio {
- marvell,pins = "mpp_audio1";
- marvell,function = "gpio";
- };
-
- pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
- marvell,pins = "mpp_audio1";
- marvell,function = "i2s1/spdifo";
- };
-
- pmx_spi0: pmx-spi0 {
- marvell,pins = "mpp_spi0";
- marvell,function = "spi0";
- };
-
- pmx_spi0_gpio: pmx-spi0-gpio {
- marvell,pins = "mpp_spi0";
- marvell,function = "gpio";
- };
-
- pmx_spi1_4_7: pmx-spi1-4-7 {
- marvell,pins = "mpp4", "mpp5",
- "mpp6", "mpp7";
- marvell,function = "spi1";
- };
-
- pmx_spi1_20_23: pmx-spi1-20-23 {
- marvell,pins = "mpp20", "mpp21",
- "mpp22", "mpp23";
- marvell,function = "spi1";
- };
-
- pmx_uart1: pmx-uart1 {
- marvell,pins = "mpp_uart1";
- marvell,function = "uart1";
- };
-
- pmx_uart1_gpio: pmx-uart1-gpio {
- marvell,pins = "mpp_uart1";
- marvell,function = "gpio";
- };
-
- pmx_nand: pmx-nand {
- marvell,pins = "mpp_nand";
- marvell,function = "nand";
- };
-
- pmx_nand_gpo: pmx-nand-gpo {
- marvell,pins = "mpp_nand";
- marvell,function = "gpo";
- };
-
- pmx_i2c1: pmx-i2c1 {
- marvell,pins = "mpp17", "mpp19";
- marvell,function = "twsi";
- };
-
- pmx_i2c2: pmx-i2c2 {
- marvell,pins = "mpp_audio1";
- marvell,function = "twsi";
- };
-
- pmx_ssp_i2c2: pmx-ssp-i2c2 {
- marvell,pins = "mpp_audio1";
- marvell,function = "ssp/twsi";
- };
-
- pmx_i2cmux_0: pmx-i2cmux-0 {
- marvell,pins = "twsi";
- marvell,function = "twsi-opt1";
- };
-
- pmx_i2cmux_1: pmx-i2cmux-1 {
- marvell,pins = "twsi";
- marvell,function = "twsi-opt2";
- };
-
- pmx_i2cmux_2: pmx-i2cmux-2 {
- marvell,pins = "twsi";
- marvell,function = "twsi-opt3";
- };
- };
-
- core_clk: core-clocks@d0214 {
- compatible = "marvell,dove-core-clock";
- reg = <0xd0214 0x4>;
- #clock-cells = <1>;
- };
-
- gpio0: gpio-ctrl@d0400 {
- compatible = "marvell,orion-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0xd0400 0x20>;
- ngpios = <32>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <12>, <13>, <14>, <60>;
- };
-
- gpio1: gpio-ctrl@d0420 {
- compatible = "marvell,orion-gpio";
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0xd0420 0x20>;
- ngpios = <32>;
+ pmu: power-management@d0000 {
+ compatible = "marvell,dove-pmu", "simple-bus";
+ reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
+ ranges = <0x00000000 0x000d0000 0x8000
+ 0x00008000 0x000d8000 0x8000>;
+ interrupts = <33>;
interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <61>;
- };
-
- rtc: real-time-clock@d8500 {
- compatible = "marvell,orion-rtc";
- reg = <0xd8500 0x20>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <1>;
+ #reset-cells = <1>;
+
+ domains {
+ vpu_domain: vpu-domain {
+ #power-domain-cells = <0>;
+ marvell,pmu_pwr_mask = <0x00000008>;
+ marvell,pmu_iso_mask = <0x00000001>;
+ resets = <&pmu 16>;
+ };
+
+ gpu_domain: gpu-domain {
+ #power-domain-cells = <0>;
+ marvell,pmu_pwr_mask = <0x00000004>;
+ marvell,pmu_iso_mask = <0x00000002>;
+ resets = <&pmu 18>;
+ };
+ };
+
+ thermal: thermal-diode@001c {
+ compatible = "marvell,dove-thermal";
+ reg = <0x001c 0x0c>, <0x005c 0x08>;
+ };
+
+ gate_clk: clock-gating-ctrl@0038 {
+ compatible = "marvell,dove-gating-clock";
+ reg = <0x0038 0x4>;
+ clocks = <&core_clk 0>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pin-ctrl@0200 {
+ compatible = "marvell,dove-pinctrl";
+ reg = <0x0200 0x14>,
+ <0x0440 0x04>;
+ clocks = <&gate_clk 22>;
+
+ pmx_gpio_0: pmx-gpio-0 {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_1: pmx-gpio-1 {
+ marvell,pins = "mpp1";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_2: pmx-gpio-2 {
+ marvell,pins = "mpp2";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_3: pmx-gpio-3 {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_4: pmx-gpio-4 {
+ marvell,pins = "mpp4";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_5: pmx-gpio-5 {
+ marvell,pins = "mpp5";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_6: pmx-gpio-6 {
+ marvell,pins = "mpp6";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_7: pmx-gpio-7 {
+ marvell,pins = "mpp7";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_8: pmx-gpio-8 {
+ marvell,pins = "mpp8";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_9: pmx-gpio-9 {
+ marvell,pins = "mpp9";
+ marvell,function = "gpio";
+ };
+
+ pmx_pcie1_clkreq: pmx-pcie1-clkreq {
+ marvell,pins = "mpp9";
+ marvell,function = "pex1";
+ };
+
+ pmx_gpio_10: pmx-gpio-10 {
+ marvell,pins = "mpp10";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_11: pmx-gpio-11 {
+ marvell,pins = "mpp11";
+ marvell,function = "gpio";
+ };
+
+ pmx_pcie0_clkreq: pmx-pcie0-clkreq {
+ marvell,pins = "mpp11";
+ marvell,function = "pex0";
+ };
+
+ pmx_gpio_12: pmx-gpio-12 {
+ marvell,pins = "mpp12";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_13: pmx-gpio-13 {
+ marvell,pins = "mpp13";
+ marvell,function = "gpio";
+ };
+
+ pmx_audio1_extclk: pmx-audio1-extclk {
+ marvell,pins = "mpp13";
+ marvell,function = "audio1";
+ };
+
+ pmx_gpio_14: pmx-gpio-14 {
+ marvell,pins = "mpp14";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_15: pmx-gpio-15 {
+ marvell,pins = "mpp15";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_16: pmx-gpio-16 {
+ marvell,pins = "mpp16";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_17: pmx-gpio-17 {
+ marvell,pins = "mpp17";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_18: pmx-gpio-18 {
+ marvell,pins = "mpp18";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_19: pmx-gpio-19 {
+ marvell,pins = "mpp19";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_20: pmx-gpio-20 {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+
+ pmx_gpio_21: pmx-gpio-21 {
+ marvell,pins = "mpp21";
+ marvell,function = "gpio";
+ };
+
+ pmx_camera: pmx-camera {
+ marvell,pins = "mpp_camera";
+ marvell,function = "camera";
+ };
+
+ pmx_camera_gpio: pmx-camera-gpio {
+ marvell,pins = "mpp_camera";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio0: pmx-sdio0 {
+ marvell,pins = "mpp_sdio0";
+ marvell,function = "sdio0";
+ };
+
+ pmx_sdio0_gpio: pmx-sdio0-gpio {
+ marvell,pins = "mpp_sdio0";
+ marvell,function = "gpio";
+ };
+
+ pmx_sdio1: pmx-sdio1 {
+ marvell,pins = "mpp_sdio1";
+ marvell,function = "sdio1";
+ };
+
+ pmx_sdio1_gpio: pmx-sdio1-gpio {
+ marvell,pins = "mpp_sdio1";
+ marvell,function = "gpio";
+ };
+
+ pmx_audio1_gpio: pmx-audio1-gpio {
+ marvell,pins = "mpp_audio1";
+ marvell,function = "gpio";
+ };
+
+ pmx_audio1_i2s1_spdifo: pmx-audio1-i2s1-spdifo {
+ marvell,pins = "mpp_audio1";
+ marvell,function = "i2s1/spdifo";
+ };
+
+ pmx_spi0: pmx-spi0 {
+ marvell,pins = "mpp_spi0";
+ marvell,function = "spi0";
+ };
+
+ pmx_spi0_gpio: pmx-spi0-gpio {
+ marvell,pins = "mpp_spi0";
+ marvell,function = "gpio";
+ };
+
+ pmx_spi1_4_7: pmx-spi1-4-7 {
+ marvell,pins = "mpp4", "mpp5",
+ "mpp6", "mpp7";
+ marvell,function = "spi1";
+ };
+
+ pmx_spi1_20_23: pmx-spi1-20-23 {
+ marvell,pins = "mpp20", "mpp21",
+ "mpp22", "mpp23";
+ marvell,function = "spi1";
+ };
+
+ pmx_uart1: pmx-uart1 {
+ marvell,pins = "mpp_uart1";
+ marvell,function = "uart1";
+ };
+
+ pmx_uart1_gpio: pmx-uart1-gpio {
+ marvell,pins = "mpp_uart1";
+ marvell,function = "gpio";
+ };
+
+ pmx_nand: pmx-nand {
+ marvell,pins = "mpp_nand";
+ marvell,function = "nand";
+ };
+
+ pmx_nand_gpo: pmx-nand-gpo {
+ marvell,pins = "mpp_nand";
+ marvell,function = "gpo";
+ };
+
+ pmx_i2c1: pmx-i2c1 {
+ marvell,pins = "mpp17", "mpp19";
+ marvell,function = "twsi";
+ };
+
+ pmx_i2c2: pmx-i2c2 {
+ marvell,pins = "mpp_audio1";
+ marvell,function = "twsi";
+ };
+
+ pmx_ssp_i2c2: pmx-ssp-i2c2 {
+ marvell,pins = "mpp_audio1";
+ marvell,function = "ssp/twsi";
+ };
+
+ pmx_i2cmux_0: pmx-i2cmux-0 {
+ marvell,pins = "twsi";
+ marvell,function = "twsi-opt1";
+ };
+
+ pmx_i2cmux_1: pmx-i2cmux-1 {
+ marvell,pins = "twsi";
+ marvell,function = "twsi-opt2";
+ };
+
+ pmx_i2cmux_2: pmx-i2cmux-2 {
+ marvell,pins = "twsi";
+ marvell,function = "twsi-opt3";
+ };
+ };
+
+ core_clk: core-clocks@0214 {
+ compatible = "marvell,dove-core-clock";
+ reg = <0x0214 0x4>;
+ #clock-cells = <1>;
+ };
+
+ gpio0: gpio-ctrl@0400 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x0400 0x20>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <12>, <13>, <14>, <60>;
+ };
+
+ gpio1: gpio-ctrl@0420 {
+ compatible = "marvell,orion-gpio";
+ #gpio-cells = <2>;
+ gpio-controller;
+ reg = <0x0420 0x20>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <61>;
+ };
+
+ rtc: real-time-clock@8500 {
+ compatible = "marvell,orion-rtc";
+ reg = <0x8500 0x20>;
+ interrupts = <5>;
+ };
};
gconf: global-config@e802c {
diff --git a/dts/src/arm/dra7-evm.dts b/dts/src/arm/dra7-evm.dts
index 096f68b..a6c82e5 100644
--- a/dts/src/arm/dra7-evm.dts
+++ b/dts/src/arm/dra7-evm.dts
@@ -19,6 +19,15 @@
reg = <0x80000000 0x60000000>; /* 1536 MB */
};
+ evm_3v3_sd: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "evm_3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ enable-active-high;
+ gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>;
+ };
+
mmc2_3v3: fixedregulator-mmc2 {
compatible = "regulator-fixed";
regulator-name = "mmc2_3v3";
@@ -349,6 +358,7 @@
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
regulator-boot-on;
};
@@ -462,8 +472,14 @@
&mmc1 {
status = "okay";
- vmmc-supply = <&ldo1_reg>;
+ vmmc-supply = <&evm_3v3_sd>;
+ vmmc_aux-supply = <&ldo1_reg>;
bus-width = <4>;
+ /*
+ * SDCD signal is not being used here - using the fact that GPIO mode
+ * is always hardwired.
+ */
+ cd-gpios = <&gpio6 27 0>;
};
&mmc2 {
diff --git a/dts/src/arm/dra7.dtsi b/dts/src/arm/dra7.dtsi
index 1e29ccf..5d65db9 100644
--- a/dts/src/arm/dra7.dtsi
+++ b/dts/src/arm/dra7.dtsi
@@ -141,7 +141,7 @@
dra7_pmx_core: pinmux@1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
- reg = <0x1400 0x0464>;
+ reg = <0x1400 0x0468>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
@@ -149,6 +149,11 @@
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
+
+ scm_conf1: scm_conf@1c04 {
+ compatible = "syscon";
+ reg = <0x1c04 0x0020>;
+ };
};
cm_core_aon: cm_core_aon@5000 {
@@ -211,7 +216,7 @@
#address-cells = <1>;
ranges = <0x51000000 0x51000000 0x3000
0x0 0x20000000 0x10000000>;
- pcie@51000000 {
+ pcie1: pcie@51000000 {
compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
@@ -286,16 +291,6 @@
#thermal-sensor-cells = <1>;
};
- dra7_ctrl_core: ctrl_core@4a002000 {
- compatible = "syscon";
- reg = <0x4a002000 0x6d0>;
- };
-
- dra7_ctrl_general: tisyscon@4a002e00 {
- compatible = "syscon";
- reg = <0x4a002e00 0x7c>;
- };
-
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
@@ -308,6 +303,15 @@
dma-requests = <127>;
};
+ sdma_xbar: dma-router@4a002b78 {
+ compatible = "ti,dra7-dma-crossbar";
+ reg = <0x4a002b78 0xfc>;
+ #dma-cells = <1>;
+ dma-requests = <205>;
+ ti,dma-safe-map = <0>;
+ dma-masters = <&sdma>;
+ };
+
gpio1: gpio@4ae10000 {
compatible = "ti,omap4-gpio";
reg = <0x4ae10000 0x200>;
@@ -397,73 +401,73 @@
};
uart1: serial@4806a000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806a000 0x100>;
interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart1";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 49>, <&sdma 50>;
+ dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
dma-names = "tx", "rx";
};
uart2: serial@4806c000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806c000 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart2";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 51>, <&sdma 52>;
+ dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
dma-names = "tx", "rx";
};
uart3: serial@48020000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48020000 0x100>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart3";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 53>, <&sdma 54>;
+ dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
dma-names = "tx", "rx";
};
uart4: serial@4806e000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x4806e000 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart4";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 55>, <&sdma 56>;
+ dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
dma-names = "tx", "rx";
};
uart5: serial@48066000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48066000 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart5";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 63>, <&sdma 64>;
+ dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
dma-names = "tx", "rx";
};
uart6: serial@48068000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48068000 0x100>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "uart6";
clock-frequency = <48000000>;
status = "disabled";
- dmas = <&sdma 79>, <&sdma 80>;
+ dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
dma-names = "tx", "rx";
};
uart7: serial@48420000 {
- compatible = "ti,omap4-uart";
+ compatible = "ti,dra742-uart", "ti,omap4-uart";
reg = <0x48420000 0x100>;
inter