diff options
| author | Lucas Stach <l.stach@pengutronix.de> | 2023-02-02 13:05:24 +0100 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2023-02-03 08:59:46 +0100 |
| commit | d86bbaed71cf8928575b40e4bfa904cded5fa2d2 (patch) | |
| tree | 45b7111436d00efadbafd5bc70c33f29bf0bf98a | |
| parent | f6f5cbfef751f728bfa985f846fab468d222a019 (diff) | |
| download | barebox-d86bbaed71cf8928575b40e4bfa904cded5fa2d2.tar.gz barebox-d86bbaed71cf8928575b40e4bfa904cded5fa2d2.tar.xz | |
clk: imx8mp: add USB suspend clock
Linux added another USB clock to properly describe the controller root
and suspend clocks. As new DTs are using this clock to keep the shared
gate enabled, access to the USB controller will hang Barebox without
support for this clock.
Fixes: 0d682a2997a8 ("dts: update to v6.2-rc5")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Link: https://lore.barebox.org/20230202120524.469258-1-l.stach@pengutronix.de
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| -rw-r--r-- | drivers/clk/imx/clk-imx8mp.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c index a1611be183..40578c2a4b 100644 --- a/drivers/clk/imx/clk-imx8mp.c +++ b/drivers/clk/imx/clk-imx8mp.c @@ -665,7 +665,8 @@ static int imx8mp_clocks_init(struct device_node *ccm_np) hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk", "uart2", ccm_base + 0x44a0, 0); hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk", "uart3", ccm_base + 0x44b0, 0); hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk", "uart4", ccm_base + 0x44c0, 0); - hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk", "osc_32k", ccm_base + 0x44d0, 0); + hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk", "hsio_axi", ccm_base + 0x44d0, 0); + hws[IMX8MP_CLK_USB_SUSP] = imx_clk_hw_gate2_shared2("usb_suspend_clk", "osc_32k", ccm_base + 0x44d0, 0); hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk", "usb_phy_ref", ccm_base + 0x44f0, 0); hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk", "usdhc1", ccm_base + 0x4510, 0); hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk", "usdhc2", ccm_base + 0x4520, 0); |