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authorSascha Hauer <s.hauer@pengutronix.de>2020-05-14 07:11:20 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2020-05-14 07:11:20 +0200
commitc10b20dc83ac25b1d81c39eaad4529d9911813b1 (patch)
tree6558720fa869c01d7093b3df721dedaaec06cb5f /arch
parent9b01acf90f04aaf3f6f41875e91272cbeac51171 (diff)
parent2c42da39a91238cc16f87c2867c8a5ea7847f99c (diff)
downloadbarebox-master.tar.gz
Merge branch 'for-next/stm32'HEADmaster
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-stm32mp/include/mach/bsec.h6
-rw-r--r--arch/arm/mach-stm32mp/include/mach/revision.h18
-rw-r--r--arch/arm/mach-stm32mp/init.c123
3 files changed, 136 insertions, 11 deletions
diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h
index 559faaa..d3cb91b 100644
--- a/arch/arm/mach-stm32mp/include/mach/bsec.h
+++ b/arch/arm/mach-stm32mp/include/mach/bsec.h
@@ -17,7 +17,7 @@ enum bsec_smc {
};
/* Service for BSEC */
-enum bsec_field {
+enum bsec_op {
BSEC_SMC_READ_SHADOW = 1,
BSEC_SMC_PROG_OTP = 2,
BSEC_SMC_WRITE_SHADOW = 3,
@@ -26,13 +26,13 @@ enum bsec_field {
BSEC_SMC_WRITE_ALL = 6,
};
-static inline enum bsec_smc bsec_read_field(enum bsec_field field, unsigned *val)
+static inline enum bsec_smc bsec_read_field(unsigned field, unsigned *val)
{
return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW,
field, 0, val);
}
-static inline enum bsec_smc bsec_write_field(enum bsec_field field, unsigned val)
+static inline enum bsec_smc bsec_write_field(unsigned field, unsigned val)
{
return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW,
field, val, NULL);
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
index 3872014..2eb4d44 100644
--- a/arch/arm/mach-stm32mp/include/mach/revision.h
+++ b/arch/arm/mach-stm32mp/include/mach/revision.h
@@ -6,17 +6,33 @@
#ifndef __MACH_CPUTYPE_H__
#define __MACH_CPUTYPE_H__
-/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
+
+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit7:0)
+ * 157X: 2x Cortex-A7, Cortex-M4, CAN FD, GPU, DSI
+ * 153X: 2x Cortex-A7, Cortex-M4, CAN FD
+ * 151X: 1x Cortex-A7, Cortex-M4
+ * XXXA: Cortex-A7 @ 650 MHz
+ * XXXC: Cortex-A7 @ 650 MHz + Secure Boot + HW Crypto
+ * XXXD: Cortex-A7 @ 800 MHz
+ * XXXF: Cortex-A7 @ 800 MHz + Secure Boot + HW Crypto
+ */
#define CPU_STM32MP157Cxx 0x05000000
#define CPU_STM32MP157Axx 0x05000001
#define CPU_STM32MP153Cxx 0x05000024
#define CPU_STM32MP153Axx 0x05000025
#define CPU_STM32MP151Cxx 0x0500002E
#define CPU_STM32MP151Axx 0x0500002F
+#define CPU_STM32MP157Fxx 0x05000080
+#define CPU_STM32MP157Dxx 0x05000081
+#define CPU_STM32MP153Fxx 0x050000A4
+#define CPU_STM32MP153Dxx 0x050000A5
+#define CPU_STM32MP151Fxx 0x050000AE
+#define CPU_STM32MP151Dxx 0x050000AF
/* silicon revisions */
#define CPU_REV_A 0x1000
#define CPU_REV_B 0x2000
+#define CPU_REV_Z 0x2001
int stm32mp_silicon_revision(void);
int stm32mp_cputype(void);
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
index 7bad989..7f687fa 100644
--- a/arch/arm/mach-stm32mp/init.c
+++ b/arch/arm/mach-stm32mp/init.c
@@ -13,6 +13,7 @@
#include <mach/revision.h>
#include <mach/bootsource.h>
#include <bootsource.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/* DBGMCU register */
#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
@@ -75,6 +76,9 @@
#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
#define TAMP_BOOT_DEBUG_ON BIT(16)
+#define FIXUP_CPU_MASK(num, mhz) (((num) << 16) | (mhz))
+#define FIXUP_CPU_NUM(mask) ((mask) >> 16)
+#define FIXUP_CPU_HZ(mask) (((mask) & GENMASK(15, 0)) * 1000UL * 1000UL)
static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode;
enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void)
@@ -155,7 +159,7 @@ static inline u32 read_idc(void)
}
/* Get Device Part Number (RPN) from OTP */
-static u32 get_cpu_rpn(u32 *rpn)
+static int get_cpu_rpn(u32 *rpn)
{
int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
if (ret)
@@ -170,7 +174,7 @@ static u32 get_cpu_revision(void)
return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
}
-static u32 get_cpu_type(u32 *type)
+static int get_cpu_type(u32 *type)
{
u32 id;
int ret = get_cpu_rpn(type);
@@ -192,30 +196,109 @@ static int get_cpu_package(u32 *pkg)
return 0;
}
+static int stm32mp15_fixup_cpus(struct device_node *root, void *_ctx)
+{
+ unsigned long ctx = (unsigned long)_ctx;
+ struct device_node *cpus_node, *np, *tmp;
+
+ cpus_node = of_find_node_by_name(root, "cpus");
+ if (!cpus_node)
+ return 0;
+
+ for_each_child_of_node_safe(cpus_node, tmp, np) {
+ u32 cpu_index;
+
+ if (of_property_read_u32(np, "reg", &cpu_index))
+ continue;
+
+ if (cpu_index >= FIXUP_CPU_NUM(ctx)) {
+ of_delete_node(np);
+ continue;
+ }
+
+ of_property_write_u32(np, "clock-frequency", FIXUP_CPU_HZ(ctx));
+ }
+
+ return 0;
+}
+
+static int fixup_pinctrl(struct device_node *root, const char *compat, u32 pkg)
+{
+ struct device_node *np = of_find_compatible_node(root, NULL, compat);
+ if (!np)
+ return -ENODEV;
+
+ return of_property_write_u32(np, "st,package", pkg);
+}
+
+static int stm32mp15_fixup_pkg(struct device_node *root, void *_pkg)
+{
+ unsigned long pkg = (unsigned long)_pkg;
+ int ret;
+
+ ret = fixup_pinctrl(root, "st,stm32mp157-pinctrl", pkg);
+ if (ret)
+ return ret;
+
+ return fixup_pinctrl(root, "st,stm32mp157-z-pinctrl", pkg);
+}
+
static int setup_cpu_type(void)
{
- const char *cputypestr;
- const char *cpupkgstr;
+ const char *cputypestr, *cpupkgstr, *cpurevstr;
+ unsigned long cpufixupctx = 0, pkgfixupctx = 0;
+ u32 pkg;
+ int ret;
get_cpu_type(&__stm32mp_cputype);
switch (__stm32mp_cputype) {
+ case CPU_STM32MP157Fxx:
+ cputypestr = "157F";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
+ break;
+ case CPU_STM32MP157Dxx:
+ cputypestr = "157D";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
+ break;
case CPU_STM32MP157Cxx:
cputypestr = "157C";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP157Axx:
cputypestr = "157A";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
+ break;
+ case CPU_STM32MP153Fxx:
+ cputypestr = "153F";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
+ break;
+ case CPU_STM32MP153Dxx:
+ cputypestr = "153D";
+ cpufixupctx = FIXUP_CPU_MASK(2, 800);
break;
case CPU_STM32MP153Cxx:
cputypestr = "153C";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP153Axx:
cputypestr = "153A";
+ cpufixupctx = FIXUP_CPU_MASK(2, 650);
break;
case CPU_STM32MP151Cxx:
cputypestr = "151C";
+ cpufixupctx = FIXUP_CPU_MASK(1, 650);
break;
case CPU_STM32MP151Axx:
cputypestr = "151A";
+ cpufixupctx = FIXUP_CPU_MASK(1, 650);
+ break;
+ case CPU_STM32MP151Fxx:
+ cputypestr = "151F";
+ cpufixupctx = FIXUP_CPU_MASK(1, 800);
+ break;
+ case CPU_STM32MP151Dxx:
+ cputypestr = "151D";
+ cpufixupctx = FIXUP_CPU_MASK(1, 800);
break;
default:
cputypestr = "????";
@@ -226,15 +309,19 @@ static int setup_cpu_type(void)
switch (__stm32mp_package) {
case PKG_AA_LBGA448:
cpupkgstr = "AA";
+ pkgfixupctx = STM32MP_PKG_AA;
break;
case PKG_AB_LBGA354:
cpupkgstr = "AB";
+ pkgfixupctx = STM32MP_PKG_AB;
break;
case PKG_AC_TFBGA361:
cpupkgstr = "AC";
+ pkgfixupctx = STM32MP_PKG_AC;
break;
case PKG_AD_TFBGA257:
cpupkgstr = "AD";
+ pkgfixupctx = STM32MP_PKG_AD;
break;
default:
cpupkgstr = "??";
@@ -242,11 +329,33 @@ static int setup_cpu_type(void)
}
__stm32mp_silicon_revision = get_cpu_revision();
+ switch (__stm32mp_silicon_revision) {
+ case CPU_REV_A:
+ cpurevstr = "A";
+ break;
+ case CPU_REV_B:
+ cpurevstr = "B";
+ break;
+ case CPU_REV_Z:
+ cpurevstr = "Z";
+ break;
+ default:
+ cpurevstr = "?";
+ }
pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
- __stm32mp_cputype, __stm32mp_package, __stm32mp_silicon_revision);
- pr_info("detected STM32MP%s%s Rev.%c\n", cputypestr, cpupkgstr,
- (__stm32mp_silicon_revision >> 12) + 'A' - 1);
+ __stm32mp_cputype, pkg, __stm32mp_silicon_revision);
+ pr_info("detected STM32MP%s%s Rev.%s\n", cputypestr, cpupkgstr, cpurevstr);
+
+ if (cpufixupctx) {
+ ret = of_register_fixup(stm32mp15_fixup_cpus, (void*)cpufixupctx);
+ if (ret)
+ return ret;
+ }
+
+ if (pkgfixupctx)
+ return of_register_fixup(stm32mp15_fixup_pkg, (void*)pkgfixupctx);
+
return 0;
}