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authorSascha Hauer <s.hauer@pengutronix.de>2012-08-12 15:21:54 +0200
committerSascha Hauer <s.hauer@pengutronix.de>2012-08-13 20:27:38 +0200
commit837795895801e6c368a564f9dcbbda2c87137ea7 (patch)
tree632621b6a35fdb86042157ca392e42a6e1875b84 /arch/arm/cpu/cache-armv4.S
parente4e141159d5019006a85d4be5fb672a7e928dc38 (diff)
downloadbarebox-837795895801e6c368a564f9dcbbda2c87137ea7.tar.gz
barebox-837795895801e6c368a564f9dcbbda2c87137ea7.tar.xz
ARM __mmu_cache_*: Do not clobber registers
Save/restore the registers used in __mmu_cache_* so that they can be called as regular C functions. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/cache-armv4.S')
-rw-r--r--arch/arm/cpu/cache-armv4.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/cache-armv4.S b/arch/arm/cpu/cache-armv4.S
index 2231eee06b..22fab1455c 100644
--- a/arch/arm/cpu/cache-armv4.S
+++ b/arch/arm/cpu/cache-armv4.S
@@ -46,6 +46,7 @@ ENDPROC(__mmu_cache_off)
.section .text.__mmu_cache_flush
ENTRY(__mmu_cache_flush)
+ stmfd sp!, {r6, r11, lr}
mrc p15, 0, r6, c0, c0 @ get processor ID
mov r2, #64*1024 @ default: 32K dcache size (*2)
mov r11, #32 @ default: 32 byte line size
@@ -74,7 +75,7 @@ no_cache_id:
mcr p15, 0, r1, c7, c5, 0 @ flush I cache
mcr p15, 0, r1, c7, c6, 0 @ flush D cache
mcr p15, 0, r1, c7, c10, 4 @ drain WB
- mov pc, lr
+ ldmfd sp!, {r6, r11, pc}
ENDPROC(__mmu_cache_flush)
/*