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authorAndrey Smirnov <andrew.smirnov@gmail.com>2018-06-14 21:21:02 -0700
committerSascha Hauer <s.hauer@pengutronix.de>2018-06-18 08:59:04 +0200
commit9fe4ab90d0c8aab15fee9de78a804dd2d564f180 (patch)
tree67509b63a75da5e72b3e93a2f2817bc9db8a71d0 /arch/arm/cpu/mmu.c
parentb1f7b45ba88ea27529e4188f58f266adb54d700d (diff)
downloadbarebox-9fe4ab90d0c8aab15fee9de78a804dd2d564f180.tar.gz
barebox-9fe4ab90d0c8aab15fee9de78a804dd2d564f180.tar.xz
ARM: mmu: psci: Make use of get_ttbr()
Introduce a simple inline function to get TTBR and use it in mmu.c and sm.c Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/arm/cpu/mmu.c')
-rw-r--r--arch/arm/cpu/mmu.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/cpu/mmu.c b/arch/arm/cpu/mmu.c
index 7e2e5bf7e0..9e765514dc 100644
--- a/arch/arm/cpu/mmu.c
+++ b/arch/arm/cpu/mmu.c
@@ -453,10 +453,8 @@ static int mmu_init(void)
* Early MMU code has already enabled the MMU. We assume a
* flat 1:1 section mapping in this case.
*/
- asm volatile ("mrc p15,0,%0,c2,c0,0" : "=r"(ttb));
-
/* Clear unpredictable bits [13:0] */
- ttb = (uint32_t *)((unsigned long)ttb & ~0x3fff);
+ ttb = (uint32_t *)(get_ttbr() & ~0x3fff);
if (!request_sdram_region("ttb", (unsigned long)ttb, SZ_16K))
/*