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author | Antony Pavlov <antonynpavlov@gmail.com> | 2013-01-26 20:52:37 +0400 |
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committer | Sascha Hauer <s.hauer@pengutronix.de> | 2013-01-27 22:41:27 +0100 |
commit | ee3e2a83927dc4123e3acd970ccfcad2b6a4d059 (patch) | |
tree | 7504063ef5c74904be3eb5b625321a7ca2ff981d /arch/mips/boards/qemu-malta/init.c | |
parent | 1e8c9c5a4a1927b8e94769945d5d436ef9aa0754 (diff) | |
download | barebox-ee3e2a83927dc4123e3acd970ccfcad2b6a4d059.tar.gz barebox-ee3e2a83927dc4123e3acd970ccfcad2b6a4d059.tar.xz |
MIPS: introduce ram0 regions register function
On MIPS there are two segments in CPU address space that
can be used for untranslated memory access: KSEG0 and KSEG1.
KSEG0 is used for cached access and KSEG1 is used for
uncached one.
The instroduced mips_add_ram0() function registers two
address regions for memory access: one in KSEG0 and
the other one in KSEG1.
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/mips/boards/qemu-malta/init.c')
0 files changed, 0 insertions, 0 deletions