diff options
| author | Barbier, Renaud <renaud.barbier@abaco.com> | 2019-04-15 12:35:23 +0000 |
|---|---|---|
| committer | Sascha Hauer <s.hauer@pengutronix.de> | 2019-05-08 11:05:33 +0200 |
| commit | aa4882a29b21123df67a4a56e70758fc4fc6c5ee (patch) | |
| tree | bac420ed160f4d0b0c946e16b22df0dde3869222 /arch/ppc/boards/owc-da923rc/config.h | |
| parent | ea569a0afd6a2e9a84418cd18ddeaeefaa5eae39 (diff) | |
| download | barebox-aa4882a29b21123df67a4a56e70758fc4fc6c5ee.tar.gz barebox-aa4882a29b21123df67a4a56e70758fc4fc6c5ee.tar.xz | |
owc: directories and files renaming
As the company changed name to Abaco Systems Inc, we have
a contractual requirement to remove GE references. Start by
renaming files and directories using a neutral name.
Signed-off-by: Renaud Barbier <renaud.barbier@abaco.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch/ppc/boards/owc-da923rc/config.h')
| -rw-r--r-- | arch/ppc/boards/owc-da923rc/config.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/ppc/boards/owc-da923rc/config.h b/arch/ppc/boards/owc-da923rc/config.h new file mode 100644 index 0000000000..3895324e95 --- /dev/null +++ b/arch/ppc/boards/owc-da923rc/config.h @@ -0,0 +1,53 @@ +/* + * Copyright 2013 GE Intelligent Platforms, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * DA923RC board configuration file. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CFG_SYS_CLK_FREQ 66666666 + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CFG_CHIP_SELECTS_PER_CTRL 1 + +/* + * Memory map + * + * 0x0000_0000 0x1fff_ffff DDR 512MB Cacheable + * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable + * 0xf400_0000 0xf400_3fff L1 for stack 4K Cacheable TLB0 + * + */ +#define CFG_SDRAM_BASE 0x00000000 + +#define CFG_CCSRBAR_DEFAULT 0xff700000 +#define CFG_CCSRBAR 0xe0000000 +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR +#define CFG_IMMR CFG_CCSRBAR + +/* Initial memory for global storage and stack. */ +#define CFG_INIT_RAM_ADDR 0xf4000000 +#define CFG_INIT_RAM_SIZE 0x00004000 +#define CFG_INIT_BI_SIZE 0x100 +#define CFG_INIT_SP_OFFSET (CFG_INIT_RAM_SIZE - CFG_INIT_BI_SIZE) + +#define BOOT_BLOCK 0xfc000000 + +#define BOARD_TYPE_UNKNOWN -1 +#define BOARD_TYPE_NONE 0 +#define BOARD_TYPE_DA923 1 +#define BOARD_TYPE_GBX460 2 + +#endif /* __CONFIG_H */ |